Switched capacitor cascade three-phase four-leg boost inverter configuration

Abstract

The invention discloses a switch capacitor cascade three-phase four-bridge arm boost inverter configuration which comprises a switch capacitor circuit and a three-phase four-bridge arm inverter circuit, and the switch capacitor circuit is connected with the three-phase four-bridge arm inverter circuit. The switched capacitor circuit comprises a controlled switch tube S1, a controlled switch tube S2, a diode D1 and a capacitor C, the positive end of the direct-current voltage source Vdc is connected with the anode of the diode D1 and the collector of the controlled switch tube S1, the cathode of the diode D1 is connected with one end of the capacitor C and the collector of the controlled switch tube S2, and the other end of the capacitor C, the emitter of the controlled switch tube S1 and the emitter of the controlled switch tube S2 are connected with the negative end of the direct-current voltage source Vdc. According to the invention, the switched capacitor boost inverter is adopted, boost can be carried out without using an inductor, and the problems of large inductor weight, high loss, low efficiency and the like of a traditional boost inverter circuit are solved.

Description

Technical Field

[0001] This invention relates to the field of home appliance technology, specifically a configuration of a cascaded three-phase four-bridge boost inverter with switched capacitors. Background Technology

[0002] Induction motors are renowned for their compactness, robustness, and high efficiency, making them very popular in the industry. However, three-phase induction motors offer even higher efficiency, higher power density, and more reliable performance compared to traditional single-phase induction motors. However, due to the typically single-phase nature of household power supplies and the relatively low power ratings of these appliances, the development of three-phase induction motors for household appliances has not been sufficiently explored. Furthermore, the high cost of power electronic components and related controls has hindered this development. In recent years, advancements in power electronics technology and the decrease in the price of electronic controllers have made it economically possible to build single-phase to three-phase converters for small household appliances. However, when the power source driving the household appliances is DC, such as a battery, the requirements of the DC-DC conversion stage depend on the magnitude of the input voltage from the DC power supply and the AC rated voltage of the three-phase induction motor. Depending on the AC rated voltage of the corresponding low-power three-phase induction motor, it may be necessary to boost the input voltage to a sufficient level during the boost stage so that the bus voltage (DC bus voltage) is high enough to allow the inverter to drive the induction motor.

[0003] Regarding the issue of increasing the input voltage of DC power supplies in AC systems, current research both domestically and internationally has proposed several power converter topologies. For example, in microgrids, a traditional boost-type DC-DC converter circuit is cascaded with a three-phase inverter circuit to drive a three-phase induction motor. This method can be used to increase the input voltage from the DC source. However, this configuration typically requires a large inductor to avoid high current ripple, as the current amplitude is usually very low in low-power applications. A large inductor leads to greater system weight and size, and higher losses due to magnetism. To avoid excessively large inductors while maintaining a three-fold lower input current, the switching frequency can be increased; however, this will result in increased switching losses and decreased efficiency.

[0004] Currently, three-phase induction motors have three-phase three-arm inverter topologies and four-arm inverter topologies. The three-arm inverter circuit uses a traditional pulse width modulation strategy. Three-phase three-arm inverter circuits are widely used in current induction motors, but when the load is unbalanced, zero-sequence current is generated, leading to asymmetrical three-phase output voltages. Using a three-phase four-arm inverter circuit can improve the system's ability to handle load imbalances. However, the control strategy for traditional three-phase four-arm inverter circuits differs from that of three-phase three-arm inverter circuits; the three-phase four-arm inverter circuit must be controlled as a whole, making the control process more complex. Summary of the Invention

[0005] The purpose of this invention is to provide a configuration of a cascaded three-phase four-bridge boost inverter with switched capacitors to solve the problems in the prior art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a switched capacitor cascaded three-phase four-arm boost inverter configuration, including a switched capacitor circuit and a three-phase four-arm inverter circuit, wherein the switched capacitor circuit is connected to the three-phase four-arm inverter circuit.

[0007] The switched capacitor circuit includes a controlled switch S1, a controlled switch S2, a diode D1, and a capacitor C. The positive terminal of the DC voltage source Vdc is connected to the anode of the diode D1 and the collector of the controlled switch S1. The cathode of the diode D1 is connected to one end of the capacitor C and the collector of the controlled switch S2. The other end of the capacitor C, the emitter of the controlled switch S1, and the emitter of the controlled switch S2 are connected to the negative terminal of the DC voltage source Vdc.

[0008] The three-phase four-arm inverter circuit includes a controlled switch S A1 Controlled switch S A2 Controlled switch S B1 Controlled switch S B2 Controlled switch S C1 Controlled switch S C2 Controlled switch S D1 Controlled switch S D2 .

[0009] Preferably, the controlled switch S1, controlled switch S2, and controlled switch S... A1 Controlled switch S A2 Controlled switch S B1 Controlled switch S B2 Controlled switch S C1 Controlled switch S C2 Controlled switch S D1 Controlled switch S D2 Use either a power switching transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) with an anti-parallel diode.

[0010] Preferably, it also includes inductor and resistor-capacitor branches, with a total of four inductors and three sets of resistor-capacitor branches.

[0011] A PWM method based on virtual space vector modulation, using the aforementioned switched capacitor cascaded three-phase four-bridge boost inverter configuration, includes the following steps:

[0012] S1. Signal generation and comparison: Generate a three-phase sinusoidal modulation wave [a,b,c] and two triangular carrier waves. Compare and add the modulation wave and carrier waves to obtain a 1×3 matrix. After min operation and difference processing, output the switch state vector SSV.

[0013] S2. Signal Processing and Variable Generation: The modulated signal is sent to the "Signal Processing" module to generate the matrix: [m x ,m d ,m n ], using matrix [m x ,m d ,m n A new variable xVV is generated from [a,b,c]. The generated xVV is compared with a 180° phase-shifted cwl triangular carrier wave to generate a pulse PVV.

[0014] S3, Pulse Synthesis Output: SSV, PVV, and

[210] are sent to the "Pulse Processing" module to generate a gate pulse; switch S A1 S B1 S C1 The gate pulses of S1 and S2 are referred to as sA, sB, sC and s1, respectively; switch S A2 S B2 S C2 S2 and S2 are respectively connected to switch S A1 S B1 S C1 It works in a complementary way to S1.

[0015] Compared with the prior art, the beneficial effects of the present invention are:

[0016] 1. By employing a switched-capacitor boost inverter, voltage boosting can be achieved without using an inductor, solving the problems of large inductor weight, high losses, and low efficiency in traditional boost inverter circuits. The switched-capacitor boost inverter of this application has the advantages of high efficiency and low losses.

[0017] 2. The first three bridge arms and the fourth bridge arm are controlled independently. The first three bridge arms adopt the control strategy of a traditional three-phase three-bridge arm inverter circuit, while the fourth bridge arm is independently controlled for zero-sequence current. This strategy simplifies control and enhances anti-interference capability. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0019] Figure 1 This is the circuit topology diagram of the present invention;

[0020] Figure 2 This is a circuit diagram of the first operating mode of the present invention;

[0021] Figure 3 This is a circuit diagram of the second operating mode of the present invention;

[0022] Figure 4 This is a spatial vector diagram of the first working mode of the present invention;

[0023] Figure 5 This is a spatial vector diagram of the second working mode of the present invention;

[0024] Figure 6 This is a diagram of the carrier-based VSVM strategy of this invention;

[0025] Figure 7 This is the SV diagram proposed in the CMVR PWM of this invention;

[0026] Figure 8 This is a block diagram of the CMVR PWM strategy of the present invention;

[0027] Figure 9 This is a control block diagram of the fourth bridge arm of the present invention;

[0028] Figure 10 This is a control block diagram of the fourth bridge arm of the present invention;

[0029] Figure 11 This is the control block diagram of the fourth bridge arm in the prior art;

[0030] Figure 12 This is the output voltage waveform diagram of a current three-phase three-bridge-arm inverter;

[0031] Figure 13 This is a waveform diagram of the output voltage of the three-phase four-bridge-arm inverter of the present invention;

[0032] Figure 14 This is a load diagram (bottom) of the neutral current (top) and three-phase load current of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention.

[0034] Please see Figure 1-6 In this embodiment of the invention, a switched capacitor cascaded three-phase four-arm boost inverter configuration includes a switched capacitor circuit and a three-phase four-arm inverter circuit, wherein the switched capacitor circuit is connected to the three-phase four-arm inverter circuit.

[0035] The switched capacitor circuit includes a controlled switch S1, a controlled switch S2, a diode D1, and a capacitor C. The positive terminal of the DC voltage source Vdc is connected to the anode of the diode D1 and the collector of the controlled switch S1. The cathode of the diode D1 is connected to one end of the capacitor C and the collector of the controlled switch S2. The other end of the capacitor C, the emitter of the controlled switch S1, and the emitter of the controlled switch S2 are connected to the negative terminal of the DC voltage source Vdc.

[0036] The three-phase four-arm inverter circuit includes a controlled switch S A1 Controlled switch S A2 Controlled switch S B1 Controlled switch S B2 Controlled switch S C1 Controlled switch S C2 Controlled switch S D1 Controlled switch S D2 It also includes inductor and resistor-capacitor branches, with a total of four inductors and three sets of resistor-capacitor branches.

[0037] The controlled switch S1, controlled switch S2, and controlled switch S A1 Controlled switch S A2 Controlled switch S B1 Controlled switch S B2 Controlled switch S C1 Controlled switch S C2 Controlled switch S D1 Controlled switch S D2 Use either a power switching transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) with an anti-parallel diode.

[0038] The switching of the transistor will result in two operating modes. The circuit working principle of the first operating mode is as follows: Figure 2 As shown, in this mode, switch S2 is on and S1 is off. At this time, diode D1 is forward biased and capacitor C is charged to Vdc voltage. In this operating mode, the first three bridge arms of the three-phase inverter generate 6 active space vectors

[100] ,

[110] ,

[010] ,

[011] ,

[001] , and

[101] , and 2 zero vectors

[000] and

[111] , as shown. Figure 4 As shown.

[0039] In the second working mode ( Figure 3When switch S1 is on and S2 is off, diode D is reverse biased and charged to Vdc. Since the input voltage source and capacitor C are connected in series, Vbus is 2Vdc. In this operating mode, six large vectors

[200] ,

[220] ,

[020] ,

[022] ,

[002] , and

[202] , as well as a zero vector

[222] , are generated. Figure 5 As shown. In this operating mode, the capacitor discharges.

[0040] like Figure 4 , 5 The spatial vector diagram, combining the two operating modes, contains a total of 15 spatial vectors: 6 large vectors, 6 small vectors, and 3 zero vectors. By employing a suitable PWM strategy to implement the reference spatial vector, then... Figure 3 The formula for the magnitude of the reference vector Vref in the equation is shown in Equation 1:

[0041]

[0042] Where ma is the modulation index and Vdc is the input voltage of the switched capacitor circuit.

[0043] The output voltage of the switched capacitor voltage multiplier in this invention, due to the switching of the switched capacitor circuit, will output either Vdc or 2Vdc. However, the output voltage of a conventional boost converter is always twice the input voltage Vdc of the inverter circuit. Therefore, this characteristic of the proposed topology means that one of the space vectors (SV) cannot be operated using conventional pulse width modulation (PWM) techniques. Therefore, this application proposes two new PWM modulation strategies: a virtual space vector modulation strategy and a common-mode buck space vector modulation strategy.

[0044] The first PWM strategy proposed in this invention is the Virtual Space Vector Modulation (VSVM) strategy. Traditional VSVM schemes typically utilize dwell time calculation and sector identification, which often increases the computational complexity of the digital controller. To simplify the calculation, this paper proposes a carrier-based VSVM strategy derived from a simple level-switching PWM strategy. The proposed VSVM strategy eliminates the need for sector identification or dwell time calculation. Compared to the traditional DC-DC boost converter cascaded three-phase boost inverter solution, the proposed topology and the proposed VSVM strategy result in lower losses, lower phase current THD, and lower torque ripple.

[0045] In the first PWM strategy, the concept of a virtual space vector (VSV) is employed. The virtual vector is implemented using two or more other vectors whose positions differ from the virtual vector to be synthesized. Figure 5In this paper, six virtual vectors are introduced:

[210] ,

[120] ,

[021] ,

[012] ,

[102] , and

[201] . It can be seen that after introducing these six virtual vectors, the proposed spatial vector diagram can be similar to the traditional three-level spatial vector diagram, thus allowing modulation using standard spatial vector modulation strategies. However, traditional VSVM implementations require sector identification and dwell time calculation. To avoid this, this paper proposes a carrier-based VSVM strategy based on third harmonic injection modulation waveforms. In a multi-level inverter, level-switching PWM technology is used to implement the carrier-based VSVM.

[0046] The complete flowchart of the proposed PWM strategy is as follows: Figure 6 As shown. First, three sinusoidal modulation waves [a, b, c] and two triangular carrier waves are generated. The modulation signals are compared with the carrier waves, and the outputs of the comparisons are summed to obtain a 1×3 matrix. Then, the minimum element in this matrix is ​​found and subtracted from all elements pointing to the new matrix to obtain the switching state vector (SSV). The SSV corresponds to... Figure 4 and 5 All SVs shown. This means that if the SSV is

[210] , the inverter needs to Figure 5 It runs on the

[210] vector.

[0047] from Figure 6 As can be seen, the modulated signal is sent to the "Signal Processing" module to generate the matrix: [mx,md,mn]. A new variable xVV is generated using the matrix [mx,md,mn] and [a,b,c], as shown in Table 1. The generated xVV is compared with a 180° phase-shifted cwl triangular carrier wave to generate the pulse PVV. SSV, PVV, and

[210] are sent to the "Pulse Processing" module to generate the gate pulse. Switch S... A1 S B1 S C1 The gate pulses for S1 and S2 are referred to as sA, sB, sC, and s1, respectively. Switch S... A2 S B2 S C2 S2 and S2 are respectively connected to switch S A1 S B1 S C1 It works in a complementary way to S1.

[0048] Table 1 Carrier and Modulation Signals

[0049]

[0050] This invention also proposes another PWM technique to reduce the common-mode voltage (CMV) of the proposed converter. This PWM strategy is called Common-Mode Buck Space Vector Modulation (CMVR) SVM. In power electronics, CMV is detrimental to electric drives. This has prompted researchers to propose several topologies with reduced CMV. However, all existing topologies have higher power semiconductor counts because they require additional devices to address the CMV problem. However, by using the proposed CMVR SVM scheme, the proposed topology can significantly reduce CMV without using external devices. Therefore, the proposed topology has lower power semiconductor requirements compared to conventional solutions. The proposed common-mode buck PWM strategy requires further analysis. Figure 4 The common-mode voltage of each space vector in the equation. The expression for the common-mode voltage is shown in Equation 2:

[0051]

[0052] Among them, V aN V bN V cN Let A, B, and C be the phase voltages, respectively. Using Formula 1, calculate the CMV value for each space vector SV, and the results are given in Table 2.

[0053] Table 2 CMV values ​​of each spatial vector SV

[0054]

[0055] As can be seen from Table 2, if only the proposed topology is used to implement large vectors (

[020] ,

[200] ,

[002] ,

[202] ,

[220] , and

[022] ), the CMV is only in (2 / 3)V. dc and (4 / 3)V dc Oscillate between. Furthermore, the CMV of the zero vector

[111] is V. dc` Between (2 / 3)Vdc and (4 / 3)V dc Therefore, if the zero vector

[111] is used with a large vector, the CMV oscillation can be contained between (2 / 3)Vdc and (4 / 3)Vdc, with the intermediate value being V. dc Vectors with recommended CMV values ​​(all large vectors and

[111] ) are marked with "*" in Table II.

[0056] If only recommendation vectors are used to construct the SV diagram, then a traditional SV diagram can be referenced, such as... Figure 7 As shown. The CMV value corresponding to each vector is also as follows. Figure 7 As shown. Therefore, the proposed converter can be operated using conventional PWM techniques, such as... Figure 8 As shown. From Figure 8As can be seen, the upper bus clamp PWM is used to generate the gate pulses of the three-phase inverter. The modulation signal of the SC converter can generate the upper bus clamp output vector by calculating its minimum value. Compared with other SVM schemes (VSVM schemes) proposed in this application, the CMVR SVM scheme proposed in this application is simpler. The CMVR SVM scheme can be implemented using a low-cost PWM-enabled microcontroller or digital signal processor with at least four independent PWM pins.

[0057] The proposed topology was analyzed using switching functions. In this analysis, four variables, s1, sA, sB, and sC, were defined, corresponding to switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S1, S1, S1, S2, S1, S3, S4, S1, S1, S2 ... A S B and S C The switching states are determined. If switch SA is on, the variable "sA" becomes "1", otherwise it is "0". The same applies to other switching variables corresponding to their respective switches. Therefore, the phase voltages [VaN, VbN, VcN] of the proposed topology are shown in Equation 3-5:

[0058]

[0059] Among them, v sc This is the SC voltage.

[0060] If the maximum rated current of the motor driven by the proposed topology is required, the value of the phase current is shown in Equation 6-8:

[0061] i A =i m sin(ωt+ψ) (6)

[0062] i B =i m sin(ωt+ψ+4π / 3) (7)

[0063] i C =i m sin(ωt+ψ+2π / 3) (8)

[0064] Where ψ is the power factor angle, i m It is the maximum rated current of the topology-driven motor.

[0065] The three-phase four-arm control method actually involves independently controlling the first three arms and the fourth arm. The first three arms use the traditional three-phase three-arm control method, while the fourth arm uses independent tracking control based on the zero-sequence current of the load. The fourth arm controls the operation of its upper and lower switching transistors, ensuring the neutral current in tracks the three-phase load current. An average current control method is employed, which offers high control accuracy, a fixed switching frequency, and strong anti-interference performance. Figure 9 As shown.

[0066] The three-phase load current is first summed and the negative value is taken. Then, it is subtracted from the neutral current and the output adjustment value is compared with the triangular wave through a simple PI controller to generate a PWM signal to drive the corresponding switching transistor.

[0067] Compared to traditional topologies and control strategies, this inverter topology offers advantages such as high efficiency and low losses. It avoids the use of large inductors, thus resolving issues like high losses, low efficiency, and unbalanced loads inherent in traditional solutions.

[0068] The control strategy presented in this paper, CMVR SVM, and the CMV generated by a three-phase inverter operating under conventional SVM are as follows: Figure 10-11 As shown, it can be observed that under the proposed strategy, the CMV is much smaller than that of a conventional three-phase inverter system operating with a conventional SVM.

[0069] Figure 12 Simulated output voltage waveforms when powering a traditional three-phase, three-arm inverter. From Figure 12 As can be seen, the three-phase voltages of the traditional topology are severely asymmetrical. Figure 13 The waveforms of the phase voltages output when the first three bridge arms adopt the traditional control strategy are shown. It can be seen that the imbalance between the output phase voltages is very small under three-phase unbalanced load conditions, indicating a strong ability to handle unbalanced loads.

[0070] Figure 14 The sum of the negative three-phase load currents and the neutral current in are given. It can be seen that by independently controlling the zero-sequence voltage of the fourth bridge arm, the neutral current in tracks the reference command current very well.

[0071] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A configuration of a switched capacitor cascaded three-phase four-bridge boost inverter, characterized in that: It includes a switched capacitor circuit and a three-phase four-arm inverter circuit, wherein the switched capacitor circuit is connected to the three-phase four-arm inverter circuit. The switched capacitor circuit includes a controlled switch S1, a controlled switch S2, a diode D1, and a capacitor C. The positive terminal of the DC voltage source Vdc is connected to the anode of the diode D1 and the collector of the controlled switch S1. The cathode of the diode D1 is connected to one end of the capacitor C and the collector of the controlled switch S2. The other end of the capacitor C, the emitter of the controlled switch S1, and the emitter of the controlled switch S2 are connected to the negative terminal of the DC voltage source Vdc. The three-phase four-arm inverter circuit includes a controlled switch S A1 Controlled switch S A2 Controlled switch S B1 Controlled switch S B2 Controlled switch S C1 Controlled switch S C2 Controlled switch S D1 Controlled switch S D2 .

2. The configuration of a switched capacitor cascaded three-phase four-bridge boost inverter according to claim 1, characterized in that: The controlled switch S1, controlled switch S2, and controlled switch S A1 Controlled switch S A2 Controlled switch S B1 Controlled switch S B2 Controlled switch S C1 Controlled switch S C2 Controlled switch S D1 Controlled switch S D2 Use either a power switching transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) with an anti-parallel diode.

3. The configuration of a switched capacitor cascaded three-phase four-bridge boost inverter according to claim 1, characterized in that: It also includes inductor and resistor-capacitor branches, with a total of four inductors and three sets of resistor-capacitor branches.

4. A PWM method based on virtual space vector modulation, characterized in that: The configuration of a switched capacitor cascaded three-phase four-bridge boost inverter according to any one of claims 1-3 includes the following steps: S1. Signal generation and comparison: Generate a three-phase sinusoidal modulation wave [a,b,c] and two triangular carrier waves. Compare and add the modulation wave and carrier waves to obtain a 1×3 matrix. After min operation and difference processing, output the switch state vector SSV. S2. Signal Processing and Variable Generation: The modulated signal is sent to the "Signal Processing" module to generate the matrix: [m x ,m d ,m n ], using matrix [m x ,m d ,m n A new variable xVV is generated from [a,b,c]. The generated xVV is compared with a 180° phase-shifted cwl triangular carrier wave to generate a pulse PVV. S3, Pulse Synthesis Output: SSV, PVV, and [210] are sent to the "Pulse Processing" module to generate a gate pulse; switch S A1 S B1 S C1 The gate pulses of S1 and S2 are referred to as sA, sB, sC and s1, respectively; switch S A2 S B2 S C2 S2 and S2 are respectively connected to switch S A1 S B1 S C1 It works in a complementary way to S1.

Images