Storage device, data processing method, computer system and medium

Abstract

A storage device, a data processing method, a computer system and a medium relate to the field of data storage, the storage device comprises a storage unit, a control chip and a capacitance manager, the storage unit comprises vertically stacked multi-layer high bandwidth memory silicon grains and vertically stacked multi-layer flash memory silicon grains, the multi-layer flash memory silicon crystal grains are stacked on the multi-layer high-bandwidth memory silicon crystal grains in a 3D packaging mode; the capacitor manager is configured to supply power to the control chip in response to power failure of an external power supply connected with the control chip; the control chip is configured to transfer data stored in the multi-layer high-bandwidth memory silicon crystal grains to the multi-layer flash memory silicon crystal grains when the capacitor manager supplies power. The storage device is realized into a small-sized hybrid storage system, so that data can be stored persistently, and the storage device can also have relatively high data interaction performance, so that the storage device has the advantages of high performance and low cost.

Description

Technical Field

[0001] This disclosure relates to the field of storage units, and more particularly to a storage device, a data processing method, a computer system, and a medium. Background Technology

[0002] High-bandwidth memory (HBM) achieves high density and high bandwidth by stacking multiple memory chips on a single chip. This stacking design allows memory chips to be integrated more tightly, reducing circuit length, lowering signal transmission latency, and thus increasing data transfer rates.

[0003] In current computer systems, in order to improve the speed of processor reading and writing data, high-bandwidth memory (HBM) units are usually set up in multi-level virtual systems. However, high-bandwidth memory units usually do not have persistent storage capabilities and will lose data when power is off. Summary of the Invention

[0004] This disclosure provides a storage device, a data processing method, a computer system, and a medium.

[0005] In a first aspect, embodiments of this disclosure provide a storage device, which includes a storage unit, a control chip, and a capacitor manager. The storage unit includes vertically stacked multilayer high-bandwidth memory silicon dies and vertically stacked multilayer flash memory silicon dies. The multilayer flash memory silicon dies are stacked on top of the multilayer high-bandwidth memory silicon dies using a 3D packaging method. The capacitor manager is configured to supply power to the control chip in response to a power outage of an external power supply connected to the control chip. The control chip is configured to transfer data stored in the multilayer high-bandwidth memory silicon dies to the multilayer flash memory silicon dies when the capacitor manager is powered on.

[0006] Secondly, this disclosure provides a data processing method applied to the storage device in the above embodiments, comprising: responding to a power outage of the external power supply connected to the storage device, supplying power to a control chip using a capacitor manager; transferring data stored in a multilayer high-bandwidth memory silicon die to a multilayer flash memory silicon die when the capacitor manager is powered on; and transferring data in the multilayer flash memory silicon die to the multilayer high-bandwidth memory silicon die when the external power supply is restored.

[0007] Thirdly, this disclosure provides a computer system including a host and the storage device described in the above embodiments. The host's processor is configured to: when the host is running an operating system, extract the operating system's running state information from the host's data; store the running state information in the storage device; and when the host is powered off and then powered on again, read the running state information from the storage device and restore the operating system to its running state before the power failure based on the running state information.

[0008] Fourthly, this disclosure provides a non-transient computer storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the data processing method described in the above embodiments.

[0009] The storage device of this disclosure embodiment comprises a storage unit stacked from multiple layers of high-bandwidth memory silicon and multiple layers of flash memory silicon using a 3D packaging method. The high-bandwidth memory silicon has high read / write performance, while the flash memory silicon retains data even when power is off. When the external power supply connected to the control chip is disconnected, a capacitor manager can be used to supply power to the control chip. During the capacitor manager's power supply period, the control chip transfers data from the multiple layers of high-bandwidth memory silicon to the multiple layers of flash memory silicon, thus implementing the storage device as a small hybrid storage system. This system can persistently store data and also has high data interaction performance, giving the storage device both high performance and low cost.

[0010] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0012] Figure 1 This is a schematic diagram of the structure of one embodiment of the storage device disclosed herein;

[0013] Figure 2 This is a schematic diagram of the microstructure of a storage cell in one embodiment of the storage device disclosed herein;

[0014] Figure 3 This is a schematic diagram of the capacitor manager in one embodiment of the storage device disclosed herein;

[0015] Figure 4 This is a schematic diagram of the structure of a power failure detection module in one embodiment of the storage device disclosed herein;

[0016] Figure 5 This is a schematic diagram illustrating data transfer in one embodiment of the storage device disclosed herein;

[0017] Figure 6 This is a flowchart illustrating one embodiment of the data processing method disclosed herein;

[0018] Figure 7 This is a schematic diagram of the structure of one embodiment of the computer system disclosed herein. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0020] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0021] The ordinal numbers such as "first" and "second" in this disclosure are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0022] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0023] Figure 1 A schematic diagram of the structure of one embodiment of the storage device of this disclosure is shown, such as... Figure 1 As shown, the storage device includes a capacitor manager 110, a control chip 120, and a storage unit 130 connected to the control chip 120. Figure 2 This illustrates the microstructure of the storage cell 130, such as... Figure 2 As shown, the storage cell 130 includes vertically stacked multi-layer high-bandwidth memory silicon dies (i.e., HDM DRAM Die in the figure) and vertically stacked multi-layer flash memory silicon dies (i.e., NAND Die in the figure), with the multi-layer flash memory silicon dies stacked on top of the multi-layer high-bandwidth memory silicon dies through 3D packaging.

[0024] The capacitor manager 110 includes capacitors (not shown) and is configured to supply power to the control chip 120 in response to the disconnection of an external power supply connected to the control chip 120. The control chip 120 is configured to transfer data stored in a multilayer high-bandwidth memory silicon die to a multilayer flash memory silicon die when the capacitor manager is powered.

[0025] exist Figure 2 In the example shown, the high-bandwidth memory silicon die can be a DRAM (Dynamic Random Access Memory) die; the flash memory silicon die can be a NAND (Not AND) die. By using 3D packaging to stack multiple layers of high-bandwidth memory silicon dies and multiple layers of flash memory silicon dies vertically, with adjacent silicon dies interconnected via through-silicon vias (TSVs) and microbump technology, more capacity can be accommodated while keeping the memory cells within a smaller form factor. This structure also allows for shorter connection distances, reducing signal transmission time and power consumption, thus improving the bandwidth and data transfer rate of the memory cells.

[0026] In a specific example, the storage device can be connected to the host's processor (which can be a CPU and / or GPU), and storage unit 130 can be part of the host's multi-level virtual system, where the host's processor can store selected data. This is done to improve the data read / write efficiency between the host's processor and the storage device. Figure 1 As shown, the control chip 120 is equipped with address pins (ADDR: A0-A64), data pins (DATA: D0-D63), flash read enable pin (NANDR), flash write enable pin (NANDW), memory read enable pin (MEMR), and memory write enable pin (MEMW), enabling the control chip 120 to access data in multi-layer high-bandwidth memory silicon dies and multi-layer flash memory silicon dies according to the address.

[0027] The capacitor manager 110 may include capacitors, a charger, and a discharger. The charger controls the charging of the capacitors, while the discharger controls the discharging of the capacitors, i.e., supplies power to the control chip 120. The capacitor manager 110 also detects the on / off state of an external power source. For example, the discharger can be connected to an external power source; when the host is operating normally, the host's power supply supplies power to the control chip 120. When the discharger detects that the external power source is disconnected, it controls the capacitors to supply power to the control chip 120. At this time, the control chip 120 can read data from the high-bandwidth memory silicon die and store it in the flash memory silicon die, preventing data loss during power outages and effectively achieving persistent data storage.

[0028] In this embodiment, the storage device's storage unit is stacked using a 3D packaging method, comprising multiple layers of high-bandwidth memory silicon and multiple layers of flash memory silicon. The high-bandwidth memory silicon has high read / write performance, while the flash memory silicon retains data even when power is off. When the external power supply connected to the control chip is disconnected, a capacitor manager can be used to supply power to the control chip. During the capacitor manager's power supply period, the control chip transfers data from the multiple layers of high-bandwidth memory silicon to the multiple layers of flash memory silicon, thus realizing the storage device as a small hybrid storage system. This system can persistently store data and also has high data interaction performance, giving the storage device the advantages of both high performance and low cost.

[0029] In an optional example, after transferring data from the multilayer high-bandwidth memory silicon die to the multilayer flash memory silicon die when the capacitor manager is powered, the control chip is also configured to transfer data from the multilayer flash memory silicon die to the multilayer high-bandwidth memory silicon die when the external power supply is restored.

[0030] As an example, when a storage device is connected to a host, the host's data can be stored in a multi-layer high-bandwidth memory silicon chip. When the host loses power, the data is transferred to a multi-layer flash memory silicon chip to prevent data loss. When the host is powered on again, the control chip can first transfer the data in the multi-layer flash memory silicon chip to the multi-layer high-bandwidth memory silicon chip. In this way, the host can read the data stored before the power failure from the multi-layer high-bandwidth memory silicon chip more quickly.

[0031] Figure 3 A schematic diagram of the capacitor manager is shown in one embodiment of the storage device of this disclosure. For example... Figure 3 As shown, the capacitor manager 310 may include a discharger 311 and a capacitor 312; wherein, the discharger 311 is connected to an external power supply 320 and a capacitor 312, and is configured to: detect the voltage of the external power supply 320; when the detected voltage of the external power supply 320 is less than or equal to a preset threshold, output a high-level signal; and, when a power-on signal is received, supply power to the control chip through the capacitor 312, wherein the preset threshold represents the voltage value required for the normal operation of the control chip.

[0032] In this embodiment, the discharger 311 is equipped with a discharge switch. When the discharger 311 detects that the voltage of the external power supply 320 is less than or equal to a preset threshold, it can output a high-level signal to the control chip. After receiving the high-level signal, the control chip can return a power-on signal to the discharger 311 to instruct the discharger 311 to open the discharge switch, so that the capacitor 312 supplies power to the control chip. When the control chip transfers all the data in the memory to the flash memory, the discharger 311 closes the discharge switch and stops supplying power to the capacitor 312.

[0033] In this embodiment, when the voltage of the external power supply 320 is less than or equal to a preset threshold, it indicates that the external power supply 320 cannot provide the power required for the normal operation of the control chip. As an example, the preset threshold can be pre-set based on experience or specific scenarios; for example, it can be set to 0 or a value close to 0 (such as 0.1V, 0.2V, etc.). When the voltage of the external power supply 320 is less than or equal to the preset threshold, it indicates that the external power supply 320 is disconnected. Alternatively, the preset threshold can be set to a value less than the rated voltage of the control chip. When the voltage of the external power supply 320 is less than or equal to the preset threshold, it indicates that the voltage provided by the external power supply 320 to the control chip is less than the rated voltage of the control chip, causing the control chip to malfunction.

[0034] As an example, the control chip may be equipped with a power failure detection component to receive a high-level signal output by the discharger, and to send a power-on signal to the discharger when a high-level signal is received.

[0035] In an optional example, the capacitor manager 310 may also include a charger 313 configured to control the charging of the capacitor 312 when the external power supply 320 is turned on.

[0036] Figure 4 A schematic diagram of a power-loss detection component is shown in one embodiment of the storage device of this disclosure. For example... Figure 4 As shown, the power-down detection component 410 is connected to the capacitor manager. The power-down detection component 410 includes a power-down detector 411, a status register 412, an AND gate circuit 413, and a control register 414. The power-down detector 411 is connected to the discharger (not shown in the figure), the AND gate circuit 413, and the status register 412, and is configured to: in response to a high-level signal, set the first input terminal (i.e., terminal a in the figure) of the AND gate circuit 413 to 1, and set the preset bit in the status register 412 to 1. The processor (CPU) of the control chip is configured to: when the preset bit in the status register 412 is detected to be 1, set the preset bit in the control register 414 to 1; the control register 414 is configured to set the second input terminal (i.e., terminal b in the figure) of the AND gate circuit 413 to 1 when the preset bit therein is set to 1; the AND gate circuit 413 is connected to the discharger and is configured to perform an AND operation on the input signals of the first input terminal and the second input terminal; when the operation result is 1, a power-on signal is sent to the discharger.

[0037] In this embodiment, the preset bits in the status register 412 and the control register 414 can be any pre-specified bit or all bits. Setting the first input of the AND gate circuit 413 to 1 indicates that the external power supply is disconnected, and setting the second input to 1 indicates that a power-on command has been received from the processor of the control chip. Only when both conditions are met simultaneously will the AND gate circuit 413 output a power-on signal to the discharger.

[0038] The power-down detector can receive the high-level signal output by the discharger and feed it back to the AND gate circuit 412 and the processor of the control chip. The processor generates a power-on instruction (that is, sets the preset value in the control register 414 to 1). Through the AND (&) operation of the AND gate circuit 413, it ensures that the external power supply is disconnected and the control chip determines that the capacitor power supply is turned on before outputting a power-on signal to the discharger, which helps to improve the reliability of the storage device.

[0039] In some optional embodiments of this example, the power failure detection component 410 further includes an enable processor 415 connected to the power failure detector 411, configured to turn the power failure detector 411 on or off.

[0040] In this embodiment, the enable processor 415 can control the on / off state of the power failure detection 411. When the persistent function of the storage device is not needed, the power failure detector 411 can be turned off by the enable processor 415. In this way, when the external power is disconnected, the control chip will no longer perform data transfer operations, making the storage device more flexible in practical applications.

[0041] Next, refer to Figure 4 In some embodiments, the processor of the control chip is further configured to: set a preset bit in the control register 414 to 0 when all data in the multilayer high-bandwidth memory silicon die is stored in the multilayer flash memory silicon die; the AND gate 413 is further configured to send a power supply stop signal to the discharger when the operation result is 0. The discharger is also configured to disable the capacitor in response to the power supply stop signal.

[0042] In this embodiment, when the data transfer operation is completed, the control chip generates a power supply stop signal through the control register and AND gate circuit to instruct the discharger to stop the capacitor from supplying power to the control chip, so as to avoid wasting resources.

[0043] The following is for reference. Figure 5 , Figure 5 A schematic diagram of a data transfer operation is shown in one embodiment of the storage device of this disclosure, such as... Figure 5As shown, the storage device includes a control chip 510, a storage unit 520 (including a multilayer high-bandwidth silicon die 521 and a multilayer flash memory silicon die 522), and a capacitor manager (not shown in the figure). The storage device may also include a memory manager 530, which is disposed in the control chip 510 or the storage unit 520. The memory manager 530 is configured to convert memory addresses to flash memory addresses according to a pre-established mapping relationship between memory addresses and flash memory addresses. The memory address represents the storage address of data in the multilayer high-bandwidth silicon die 521, and the flash memory address represents the storage address of data in the multilayer flash memory silicon die 522.

[0044] The control chip 510 can transfer data in the following way: read the data to be transferred from the multilayer high-bandwidth silicon die 521 and send the memory address of the data to be transferred to the memory manager 530; according to the flash memory address output by the memory manager 530, store the data to be transferred into the multilayer flash memory silicon die 522.

[0045] Figure 5 This disclosure only shows one embodiment of the memory manager 530 being configured in a multilayer high-bandwidth silicon die 521, but is not limited to this one embodiment. When the memory manager 530 is configured in the multilayer high-bandwidth silicon die 521 as a register, the processor of the control chip 510 can read the mapping relationship (i.e., MMU_DATA) between memory addresses and flash memory addresses in the memory manager 530 into a cache (i.e., cache) according to the address ADD1 (i.e., the address of the register) of the memory manager 540. Then, according to the memory address ADD2, it reads the data to be transferred, DRAM_DRTA, from the multilayer high-bandwidth silicon die 521, and according to the flash memory address NAND_ADD corresponding to ADD2 in the mapping relationship, converts the data to be transferred, DRAM_DRTA, into flash memory data NAND_DATA and writes it into the multilayer flash memory silicon die 522.

[0046] When the memory manager 530 is set in the control chip 510, the processor of the control chip 510 does not need to obtain the mapping relationship from the storage unit 520, and can directly look up the flash memory address corresponding to the memory address.

[0047] In this embodiment, the storage device can manage the mapping relationship between memory addresses and flash memory addresses through a memory manager, which helps to improve the efficiency of data transfer when power is lost.

[0048] In practice, in order to improve the restart speed of the host after a power failure, the operating system's running status information (such as user data and critical system information) before the power failure is usually exchanged to an external persistent storage unit. When power is restored, the running status information is read from the external persistent storage into the host's processor. Due to the limited read and write speed of persistent storage, this process takes a long time.

[0049] To address this issue, the storage device disclosed herein can be connected to the host's processor and powered externally by the host. See next for further details. Figure 2 The storage device may also include a logic control unit (i.e., the Logic Die in the figure), configured to: store the host system's operating status information into a multilayer high-bandwidth memory silicon die; and, after transferring data from the multilayer flash memory silicon die to the multilayer high-bandwidth memory silicon die, load the operating status information from the multilayer high-bandwidth memory silicon die into the host's processor so that the host can restore the system state to the state before the power failure based on the operating status information.

[0050] In this embodiment, the logic control unit receives operating status information sent by the host and stores it in a multilayer high-bandwidth memory silicon die. When the host loses power, the storage device can use a capacitor manager to supply power to the control chip. During this stage, the control chip transfers the host's system operating status information from the multilayer high-bandwidth memory silicon die to the multilayer flash memory silicon die. When the host regains power and needs to read the operating status information, it can send a data read command to the logic control unit, which then reads the data from the multilayer high-bandwidth memory silicon die and returns it to the host.

[0051] In this embodiment, the system's operating status information can be persistently stored through a storage device. Thanks to the high-speed read and write performance of the storage device, the host can read the operating status information more quickly after power is restored, and thus restore the system to the state before the power failure more quickly, which helps to shorten the time consumed by the host restart.

[0052] In some embodiments, the storage device disclosed herein may be embedded in the host's processor, with the external power supply provided by the host.

[0053] In this embodiment, the host's processor can be a CPU or a GPU. Embedding the storage device within the host's processor can reduce the distance between the storage device and the host's processor, which helps to further shorten the time required for data interaction between the host and the storage device.

[0054] Figure 6 A flowchart illustrating an embodiment of the data processing method of this disclosure is shown, which is applied to a storage device in any of the above embodiments, such as... Figure 6 As shown, the method includes the following steps.

[0055] Step 610: In response to the power failure of the external power supply connected to the control chip, power is supplied to the control chip using the capacitor manager.

[0056] Step 620: When the capacitor manager is powered on, the data stored in the multi-layer high-bandwidth memory silicon die is transferred to the multi-layer flash memory silicon die.

[0057] Step 630: When the external power supply is restored, the data in the multilayer flash memory silicon die is transferred to the multilayer high-bandwidth memory silicon die.

[0058] In this embodiment, when the external power supply connected to the control chip is disconnected, the capacitor manager can be used to supply power to the control chip so that the control chip can transfer data from the multi-layer high-bandwidth memory silicon to the multi-layer flash memory silicon during the power supply period of the capacitor manager. This can realize the storage device as a small hybrid storage system, which can persistently store data and also has high data interaction performance, so that the storage device has the advantages of high performance and low cost.

[0059] In this embodiment, preset information from the host is stored in the memory of the memory device, and when the host loses power, the preset information is transferred to the flash memory. This improves the data read / write speed between the host and the memory device while achieving persistent data storage.

[0060] like Figure 7 As shown, this disclosure also provides a computer system including a host and a storage device in any of the above embodiments, wherein the host's processor is configured to: when the host is running an operating system, extract the operating system's running state information from the host's data; store the running state information in the storage device; and when the host is powered off and then powered on again, read the running state information from the storage device and restore the operating system to its running state before the power failure based on the running state information.

[0061] As an example, the host's processor can be a CPU and / or GPU, used to store the host's operating system state information into the multi-layer high-bandwidth memory silicon (DRAM) of the storage device. When the host is powered off, the storage device can activate the capacitor manager to supply power to the control chip, transferring the operating state information from the DRAM to the multi-layer flash memory silicon (DRAM). When the host is powered on again, the storage device can transfer the data from the multi-layer flash memory silicon to the DRAM, allowing the host to read the operating state information from the DRAM and restore the operating system to its state before the power outage.

[0062] In this embodiment, thanks to the high-speed read / write performance and persistent storage capability of the storage device, the host can persistently store the running status information and read the running status information more quickly after power failure, thereby shortening the restart time of the host after power failure.

[0063] like Figure 7 As shown, the computer system may also include a CXL module, and the host's processor is further configured to store data other than running status information into the CXL module, thereby expanding the host's storage resources.

[0064] In some embodiments, the storage device is embedded within the host's processor. This reduces the distance between the memory device and the host's processor, helping to further shorten the time required for data interaction between the host and the memory device.

[0065] This disclosure also provides a non-transient computer storage medium, which stores a computer program that, when executed by a processor, implements the data processing method described above.

[0066] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other storage unit technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A storage device, characterized in that, The storage device includes a storage unit, a control chip, and a capacitor manager. The storage unit includes vertically stacked multilayer high-bandwidth memory silicon dies and vertically stacked multilayer flash memory silicon dies. The multilayer flash memory silicon dies are stacked on top of the multilayer high-bandwidth memory silicon dies using a 3D packaging method. The capacitor manager is configured to supply power to the control chip in response to a power outage of the external power supply connected to the control chip. The control chip is configured to transfer data stored in the multilayer high-bandwidth memory silicon die to the multilayer flash memory silicon die when the capacitor manager is powered.

2. The storage device according to claim 1, characterized in that, The capacitor manager includes a discharger and a capacitor; The discharger is connected to the external power supply and the capacitor, and is configured to detect the voltage of the external power supply. When the voltage of the external power supply is detected to be less than or equal to a preset threshold, a high-level signal is output. In addition, when a power-on signal is received, power is supplied to the control chip through the capacitor; The preset threshold represents the voltage value required for the control chip to operate normally.

3. The storage device according to claim 2, characterized in that, The control chip is equipped with a power-down detection component connected to the capacitor manager. The power-down detection component is configured to send the power-on signal to the discharger when it receives the high-level signal.

4. The storage device according to claim 3, characterized in that, The control chip includes a processor; the power-down detection component includes a power-down detector, a status register, an AND gate circuit, and a control register, wherein... The power-down detector is connected to the discharger, the AND gate circuit, and the status register, and is configured to: in response to the high-level signal, set the first input terminal of the AND gate circuit to 1, and set the preset bit in the status register to 1; The processor is configured to: when it detects that a preset bit in the status register is 1, set a preset bit in the control register to 1; The control register is configured such that when a preset bit in the controller register is set to 1, the second input of the AND gate is set to 1. The AND gate circuit is configured to perform an AND operation on the input signals of the first input terminal and the second input terminal; when the operation result is 1, the power supply start signal is sent to the discharger.

5. The storage device according to claim 4, characterized in that, The power failure detection component also includes an enable processor connected to the power failure detector, configured to turn the power failure detector on or off.

6. The storage device according to claim 4, characterized in that, The processor is also configured to: set a preset bit in the control register to 0 when all the data in the multi-layer high-bandwidth memory silicon die is stored in the multi-layer flash memory silicon die; The AND gate circuit is also configured to send a power supply stop signal to the discharger when the operation result is 0; The discharger is also configured to disable the capacitor in response to the power supply stop signal.

7. The storage device according to claim 2, characterized in that, The capacitor manager also includes a charger configured to control the charging of the capacitor when the external power source is connected.

8. The storage device according to claim 1, characterized in that, The storage device further includes a memory manager disposed in the control chip or the storage unit. The memory manager is configured to convert memory addresses into flash memory addresses according to a pre-established mapping relationship between memory addresses and flash memory addresses. The memory address represents the storage address of data in the multilayer high-bandwidth memory silicon die, and the flash memory address represents the storage address of data in the multilayer flash memory silicon die. The control chip is configured to transfer data stored in the multilayer high-bandwidth memory silicon die to the multilayer flash memory silicon die, including: reading the data to be transferred from the multilayer high-bandwidth memory silicon die and sending the memory address of the data to be transferred to the memory manager; The data to be transferred is stored in the multilayer flash memory silicon die according to the flash memory address output by the memory manager.

9. The storage device according to claim 1, characterized in that, After transferring the data stored in the multilayer high-bandwidth memory silicon die to the multilayer flash memory silicon die, the control chip is further configured to transfer the data in the multilayer flash memory silicon die to the multilayer high-bandwidth memory silicon die when the external power supply is restored.

10. The storage device according to any one of claims 1 to 9, characterized in that, The storage device is connected to the host's processor, and the external power supply is provided by the host. The storage device further includes a logic control unit configured to: store the operating status information of the host system into the multilayer high-bandwidth memory silicon die; and, after transferring data from the multilayer flash memory silicon die to the multilayer high-bandwidth memory silicon die, load the operating status information from the multilayer high-bandwidth memory silicon die into the processor of the host, so that the host can restore the system state to the state before the power failure based on the operating status information.

11. The storage device according to claim 10, characterized in that, The storage device is embedded in the host's processor.

12. A data processing method applied to a storage device according to any one of claims 1 to 11, the storage device comprising a storage unit, a control chip, and a capacitor manager, wherein, The storage unit includes vertically stacked multilayer high-bandwidth memory silicon dies and vertically stacked multilayer flash memory silicon dies, wherein the multilayer flash memory silicon dies are stacked on top of the multilayer high-bandwidth memory silicon dies using a 3D packaging method; characterized in that the method includes: In response to the power failure of the external power supply connected to the control chip, the capacitor manager supplies power to the control chip. When the capacitor manager is powered, data stored in the multilayer high-bandwidth memory silicon die is transferred to the multilayer flash memory silicon die; and, When the external power supply is restored, the data in the multilayer flash memory silicon die is transferred to the multilayer high-bandwidth memory silicon die.

13. A computer system comprising a host and a storage device as described in any one of claims 1 to 11, characterized in that, The host's processor is configured to: when the host is running an operating system, extract the operating system's running status information from the host's data; The operating status information is stored in the storage device; Furthermore, when the host is powered off and then powered on again, the operating status information is read from the storage device, and the operating system is restored to its operating state before the power failure based on the operating status information.

14. The computer system according to claim 13, characterized in that, The computer system also includes a CXL module, and the host's processor is further configured to store data other than the running status information into the CXL module.

15. A non-transient computer storage medium, wherein the computer-readable storage medium stores a computer program, characterized in that, When the computer program is executed by a processor, it implements the data processing method as described in claim 12.

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