SOC chip and electronic equipment
By fabricating the physical layer module and memory module of the SOC chip through a fully custom process, the problem of difficulty in simulating PHY and DRAM was solved, and higher timing accuracy and product reliability were achieved.
Patent Information
- Application Number
- CN202510846816.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-23
- Publication Date
- 2025-11-18
AI Technical Summary
In existing technologies, PHY and DRAM, as independent hard-core IPs, are difficult to simulate in a true sense, resulting in poor timing accuracy and insufficient product reliability.
A SOC chip is provided, which fabricates the physical layer module and the memory module through a fully custom process, so that the timing parameters of the physical layer module are determined based on the timing parameters of the memory module, and the physical layer module and the memory module are simulated simultaneously.
It improves timing accuracy and product reliability, enables simultaneous simulation of PHY and DRAM, and enhances the overall performance of the chip.
Smart Images
Figure CN120973727A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a SOC chip and an electronic device. BACKGROUND
[0002] A PHY (Physical Layer) is a bottom layer part in a communication protocol, mainly responsible for processing actual transmission and reception of physical signals, and in a DRAM (Dynamic Random Access Memory), the PHY can perform time domain synchronization, voltage domain conversion, timing fine adjustment and the like on signals, so as to realize signal transmission and control of the DRAM.
[0003] The existing PHY is usually a separate hard core IP, and the DRAM itself can also be a separate hard core IP, that is, the PHY and the DRAM can be IP products from different companies. In this way, in the process of verification, it is difficult to realize simulation of the PHY and the DRAM together in a true sense. SUMMARY
[0004] The application provides a SOC chip and an electronic device, which can simultaneously simulate the PHY and the DRAM, and improve timing accuracy and product reliability.
[0005] To solve the above technical problems, the first technical solution provided by the application is to provide a SOC chip, comprising: a plurality of storage components, each of the storage components comprising: a physical layer module, a storage control module connected with the physical layer module, and a storage module;
[0006] The storage control module is configured to transmit a read-write operation instruction to the physical layer module, and the physical layer module is configured to perform protocol processing on the read-write operation instruction, so as to obtain a read-write control instruction and transmit the read-write control instruction to the storage module, so as to perform read-write control on the storage module; wherein the physical layer module and the storage module are prepared through a full customization process, and a timing parameter corresponding to the physical layer module is determined based on a timing parameter of the storage module in the full customization process.
[0007] In an embodiment, the physical layer module comprises: a command processing module and a data processing module, the command processing module is configured to perform protocol processing on a command signal in the read-write operation instruction, so as to transmit the command signal to the storage module; and the data processing module is configured to perform protocol processing on a data signal in the read-write operation instruction, so as to transmit the data signal to the storage module.
[0008] In an embodiment, the storage component comprises a first unidirectional signal bus and a second unidirectional signal bus, an input end of the first unidirectional signal bus is connected to the storage control module, and an output end of the first unidirectional signal bus is connected to the command processing module; an input end of the second unidirectional signal bus is connected to the command processing module, and an output end of the second unidirectional signal bus is connected to the storage module.
[0009] In an embodiment, the storage component comprises a bidirectional signal bus, a read data signal bus and a write data signal bus, the bidirectional signal bus is connected to the storage control module and the data processing module, an input end of the read data signal bus is connected to the storage module, an output end of the read data signal bus is connected to the data processing module, an input end of the write data signal bus is connected to the data processing module, and an output end of the write data signal bus is connected to the storage module.
[0010] In an embodiment, the storage component further comprises a clock tree, the clock tree is used to provide a clock signal to the command processing module and the data processing module.
[0011] In an embodiment, the command processing module comprises a first clock unit and a first level conversion unit, an input end of the first clock unit is connected to an output end of the first unidirectional signal bus, an input end of the first level conversion unit is connected to an output end of the first clock unit, and an output end of the first level conversion unit is connected to an input end of the second unidirectional signal bus.
[0012] In an embodiment, the first clock unit comprises a first flip-flop and a delay unit, an input end of the first flip-flop is connected to an output end of the first unidirectional signal bus, an output end of the first flip-flop is connected to an input end of the delay unit, and an output end of the delay unit is connected to an input end of the first level conversion unit.
[0013] In an embodiment, the data processing module comprises a second level conversion unit, an input end of the second level conversion unit is connected to an output end of the read data signal bus, and an output end of the second level conversion unit is connected to the bidirectional signal bus.
[0014] In an embodiment, the data processing module further comprises a second clock unit and a third level conversion unit, an input end of the second clock unit is connected to the bidirectional signal bus, an input end of the third level conversion unit is connected to an output end of the second clock unit, and an output end of the third level conversion unit is connected to an input end of the write data signal bus.
[0015] The second clock unit comprises a second flip-flop, an input end of the second flip-flop is connected with the bidirectional signal bus, and an output end of the second flip-flop is connected with an input end of the third level conversion unit.
[0016] To solve the above technical problems, the second technical solution provided by the application is to provide an electronic device comprising the SOC chip.
[0017] The SOC chip provided by the application comprises a plurality of storage components, each of the storage components comprises a physical layer module, a storage control module connected with the physical layer module, and a storage module; the storage control module is configured to transmit read-write operation instructions to the physical layer module; the physical layer module is configured to perform protocol processing on the read-write operation instructions, thereby obtaining read-write control instructions and transmitting the read-write control instructions to the storage module to perform read-write control on the storage module; the physical layer module and the storage module are prepared through a full customization process, and the timing parameters corresponding to the physical layer module are determined based on the timing parameters of the storage module in the full customization process. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor, wherein:
[0019] Figure 1 is a structural schematic diagram of a first embodiment of a SOC chip of the application;
[0020] Figure 2 is a structural schematic diagram of a second embodiment of a SOC chip of the application;
[0021] Figure 3 is a structural schematic diagram of a third embodiment of a SOC chip of the application;
[0022] Figure 4 is a structural schematic diagram of a fourth embodiment of a SOC chip of the application;
[0023] Figure 5 is a structural schematic diagram of an embodiment of an electronic device of the application. DETAILED DESCRIPTION
[0024] The terms "first", "second", "third", etc. in the present application are used only for descriptive purpose and cannot be construed as indicating or implying relative importance or an indicated number of technical features. Thus, the features defined with "first", "second", "third" can include at least one of the features explicitly or implicitly. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as upper, lower, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship between the components, the movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.
[0025] Reference to "embodiments" in this document means that a particular feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of the application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative embodiments to each other. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0026] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of the present application.
[0027] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of a first embodiment of a SOC chip of the present application. The SOC chip 200 includes a plurality of storage components 100. The more storage components 100, the larger the storage capacity of the SOC chip 200.
[0028] In combination with Figure 2Each storage component 100 comprises a storage control module 101, a physical layer module 102 and a storage module 103, wherein the storage control module 101 and the storage module 103 are connected to the physical layer module 102 respectively. In an embodiment of the present application, the physical layer module 102 is a PHY, and the storage module 103 is, for example, a DRAM. In other embodiments, the storage module 103 can also be other types of memory, such as a NAND Flash, a NOR Flash, a magnetoresistive random access memory (MRAM), a phase change memory (PCRAM), a resistive random access memory (RRAM), etc.
[0029] In the present embodiment, the physical layer module 102 and the storage module 103 are prepared through a full-custom process, and the timing parameters of the physical layer module 102 are determined based on the timing parameters of the storage module 103 in the full-custom process. Both the physical layer module 102 and the storage module 103 of the present application are prepared through a full-custom process. When the physical layer module 102 is prepared, its corresponding timing parameters can be adjusted according to the timing parameters of the storage module 103, so that the physical layer module 102 and the storage module 103 can be simulated simultaneously, improving the timing accuracy and product reliability.
[0030] It is worth noting that the semi-custom process is a method of chip design based on gate arrays or standard cells. Instead of starting from the transistor level, it uses already designed sub-circuits (such as standard cell libraries) to complete the entire circuit design. Gate arrays are basic logic units (such as gate circuits) that are pre-made on chips in array form, and standard cells are pre-designed circuit modules with specific logic functions. The existing physical layer module is implemented based on the semi-custom process. Since it uses already designed sub-circuits (such as standard cell libraries) or pre-made basic logic units (such as gate circuits) on chips in array form to complete the entire circuit design, its timing parameters are fixed and cannot be adjusted. It cannot be simulated simultaneously with the storage module, and it has poor timing accuracy and insufficient product reliability.
[0031] The full-custom process is a method of designing all device and interconnection layouts manually by designers at the transistor level. First, a circuit that meets the functional requirements is designed, and then the circuit layout and wiring are optimized to achieve the best performance of the chip. The full-custom process has high design flexibility, can design circuits according to specific needs, optimize circuit details, and maximize the optimization of chip performance and the rational use of chip resources. The physical layer module 102 of the present application is prepared through a full-custom process. During the preparation process, the timing parameters of the physical layer module 102 can be optimized by referring to the timing parameters of the storage module 103, so that the timing parameters of the physical layer module 102 are determined based on the timing parameters of the storage module, making the timing of the two more matched and accurate, and the product more reliable.
[0032] The storage control module 101 is configured to transmit read-write operation instructions to the physical layer module 102, and the physical layer module 102 is configured to perform protocol processing on the read-write operation instructions, so as to obtain read-write control instructions and transmit the read-write control instructions to the storage module 103, so as to perform read-write control on the storage module 103.
[0033] Specifically, in actual application, the storage control module 101 receives a host instruction issued by a host module such as a host or a CPU, and the host instruction can be, for example, a related instruction of a memory such as a read-write command, address information, etc. The storage control module 101 is further configured to convert the received host instruction into a read-write operation instruction conforming to an interface definition of the storage module 103, and transmit the read-write operation instruction to the physical layer module 102. The physical layer module 102 is configured to perform protocol processing on the read-write operation instruction, for example, timing synchronization, voltage conversion, timing adjustment, etc. on the read-write operation instruction, so as to obtain read-write control instructions and transmit the read-write control instructions to the storage module 103, so as to perform read-write control on the storage module 103.
[0034] It can be understood that the physical layer module 102 is a bottom layer part in a communication protocol, is responsible for processing actual transmission and reception of physical signals, and is an analog-digital hybrid module between the storage control module 101 and the storage module 103. The physical layer module 102 is responsible for performing time domain synchronization and voltage domain conversion on a control signal of the storage module 103 such as a DRAM output by the storage control module 101, and performing corresponding fine adjustment on the control signal according to timing requirements of the DRAM module, and finally outputting the control signal to the corresponding DRAM. When a read command is received, the physical layer module 102 performs voltage domain conversion on a read data signal group output by the DRAM module, and then sends the read data signal group to the storage control module 101, and the storage control module 101 synchronously sends the read data signal group to the host module.
[0035] In an embodiment, in combination with Figure 3 The physical layer module 102 generally processes two types of signals, i.e. command signals and data signals output by the storage control module 101. Therefore, the physical layer module 102 includes a command processing module 104 and a data processing module 105. The command processing module 104 is configured to perform protocol processing on command signals in the read-write operation instructions, so as to transmit the command signals to the storage module 103. The data processing module 105 is configured to perform protocol processing on data signals in the read-write operation instructions, so as to transmit the data signals to the storage module 103.
[0036] Specifically, the read-write operation instruction received by the storage control module 101 from the host control module generally includes a command signal and a data signal. In the read operation, the read-write operation instruction includes the command signal. The command signal includes a read command, address information, etc., and the read command is used to inform the storage module 103 to read data, and the address information is used to inform the storage module 103 to read from which address. For example, when reading the image data stored in a specific position, the command signal in the read-write operation instruction carries the corresponding address information and the read command, which is transmitted to the storage module 103 after being processed by the command processing module 104 of the physical layer module 102. After receiving the command signal, the storage module 103 reads out the data stored in the corresponding address, and after being processed by the data processing module 105, such as voltage conversion, the data is returned to the storage control module 101 in a suitable form, and then further processed by the storage control module 101 or transmitted to the host control module.
[0037] In the write operation, the read-write operation instruction includes the command signal and the data signal. The command signal includes a write command, a target storage address, etc., and the write command is used to inform the storage module 103 to write data, and the target storage address is used to inform the storage module 103 of the storage address of the data. The data signal includes the data to be written. For example, when storing a new audio file (i.e., the data signal), the command signal in the read-write operation instruction is processed by the command processing module 104 and then transmitted to the storage module 103, informing the storage module 103 to write data and the write position. After being processed by the data processing module 105, such as time domain synchronization and voltage domain conversion, the data signal in the read-write operation instruction is transmitted to the storage module 103, so that the storage module 103 stores the data to the target storage address.
[0038] In an embodiment, in combination Figure 4 , the storage assembly 100 includes a first one-way signal bus A and a second one-way signal bus C, the input end of the first one-way signal bus A is connected to the storage control module 101, and the output end of the first one-way signal bus A is connected to the command processing module 104; the input end of the second one-way signal bus C is connected to the command processing module 104, and the output end of the second one-way signal bus C is connected to the storage module 103.
[0039] In an embodiment, the storage assembly 100 includes a bidirectional signal bus B, a read data signal bus E, and a write data signal bus D, the bidirectional signal bus B is connected to the storage control module 101 and the data processing module 105, the input end of the read data signal bus E is connected to the storage module 103, the output end of the read data signal bus E is connected to the data processing module 105, the input end of the write data signal bus D is connected to the data processing module 105, and the output end of the write data signal bus D is connected to the storage module 103.
[0040] In an embodiment, the command processing module 104 comprises a first clock unit 11 and a first level conversion unit 12, an input end of the first clock unit 11 is connected to an output end of the first unidirectional signal bus A, an input end of the first level conversion unit 12 is connected to an output end of the first clock unit 11, and an output end of the first level conversion unit 12 is connected to an input end of the second unidirectional signal bus C.
[0041] In an embodiment, the first clock unit 11 comprises a first flip-flop 13 and a delay unit 14, an input end of the first flip-flop 13 is connected to an output end of the first unidirectional signal bus A, an output end of the first flip-flop 13 is connected to an input end of the delay unit 14, and an output end of the delay unit 14 is connected to an input end of the first level conversion unit 12.
[0042] In an embodiment, the data processing module 105 comprises a second level conversion unit 17, an input end of the second level conversion unit 17 is connected to an output end of the read data signal bus E, and an output end of the second level conversion unit 17 is connected to the bidirectional signal bus B.
[0043] In an embodiment, the data processing module 105 further comprises a second clock unit 15 and a third level conversion unit 16, an input end of the second clock unit 15 is connected to the bidirectional signal bus B, an input end of the third level conversion unit 16 is connected to an output end of the second clock unit 15, and an output end of the third level conversion unit 16 is connected to an input end of the write data signal bus D.
[0044] In an embodiment, the second clock unit 15 comprises a second flip-flop, an input end of the second flip-flop is connected to the bidirectional signal bus B, and an output end of the second flip-flop is connected to an input end of the third level conversion unit 16.
[0045] In the read operation, the read-write operation instruction includes a command signal P1, the storage control module 101 transmits the command signal P1 to the command processing module 104, and also transmits a clock signal CK to the command processing module 104, the command processing module 104 receives the command signal P1 and the clock signal CK, first synchronizes in the time domain through the first flip-flop 13 in the first clock unit 11, then adjusts the timing of the synchronized signal through the delay unit 14 according to the interface timing defined by the storage module 103, the delay unit 14 here is an adjustable analog delay unit. Finally, the voltage domain conversion is performed through the first level conversion unit 12, so as to convert the command signal P1 from the SOC logic voltage domain to the voltage domain of the storage module 103 such as DRAM. When the read data is returned, the read data is read out from the storage module 103, transmitted to the second level conversion unit 17 through the read data signal bus E for voltage domain conversion, converted from the voltage domain of the storage module 103 to the voltage domain of the SOC chip, and finally transmitted to the storage control module 101 through the bidirectional signal bus B for synchronous sampling and returned to the host module.
[0046] It should be noted that the command processing module 104 shown in the present application is only a processing schematic diagram of a single read-write operation instruction. In fact, the read-write operation instruction output by the storage control module 101 is a plurality of control signals corresponding to the operation of different storage modules 103, so the physical layer module 102 needs to perform one-to-one time domain synchronization, timing adjustment and voltage domain conversion processing on each read-write operation instruction. That is, the physical layer module 102 includes a plurality of command processing modules 104. It can be understood that, since the amount of data transmitted each time by the read data depends on the bit width of the read data bus E, for example, if the bit width of the read data bus E is 32, then 32 bits of data can be transmitted each time, and the 32 bits of data need to be converted in the voltage domain through the one-to-one corresponding second level conversion unit 17.
[0047] In the write operation, the read-write operation instruction includes a command signal P1 and a data signal P2, the storage control module 101 transmits the command signal P1 to the command processing module 104, and also transmits a clock signal CK to the command processing module 104, the command processing module 104 receives the command signal P1 and the clock signal CK, first synchronizes in the time domain through the first flip-flop 13 in the first clock unit 11, then adjusts the timing of the synchronized signal through the adjustable analog delay unit 14 according to the interface timing defined by the storage module 103, and finally converts the voltage domain through the first level conversion unit 12, so as to convert the command signal P1 from the SOC logic voltage domain to the voltage domain of the storage module 103 such as DRAM. The storage control module 101 transmits the data signal P2 to the data processing module 105, and also transmits the clock signal CK to the data processing module 105, the data processing module 105 receives the data signal P2 and the clock signal CK, first synchronizes in the time domain through the second flip-flop in the second clock unit 15, then converts the voltage domain through the third level conversion unit 16, so as to convert the write data signal P2 from the SOC logic voltage domain to the voltage domain of the storage module 103 such as DRAM, and finally transmits to the storage module 103 through the write data bus D and writes to the target storage address.
[0048] It can be understood that the amount of data written each time depends on the bit width of the write data bus D, for example, the bit width of the write data bus D is 32, then 32-bit data can be written each time, and the 32-bit data needs to be synchronized in the time domain and converted in the voltage domain through the one-to-one corresponding second clock unit 15 and third level conversion unit 16.
[0049] In an embodiment, the storage assembly 100 further includes a clock tree 106 for providing a clock signal to the command processing module 104 and the data processing module 105.
[0050] It should be noted that the physical layer module 102 of the present application is relatively simple compared with the physical layer of the prior art semi-custom process preparation, it only needs to realize the corresponding timing and voltage domain conversion, and can reduce power consumption while meeting the needs.
[0051] The SOC chip of the present application integrates the physical layer module 102 and the storage module 103 on the same chip, and can realize simultaneous simulation verification of both. Specifically, the simulation verification of the physical layer module 102 includes two aspects, the first of which needs to fine-tune the delay unit according to the actual resistance-capacitance parasitic parameter extraction simulation result, to ensure that the output timing of the physical layer module 102 under various Process (process), Voltage (voltage), Temperature (temperature) meets the timing requirement details of the storage module 103; the second is to ensure the correctness of the function of the physical layer module 102 through functional verification.
[0052] Specifically, in the circuit design phase, the circuit design and layout implementation of the physical layer module 102 are completed in a full-custom manner, and then the interface timing between the physical layer module 102 and the storage module 103 is simulated and confirmed after resistance-capacitance parasitic parameter extraction to meet the timing requirement details of the storage module 103. In order to ensure more accurate simulation results, when building the environment for post-resistance-capacitance parasitic parameter extraction simulation, the resistance-capacitance parasitic parameters of the actual path between the physical layer module 102 and the storage module 103 need to be included, which can include but are not limited to the resistance-capacitance parasitic parameters of the metal layer traces inside the chip, the resistance-capacitance parasitic parameters of the devices (such as buffers) on the chip path, the specific resistance-capacitance parasitic parameters of TSV (through silicon via), HB (hybrid bonding) or RDL (redistribution layer) traces outside the chip.
[0053] In order to ensure the correctness of the behavior of the physical layer module 102 in simulation, the resistance-capacitance parasitic parameter netlist of the storage module 103 can be added to the environment. The netlist is composed of three parts: the resistance-capacitance parasitic parameter netlist of the physical layer module 102, the resistance-capacitance parasitic parameter netlist of the actual path between the physical layer module 102 and the storage module 103, and the resistance-capacitance parasitic parameter netlist of the storage module 103. Further, a test platform environment for simulation can be built outside the netlist, and the excitation output by the storage control module 101 can be simulated in this test platform environment. The simulation excitation needs to simulate the various command signals sent by the storage control module 101 to the physical layer module 102, at least including write commands and read commands. In this way, multiple groups of write commands and read commands can be sent by the physical layer module 102 in simulation, and these commands will eventually reach the storage module 103, and then the read data returned by the storage module 103 is checked through the read command, that is, whether the read data of the same address is consistent with the data written last time. During simulation, various Process (process), Voltage (voltage), Temperature (temperature) conditions can be set, and multiple groups of write-read commands can be used to ensure the correctness of the function of the physical layer module 102.
[0054] After the physical layer module 102 is prepared by the full-custom preparation process, it can be integrated into an SOC chip as a digital-analog hybrid module (for example, a standard cell) using a semi-custom process. Specifically, after the circuit and layout design of the physical layer module 102 are completed, the physical layer module 102 is integrated into an SOC chip as a hard-core macro cell using a semi-custom process. First, the file format of the current SOC chip corresponding to the process is learned through a script, and then all the timing information required under various processes, voltages, and temperatures in the resistance-capacitance parasitic parameter simulation of the physical layer module 102 is captured, and the physical layer module 102 is defined into a standard cell matching the process of the SOC chip through a script. That is, all the ports and timing of the physical layer module 102 are extracted into a standard cell for subsequent synthesis, automatic layout and routing, and related timing analysis. The timing information carried by the physical layer module 102 mainly includes: the timing requirements of the setup time and hold time of all flip-flops used for first-level synchronization, and the analog delay on the read data path.
[0055] Referring to Figure 5 , Figure 5 is a structural schematic diagram of a first embodiment of an electronic device of the present application. The electronic device 500 includes the SOC chip 510 of any of the above embodiments. The electronic device 500 may, for example, be a consumer electronics product such as a smart phone, a tablet computer, a smart TV set-top box, etc., a smart home product such as a smart home appliance, a smart security device, etc., a car electronics product such as a car entertainment system, an automatic driving assistance system, etc., or a medical electronics product, without limitation.
[0056] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A SOC chip, characterized in that, include: Multiple storage components, each of the storage components including: a physical layer module, a storage control module connected to the physical layer module, and a storage module; The storage control module transmits read / write operation instructions to the physical layer module. The physical layer module processes the read / write operation instructions to obtain read / write control instructions, which are then transmitted to the storage module for read / write control. The physical layer module and the storage module are prepared using a fully custom process, and the timing parameters of the physical layer module are determined based on the timing parameters of the storage module during the fully custom process.
2. The SOC chip according to claim 1, characterized in that, The physical layer module includes a command processing module and a data processing module. The command processing module is used to perform protocol processing on the command signals in the read / write operation instructions, and then transmit them to the storage module. The data processing module is used to perform protocol processing on the data signals in the read / write operation instructions, and then transmit them to the storage module.
3. The SOC chip according to claim 2, characterized in that, The storage component includes a first unidirectional signal bus and a second unidirectional signal bus. The input of the first unidirectional signal bus is connected to the storage control module, and the output of the first unidirectional signal bus is connected to the command processing module. The input of the second unidirectional signal bus is connected to the command processing module, and the output of the second unidirectional signal bus is connected to the storage module.
4. The SOC chip according to claim 2, characterized in that, The storage component includes a bidirectional signal bus, a read data signal bus, and a write data signal bus. The bidirectional signal bus connects the storage control module and the data processing module. The input terminal of the read data signal bus is connected to the storage module, and the output terminal of the read data signal bus is connected to the data processing module. The input terminal of the write data signal bus is connected to the data processing module, and the output terminal of the write data signal bus is connected to the storage module.
5. The SOC chip according to claim 2, characterized in that, The storage component also includes a clock tree, which provides clock signals to the command processing module and the data processing module.
6. The SOC chip according to claim 3, characterized in that, The command processing module includes a first clock unit and a first level conversion unit. The input terminal of the first clock unit is connected to the output terminal of the first unidirectional signal bus, the input terminal of the first level conversion unit is connected to the output terminal of the first clock unit, and the output terminal of the first level conversion unit is connected to the input terminal of the second unidirectional signal bus.
7. The SOC chip according to claim 6, characterized in that, The first clock unit includes a first flip-flop and a delay unit. The input terminal of the first flip-flop is connected to the output terminal of the first unidirectional signal bus, the output terminal of the first flip-flop is connected to the input terminal of the delay unit, and the output terminal of the delay unit is connected to the input and output terminals of the first level conversion unit.
8. The SOC chip according to claim 4, characterized in that, The data processing module includes: a second level conversion unit, the input of which is connected to the output of the read data signal bus, and the output of which is connected to the bidirectional signal bus.
9. The SOC chip according to claim 8, characterized in that, The data processing module further includes: a second clock unit and a third level conversion unit, wherein the input terminal of the second clock unit is connected to the bidirectional signal bus, the input terminal of the third level conversion unit is connected to the output terminal of the second clock unit, and the output terminal of the third level conversion unit is connected to the input terminal of the write data signal bus; The second clock unit includes a second flip-flop, the input of which is connected to the bidirectional signal bus, and the output of which is connected to the input of the third level conversion unit.
10. An electronic device, characterized in that, Includes the SOC chip described in any one of claims 1 to 9 above.