Broadband distributed active single-ended to differential circuit

Abstract

The invention belongs to the technical field of high-speed analog and radio-frequency integrated circuits, and discloses a broadband distributed active single-ended to differential circuit, which comprises a distributed input inductance matching network, a distributed output inductance matching network; at least one stage of single-ended signal to differential signal module is connected in parallel between the distributed input inductance matching network and the distributed output inductance matching network; wherein the single-ended signal to differential signal module comprises a Gm structure unit and a switched capacitor array; the input end of the Gm structure unit is electrically connected with the output end of the distributed input inductance matching network through a first blocking capacitor; the first output end and the second output end of the Gm structure unit are electrically connected with different signal output lines in the distributed output inductance matching network respectively; the output end of the switched capacitor array is connected between the first output end of the Gm structure unit and the distributed output inductance matching network.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-speed analog and radio frequency integrated circuit technology, in particular to a wideband distributed active single-ended to differential circuit. BACKGROUND

[0002] In modern high-speed analog and radio frequency integrated circuit (RFIC) systems, efficient conversion between single-ended and differential signals is a key step to achieve high-performance data links. Differential signals have significant advantages in terms of common-mode interference rejection, power supply noise suppression, and improvement of linearity and dynamic range, and are widely used in communication systems, analog-to-digital converters (ADCs), phase-locked loops (PLLs), and mixers. However, the signals received at the front end are often single-ended, which requires high-performance single-ended to differential (SE2D) circuits to achieve signal format conversion.

[0003] Traditional SE2D structures often use passive baluns or source-degenerated common-source topologies. However, passive baluns have large area, limited frequency range, and are not easy to integrate in silicon-based processes; while active circuits, although easy to integrate, face challenges such as gain imbalance, insufficient common-mode rejection ratio (CMRR), and limited linearity. Therefore, researchers have proposed various active SE2D topology structures to improve conversion gain while improving common-mode rejection and frequency response.

[0004] Among these structures, distributed active single-ended to differential circuits are a new solution that combines distributed amplification principles and differential driving capabilities. It uses the cascade of multiple common-source or common-gate amplification units to achieve stable gain over a wide frequency range through distributed means, and achieves excellent differential output characteristics through symmetric arrangement. This structure can significantly improve system bandwidth, suppress common-mode signals, and has strong integration scalability, making it particularly suitable for millimeter-wave frequency bands, ultra-wideband communication, and high-performance data conversion applications. However, the phase and amplitude mismatch of the output signals of existing active single-ended to differential circuits is still not ideal. SUMMARY

[0005] To overcome the deficiencies and problems of the prior art, the present application provides a wideband distributed active single-ended to differential circuit.

[0006] To solve the above technical problems, the technical solution adopted by the present application is:

[0007] A wideband distributed active single-ended to differential circuit, comprising:

[0008] A distributed input inductive matching network for inputting a single-ended signal;

[0009] A distributed output inductive matching network for outputting a differential signal;

[0010] A single-ended-to-differential signal module for converting a single-ended signal into a differential signal, at least one single-ended-to-differential signal module is connected in parallel between the distributed input inductive matching network and the distributed output inductive matching network;

[0011] The single-ended-to-differential signal module comprises a Gm structure unit for converting a single-ended signal into a differential signal, and a switched-capacitor array for providing additional capacitance compensation.

[0012] The input end of the Gm structure unit is electrically connected to the output end of the distributed input inductive matching network through a first DC blocking capacitor.

[0013] The first output end and the second output end of the Gm structure unit are respectively electrically connected to different signal output lines in the distributed output inductive matching network.

[0014] The output end of the switched-capacitor array is connected between the first output end of the Gm structure unit and the distributed output inductive matching network.

[0015] Preferably, it further comprises a voltage biasing network for providing a bias voltage.

[0016] The voltage biasing network is electrically connected to the distributed output inductive matching network, the Gm structure unit, and the switched-capacitor array, respectively.

[0017] Preferably, the Gm structure unit comprises a first transistor, a first inductor, a second transistor, a second inductor, and a third transistor.

[0018] The gate of the first transistor is electrically connected to the input end of the distributed input inductive matching network through a first DC blocking capacitor, and the gate of the first transistor is externally connected to a bias voltage VG1 through a first resistor.

[0019] The drain of the first transistor is electrically connected to one end of the second inductor and the gate of the second transistor through the first inductor, respectively.

[0020] The source of the first transistor is grounded.

[0021] The source of the second transistor is grounded.

[0022] The drain of the second transistor is electrically connected to one of the signal output lines in the distributed output inductive matching network.

[0023] The other end of the second inductor is electrically connected to the source of the third transistor.

[0024] The drain of the third transistor is electrically connected with another signal output line in the distributed output inductive matching network and the output of the switched capacitor array, respectively;

[0025] The gate of the third transistor is grounded through the second direct-current isolation capacitor and externally connected with a bias voltage VG2 through the second resistor.

[0026] Further, the switched capacitor array comprises a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor and a third capacitor.

[0027] The gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor are externally connected with a bias voltage VS1, a bias voltage VS2 and a bias voltage VS3, respectively.

[0028] The source of the fourth transistor, the source of the fifth transistor and the source of the sixth transistor are grounded, respectively.

[0029] The drain of the fourth transistor is electrically connected with one end of the first capacitor.

[0030] The drain of the fifth transistor is electrically connected with one end of the second capacitor.

[0031] The drain of the sixth transistor is electrically connected with one end of the third capacitor.

[0032] The other end of the first capacitor, the other end of the second capacitor and the other end of the third capacitor are commonly connected and serve as the output of the switched capacitor array.

[0033] Preferably, the distributed input inductive matching network comprises a single-ended signal input end, a third resistor and at least two input inductors connected in series between the single-ended signal input end and the third resistor.

[0034] The input of the Gm structure unit in the single-ended-to-differential signal conversion module at each stage is connected between two adjacent input inductors through a first direct-current isolation capacitor.

[0035] Further, the input inductor connected with the single-ended signal input end and the third resistor and the other input inductor are set to have a relationship of 1:2 in terms of inductance.

[0036] Preferably, the distributed output inductive matching network comprises two signal output lines, and the signals output by the two signal output lines together form a wideband differential signal with a phase shift of 180°.

[0037] The signal output line comprises a differential signal output end, a fourth resistor and at least two output inductors connected in series between the differential signal output end and the fourth resistor.

[0038] In each stage of the single-ended signal to differential signal module, one output terminal of the Gm structure unit is connected between two adjacent output inductors in a signal output line.

[0039] Furthermore, the ratio of the inductance of the output inductor connected to the differential signal output terminal and the fourth resistor to the inductance of the other output inductors is set to 1:2.

[0040] Compared with the prior art, the beneficial effects of the present invention are:

[0041] The broadband distributed active single-ended to differential circuit provided by this invention includes a distributed input inductor matching network, a distributed output inductor matching network, and a single-ended signal to differential signal module; at least one single-ended signal to differential signal module is connected in parallel between the distributed input inductor matching network and the distributed output inductor matching network; the single-ended signal to differential signal module includes a Gm structure unit for converting the single-ended signal to a differential signal and a switched capacitor array for providing additional capacitor compensation; this invention improves the design freedom of high broadband, while achieving gain flattening, low noise figure, and good matching, reducing chip area; by connecting the switched capacitor array between the first output terminal of the Gm structure unit and the distributed output inductor matching network, this invention can achieve low phase mismatch and low amplitude mismatch of the output signal over a wide bandwidth at different process angles and temperatures; the Gm structure unit used in this invention enables the overall circuit to achieve a low noise figure in the low-frequency band of use. Attached Figure Description

[0042] Figure 1 This is a circuit block diagram of the broadband distributed active single-ended to differential circuit described in this invention.

[0043] Figure 2 This is the schematic diagram of the active single-ended to differential circuit of the present invention.

[0044] Figure 3 This is the equivalent circuit structure diagram of the Gm structural unit of the present invention.

[0045] Figure 4 This is the schematic diagram of the switched capacitor array of the present invention.

[0046] Figure 5 This is a structural diagram of the active single-ended to differential circuit of the present invention.

[0047] Figure 6 This is a simulation curve of the S11 parameter of the active single-slip differential according to an embodiment of the present invention.

[0048] Figure 7 This is a simulation curve of the S22 parameter of the active single-slip differential according to an embodiment of the present invention.

[0049] Figure 8is a simulation curve diagram of the active single conversion difference S21 parameter of the embodiment of the present application.

[0050] Figure 9 is a simulation curve diagram of the active single conversion difference noise figure of the embodiment of the present application.

[0051] Figure 10 is a simulation curve diagram of the active single conversion difference phase mismatch and amplitude mismatch of the embodiment of the present application.

[0052] Figure 11 is a simulation curve diagram of the active single conversion difference K parameter stability factor of the embodiment of the present application.

[0053] Figure 12 is a layout of the active single conversion difference in the embodiment of the present application. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. The present application will be described in detail below with reference to the drawings and specific embodiments.

[0055] It should be understood that when used in the specification, the terms “comprise” and “include” indicate the presence of described features, integers, steps, operations, elements, and / or components, but do not exclude one or more other features, integers, steps, operations, elements, components, and / or sets thereof.

[0056] It should also be understood that the terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification of the present application, the singular forms “a”, “an” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0057] It should be further understood that the term “and / or” used in the specification of the present application means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0058] As shown in Figure 1 The present embodiment provides a wideband distributed active single-ended to differential circuit, which comprises:

[0059] a distributed input inductive matching network for inputting a single-ended signal;

[0060] a distributed output inductive matching network for outputting a differential signal;

[0061] A single-ended signal to differential signal module for converting a single-ended signal into a differential signal, at least one level of the single-ended signal to differential signal module is connected in parallel between a distributed input inductive matching network and a distributed output inductive matching network;

[0062] The single-ended signal to differential signal module comprises a Gm structure unit for converting a single-ended signal into a differential signal, and a switched capacitor array for providing additional capacitance compensation.

[0063] The input end of the Gm structure unit is electrically connected to the output end of the distributed input inductive matching network through a first DC blocking capacitor C1.

[0064] The first output end and the second output end of the Gm structure unit are respectively electrically connected to different signal output lines in the distributed output inductive matching network.

[0065] The output end of the switched capacitor array is connected between the first output end of the Gm structure unit and the distributed output inductive matching network.

[0066] The present application improves the design freedom of high bandwidth, realizes gain flattening, low noise factor and good matching, and reduces the chip area; the single-ended signal to differential signal module is provided with multiple levels in the circuit, which improves the gain and reduces the noise to a certain extent. The present application connects the switched capacitor array between the first output end of the Gm structure unit and the distributed output inductive matching network, so as to realize low phase mismatch and low amplitude mismatch of the output signal in a wide bandwidth under different process angles and temperatures; the Gm structure unit adopted in the present application can realize low noise factor in the low frequency band of the overall circuit.

[0067] As shown in Figure 1 , Figure 2 The present embodiment further comprises a voltage biasing network for providing a bias voltage.

[0068] The voltage biasing network is electrically connected to the distributed output inductive matching network, the Gm structure unit and the switched capacitor array.

[0069] The voltage biasing network provides switch biasing for the Gm structure unit and the switched capacitor array. The voltage biasing provides operating voltage biasing for the distributed output inductive matching network. One voltage biasing network can be provided for each level of the single-ended signal to differential signal module, or one voltage biasing network can be shared by all single-ended signal to differential signal modules. Figure 2As shown, two voltage bias networks can also be configured. One voltage bias network is electrically connected to the distributed output inductor matching network and the switched capacitor array in all single-ended signal to differential signal modules; the other voltage bias network is electrically connected to the Gm structure unit in all single-ended signal to differential signal modules. It should be noted that the voltage bias networks use conventional or existing voltage bias circuits, and therefore will not be described in detail here.

[0070] In a specific embodiment, such as Figure 2 As shown, the Gm structural unit includes a first transistor M1, a first inductor L1, a second transistor M2, a second inductor L2, and a third transistor M3;

[0071] The gate of the first transistor M1 is electrically connected to the input terminal of the distributed input inductor matching network through the first DC blocking capacitor C1; at the same time, the gate of the first transistor M1 is externally connected to the bias voltage VG1 through the first resistor R1.

[0072] The drain of the first transistor M1 is electrically connected to one end of the second inductor L2 and the gate of the second transistor M2 through the first inductor L1.

[0073] The source of the first transistor M1 is grounded;

[0074] The source of the second transistor M2 is grounded;

[0075] The drain of the second transistor M2 is electrically connected to a signal output line in the distributed output inductor matching network;

[0076] The other end of the second inductor L2 is electrically connected to the source of the third transistor M3;

[0077] The drain of the third transistor M3 is electrically connected to another signal output line in the distributed output inductor matching network and the output terminal of the switched capacitor array, respectively.

[0078] The gate of the third transistor M3 is grounded through the second DC blocking capacitor C2, and a bias voltage VG2 is applied externally through the second resistor R2.

[0079] like Figure 3 The diagram shown is an equivalent circuit diagram of the specific circuit of the Gm structure unit. In this embodiment, the first transistor M1, the second transistor M2, and the third transistor M3 are all NMOS transistors.

[0080] In the embodiment, the distributed input inductance matching network and the distributed output inductance matching network; the distributed input inductance matching network is connected with the gate of the first transistor M1 in the Gm structure unit in the multi-stage single-ended signal to differential signal module through the DC blocking capacitor in sequence; the distributed output inductance matching network is connected with the drain of the second transistor M2 and the drain of the third transistor M3 in the Gm structure unit in the multi-stage single-ended signal to differential signal module; the switch capacitor array is connected with the drain of the third transistor M3 of each Gm structure unit; and each switch capacitor array and Gm structure unit are connected with the voltage bias network, and the gate bias of the input common source and the post-stage common gate transistor and the switch voltage of the switch capacitor array are controlled through the voltage bias network.

[0081] In the embodiment, the first transistor M1 is used as an input common source stage nmos transistor, connected to a post-stage common source stage nmos transistor through an inductance L1, and extended to a post-stage common gate stage nmos transistor through an inductance L2. The Gm structure unit can realize wideband differential output due to the 180° phase shift of the common gate and common source output while improving the gain. The inductance L2 is inserted between the gate of the post-stage common source stage nmos transistor and the source of the post-stage common gate stage nmos transistor, effectively solving the differential mismatch of the output current of the post-stage common source stage nmos transistor and the post-stage common gate stage nmos transistor.

[0082] The voltage bias network provides the voltage VG1 and the voltage VG2 bias for the gate of the input common source stage nmos transistor and the gate of the post-stage common source stage nmos transistor, respectively.

[0083] In the embodiment, the first DC blocking capacitor C1 at the gate connection of the input common source stage nmos transistor in the Gm structure unit and the distributed input inductance matching network constitute an input stage transmission line; and the parasitic capacitance at the drain of the post-stage common source stage nmos transistor and the post-stage common gate stage nmos transistor and the distributed output inductance matching network constitute an output stage transmission line.

[0084] In the embodiment, the Gm structure unit can realize perfect differential output due to the output inversion of the post-stage common source stage nmos transistor and the post-stage common gate stage nmos transistor, but the output current mismatch of the post-stage common source stage nmos transistor and the post-stage common gate stage nmos transistor will cause the deterioration of the differential of the active balun, and the second inductance L2 is inserted to ensure the consistency of the output current of the two transmission lines of the differential output.

[0085] In the embodiment, the mismatch of the output admittance of the back-stage common-source nmos transistor and the back-stage common-gate nmos transistor in the Gm structure unit also causes the differential mismatch of the transmission line terminal, thus providing the additional capacitance compensation for the drain path of the back-stage common-gate nmos transistor can keep the admittance of the output transmission line consistent, and thus the addition of the proposed switched-capacitor array can tune the admittance consistency of the differential transmission line.

[0086] The substrate of the first transistor M1 is not connected to the high resistance R to ground, thereby reducing the noise when using a low frequency band.

[0087] In one specific embodiment, as shown in FIG. Figure 2 、 Figure 4 The switched-capacitor array includes a fourth transistor MS1, a fifth transistor MS2, a sixth transistor MS3, a first capacitor C, a second capacitor 2C, and a third capacitor 4C.

[0088] The gate of the fourth transistor MS1, the gate of the fifth transistor MS2, and the gate of the sixth transistor MS3 are respectively connected to a bias voltage VS1, a bias voltage VS2, and a bias voltage VS3.

[0089] The source of the fourth transistor MS1, the source of the fifth transistor MS2, and the source of the sixth transistor MS3 are respectively grounded.

[0090] The drain of the fourth transistor MS1 is electrically connected to one end of the first capacitor C.

[0091] The drain of the fifth transistor MS2 is electrically connected to one end of the second capacitor 2C.

[0092] The drain of the sixth transistor MS3 is electrically connected to one end of the third capacitor 4C.

[0093] The other end of the first capacitor C, the other end of the second capacitor 2C, and the other end of the third capacitor 4C are connected in common and serve as the output end of the switched-capacitor array.

[0094] In the embodiment, the voltage bias network provides the gate of the fourth transistor MS1, the gate of the fifth transistor MS2, and the gate of the sixth transistor MS3 with a voltage VS1, a voltage VS2, and a voltage VS3 bias, respectively.

[0095] The capacitance values of the first capacitor C, the second capacitor 2C, and the third capacitor 4C are in the ratio of 1:2:4.

[0096] In one specific embodiment, as shown in FIG. Figure 2 、 Figure 5As shown, the distributed input inductance matching network comprises a single-ended signal input end, a third resistor R3, and at least two input inductances connected in series between the single-ended signal input end and the third resistor R3.

[0097] The input end of the Gm structure unit in each stage of the single-ended signal to differential signal module is connected between two adjacent input inductances through a first direct-current blocking capacitor C1.

[0098] In the embodiment, the input inductance connected with the single-ended signal input end and the third resistor R3 has a relationship of 1:2 with the other input inductances in terms of inductance value.

[0099] The single-ended signal input end is configured to input a single-ended signal.

[0100] Preferably, the distributed output inductance matching network comprises two signal output lines, and the signals output by the two signal output lines together form a broadband differential signal with a phase shift of 180°.

[0101] The signal output line comprises a differential signal output end, a fourth resistor Rt, and at least two output inductances connected in series between the differential signal output end and the fourth resistor Rt.

[0102] One output end of the Gm structure unit in each stage of the single-ended signal to differential signal module is connected between two adjacent output inductances in one signal output line.

[0103] In the embodiment, the output inductance connected with the differential signal output end and the fourth resistor Rt has a relationship of 1:2 with the other output inductances in terms of inductance value.

[0104] In the embodiment, the distributed input inductance matching network and the distributed output inductance matching network both adopt a distributed inductance structure, the distributed input inductance matching network is connected with the gate of the first transistor M1 in the Gm structure unit, and the distributed output inductance matching network is connected with the drain of the second transistor M2 and the drain of the third transistor M3 in the Gm structure unit, thereby reducing the inductance area while improving the gain and optimizing the gain flatness.

[0105] As shown in Figure 3 and Figure 5 The distributed input inductance matching network comprises at least two input inductances connected in series between the single-ended signal input end and the third resistor R3R3; the input inductances comprise two end inductances LIN and a plurality of inductances LIN1 connected in series between the two end inductances LIN; and the inductance LIN has a relationship of 1:2 with the inductance LIN1 in terms of inductance value.

[0106] The signal output line in the distributed output inductance matching network comprises a differential signal output terminal, a fourth resistor Rt, and at least two output inductances connected in series between the differential signal output terminal and the fourth resistor Rt; the output inductances comprise two inductances LOUT at the head and tail and an inductance LOUT1 connected in series between the two inductances LOUT at the head and tail; the inductance LOUT and the inductance LOUT1 have a 1:2 relationship in inductance value.

[0107] In the embodiment, the input and output of the Gm structure unit are connected to the intermediate taps of the distributed inductances of the distributed input inductance matching network and the distributed output inductance matching network respectively, and input and output transmission lines are formed due to the existence of the parasitic capacitances of the transistors.

[0108] In the embodiment, the inductances LIN and LIN1 and the inductances LOUT and LOUT1 have a 1:2 relationship in inductance value, which forms the characteristics of T-type matching in the transmission line, reduces the difficulty of input and output matching, and makes the layout area more compact when implemented.

[0109] As preferred in the embodiment, as shown in Figure 2 , Figure 5 The switch capacitor array is connected to the drain output of the third transistor M3 of the Gm structure unit; the switch capacitor array provides additional capacitance compensation to ensure that the characteristic impedances and delay characteristics of the two transmission lines are consistent due to the inconsistent admittance of the second transistor M2 and the third transistor M3, which causes the characteristic impedance mismatch and delay mismatch of the two outputs.

[0110] As preferred in the embodiment, as shown in Figure 5 The voltage bias network is connected to VG1 and VG2 of the Gm structure unit and VS1, VS2 and VS3 of the switch capacitor array; when different process corners and temperatures are used, the gain, amplitude mismatch and phase mismatch will change, the bias size is adjusted by the voltage bias network, and different gears of the switch capacitor are switched to realize 0-7 gears of the capacitance, so as to realize stable gain and low amplitude and phase mismatch under different process corners and temperatures.

[0111] As preferred in the embodiment, as shown in Figure 5 The input common source stage nmos transistor of the Gm structure unit does not perform substrate connection to high resistance to ground; when the frequency used is lower than 1GHz, the use of high resistance will make the pole advance, increase the thermal noise, make the noise slope more inclined when used at low frequency, and make the low frequency noise increase close to 0.5dB, so that the low noise figure in the used frequency band is realized by canceling the use of high resistance.

[0112] As preferred in the embodiment, as shown in Figure 6As shown, the input matching curve of S11 is below -10dB in the frequency range of 0.8GHz-38GHz. The results show that the broadband distributed single-ended to differential circuit provided in this embodiment has good input matching in the frequency range of 0.8GHz-38GHz.

[0113] like Figure 7 As shown, the output matching curve of S22 is below -10dB in the frequency range of 0.8GHz-38GHz. The results show that the broadband distributed single-ended to differential circuit provided in this embodiment has good output matching in the frequency range of 0.8GHz-38GHz.

[0114] refer to Figure 8 As can be seen, the S21 gain curve has only 0.7 dB of ripple in the frequency range of 0.8 GHz to 38 GHz. The results show that the broadband distributed single-ended to differential circuit provided in this embodiment has a flat gain curve in the frequency range of 0.8 GHz to 38 GHz.

[0115] refer to Figure 9 As can be seen, the noise figure simulation curve is below 6dB in the frequency range of 0.8GHz-38GHz. The results show that the broadband distributed single-ended to differential circuit provided in this embodiment has good noise figure matching and low noise figure in the frequency range of 0.8GHz-38GHz.

[0116] refer to Figure 10 As can be seen, the amplitude and phase mismatch are within 2dB and 2° respectively in the frequency range of 0.8GHz-38GHz. The results show that the broadband distributed single-slip circuit provided in this embodiment has good low amplitude and phase mismatch in the frequency range of 0.8GHz-38GHz.

[0117] refer to Figure 11 As can be seen, the simulated stability factor curves for the K-parameter are generally above 10 in the frequency range of 0.8GHz-38GHz, which is much greater than 1. The results show that the broadband distributed single-ended to differential circuit provided in this embodiment has good stability in the frequency range of 0.8GHz-38GHz.

[0118] refer to Figure 12 As can be seen, the layout area of ​​the single-ended to differential converter shown is only 322um*265um. The results show that the broadband distributed single-ended to differential circuit provided in this embodiment has a more compact area.

[0119] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A broadband distributed active single-ended to differential circuit, characterized in that: include: Distributed input inductor matching network for single-ended input signals; Distributed output inductor matching network for outputting differential signals; A single-ended signal to differential signal module for converting a single-ended signal to a differential signal, wherein at least one of the single-ended signal to differential signal modules is connected in parallel between a distributed input inductor matching network and a distributed output inductor matching network; The single-ended signal to differential signal module includes a Gm structure unit for converting a single-ended signal into a differential signal and a switched capacitor array for providing additional capacitor compensation. The input terminal of the Gm structure unit is electrically connected to the output terminal of the distributed input inductor matching network through a first DC blocking capacitor; The first output terminal and the second output terminal of the Gm structural unit are electrically connected to different signal output lines in the distributed output inductor matching network, respectively. The output terminal of the switched capacitor array is connected between the first output terminal of the Gm structural unit and the distributed output inductor matching network.

2. The broadband distributed active single-ended to differential circuit according to claim 1, characterized in that: Also includes: Voltage biasing network used to provide bias voltage; The voltage biasing network is electrically connected to the distributed output inductor matching network, the Gm structural unit, and the switched capacitor array, respectively.

3. The broadband distributed active single-ended to differential circuit according to claim 1, characterized in that: The Gm structural unit includes a first transistor, a first inductor, a second transistor, a second inductor, and a third transistor; The gate of the first transistor is electrically connected to the input terminal of the distributed input inductor matching network through a first DC blocking capacitor; at the same time, the gate of the first transistor is externally connected to a bias voltage VG1 through a first resistor. The drain of the first transistor is electrically connected to one end of the second inductor and the gate of the second transistor through the first inductor. The source of the first transistor is grounded; The source of the second transistor is grounded; The drain of the second transistor is electrically connected to a signal output line in the distributed output inductor matching network; The other end of the second inductor is electrically connected to the source of the third transistor; The drain of the third transistor is electrically connected to another signal output line in the distributed output inductor matching network and the output terminal of the switched capacitor array, respectively. The gate of the third transistor is grounded through the second DC blocking capacitor, and a bias voltage VG2 is applied externally through the second resistor.

4. The broadband distributed active single-ended to differential circuit according to claim 3, characterized in that: The switched capacitor array includes a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a third capacitor; The gates of the fourth transistor, the fifth transistor, and the sixth transistor are respectively externally connected to bias voltages VS1, VS2, and VS3. The sources of the fourth transistor, the fifth transistor, and the sixth transistor are grounded respectively. The drain of the fourth transistor is electrically connected to one end of the first capacitor; The drain of the fifth transistor is electrically connected to one end of the second capacitor; The drain of the sixth transistor is electrically connected to one end of the third capacitor; The other ends of the first capacitor, the second capacitor, and the third capacitor are connected together and serve as the output terminal of the switched capacitor array.

5. The broadband distributed active single-ended to differential circuit according to claim 1, characterized in that: The distributed input inductor matching network includes a single-ended signal input terminal, a third resistor, and at least two input inductors connected in series between the single-ended signal input terminal and the third resistor. The input terminal of the Gm structure unit in each stage of the single-ended signal to differential signal module is connected between two adjacent input inductors through a first DC blocking capacitor.

6. The broadband distributed active single-ended to differential circuit according to claim 5, characterized in that: The ratio of the inductance of the input inductor connected to the single-ended signal input terminal and the third resistor to the inductance of the other input inductors is set to 1:

2.

7. The broadband distributed active single-ended to differential circuit according to claim 1, characterized in that: The distributed output inductor matching network includes two signal output lines, and the signals output by the two signal output lines together form a broadband differential signal with a 180° phase shift. The signal output line includes a differential signal output terminal, a fourth resistor, and at least two output inductors connected in series between the differential signal output terminal and the fourth resistor. In each stage of the single-ended signal to differential signal module, one output terminal of the Gm structure unit is connected between two adjacent output inductors in a signal output line.

8. The broadband distributed active single-ended to differential circuit according to claim 7, characterized in that: The output inductor connected to the differential signal output terminal and the fourth resistor has an inductance ratio of 1:2 with the other output inductors.

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