Laminated chip duplexer equivalent circuit for 5G terminal and duplexer thereof

Abstract

According to the laminated chip duplexer equivalent circuit for the 5G terminal and the duplexer thereof, on the basis of the LTCC low-temperature co-fired ceramic technology, the special electrical performance requirement of the novel laminated chip duplexer for the 5G terminal is met through lumped parameter model design, a transmission zero point is introduced outside a low-frequency passband through parallel resonance at the low frequency, out-of-band rejection is enhanced, and the low-frequency band pass-band pass-band rejection is improved. The high-frequency band forms a transmission zero point at the passband low-frequency band by introducing the bridging capacitor, the suppression capability of the high-frequency passband at the low frequency is enhanced, and in addition, the passband range of the high-frequency band is simply and effectively widened by introducing the series inductor at the high-frequency port. Frequency division of low-frequency signals and high-frequency signals is effectively achieved, the high-frequency passband bandwidth is effectively widened, passing of the 5G frequency band N77 and N79 frequency bands is met, and the frequency divider has the advantages of being low in loss, high in suppression, high in isolation, high in reliability, low in cost, good in consistency, suitable for large-scale production and the like. And in addition, the novel electronic component integration and miniaturization development trend is also adapted.

Description

TECHNICAL FIELD

[0001] The application discloses a novel miniaturized, low insertion loss and wide-band laminated chip-type duplexer suitable for 5G terminal wireless communication equipment. BACKGROUND

[0002] Low Temperature Co-fired Ceramic (LTCC) is a high-density packaging technology with a wide range of applications. It has become the preferred way for future electronic component integration due to its excellent electronic, mechanical and thermal properties. RF microwave components and modules designed and produced based on LTCC technology include baluns, filters, balun filters, duplexers, multiplexers, couplers, power dividers, antennas, receive front-end modules, antenna switch modules, etc. In addition to the advantages of cost and integrated packaging, it also has many advantages in terms of wiring width and spacing, low impedance metallization, design diversity and high-frequency performance. With the continuous development of modern electronic devices towards miniaturization and high frequency, they have been widely used in small electronic devices.

[0003] In the field of 4G terminal wireless communication, the communication product generally needs to separate the low frequency: DC~960MHz and the medium and high frequency band 1710~2690MHz; Now developing to 5G terminal, adding N77&N79 frequency band, among them, N77 frequency band: 3300~4200MHz, N79 frequency band: 4400~5000MHz. The increase of new frequency band means the increase of new demand, and the high frequency band needs to cover N77 and N79 frequency bands. At this time, the duplexer separating the two kinds of frequency band signals needs to widen the high frequency band pass range to 5000MHz without affecting the original demand to meet the new demand.

[0004] In general duplexer design, discrete devices are used to build frequency division function to process different frequency band input signals, which not only occupies a large pcb board area, but also is complex to debug. The laminated chip duplexer designed and produced by LTCC technology not only has excellent performance, small size, light weight, simple patching, convenient debugging, but also low cost and is suitable for mass production. SUMMARY

[0005] The application provides a novel laminated chip duplexer for 5G terminal, which adopts a lumped parameter design structure, uses a low-pass filter for low frequency, and uses a high-pass filter for high frequency. The duplexer is made by low temperature co-firing at about 900 DEG C through LTCC technology.

[0006] The application first provides a laminated chip duplexer for 5G terminal, which includes a common port, a low frequency band input / output port and a high frequency band input / output port, and is characterized in that A first inductor L1 and a second inductor L2 are connected in series between the common port and the low-frequency input / output port. A first grounding capacitor C1 is connected between the first inductor L1 and the second inductor L2. A third grounding capacitor C1 is connected between the second inductor L2 and the low-frequency input / output port 2. A second capacitor C2 is also connected between the first inductor L1 and the second inductor L2. The other end of the second capacitor C2 is connected between the second inductor L2 and the low-frequency input / output port. A fourth capacitor C4, a sixth capacitor C6, and a fourth inductor L4 are connected in series between the common port and the high-frequency input / output port. A third grounding inductor L3 is connected between the fourth capacitor C4 and the sixth capacitor C6. A fifth bridging capacitor C5 is connected between the common port 1 and the fourth capacitor C4. The other end of the fifth bridging capacitor C5 is connected between the sixth capacitor C6 and the fourth inductor L4.

[0007] The present invention also provides a stacked chip duplexer for a 5G terminal, the duplexer comprising a ceramic substrate, a connection port disposed on the bottom surface of the ceramic substrate, and a circuit structure layer disposed inside the ceramic substrate, the circuit structure layer comprising: The first layer circuit has a first metal pattern, a second metal pattern, and a third metal pattern printed on a ceramic dielectric substrate. The first end of the first metal pattern is connected to the first port P1, the third metal pattern is connected to the second port P2, the second end of the first metal pattern is connected to the fifth port P5, and the second metal pattern is connected to the sixth port P6. The second layer circuit has a second layer of first metal pattern printed on a ceramic dielectric substrate, and the second layer of first metal pattern is connected to the first dot column. The third layer circuit has metal patterns printed on a ceramic dielectric substrate, namely a third layer first metal pattern, a third layer second metal pattern, and a third layer third metal pattern; wherein the second end of the third layer second metal pattern is connected to the first port P1, the first end of the third layer first metal pattern is connected to the sixth port P6, and the third layer third metal pattern is connected to the first point post; wherein the first layer first metal pattern, the second layer first metal pattern, the third layer second metal pattern, and the fourth layer first metal pattern together form the first grounding capacitor C1; the third layer first metal pattern and the second layer first metal pattern together form the second capacitor C2; The fourth layer circuit has a first metal pattern, a second metal pattern, and a third metal pattern printed on a ceramic dielectric substrate; the third metal pattern is connected to the second port P2; the first end of the second metal pattern is connected to the fifth port P5; the second metal pattern, the first metal pattern, and the first metal pattern together form the third grounding capacitor C3. The fifth layer circuit has a fifth layer first metal pattern, a fifth layer second metal pattern, and a fifth layer third metal pattern printed on a ceramic dielectric substrate; the fifth layer second metal pattern is connected to the first port P1, the first end of the fifth layer first metal pattern is connected to the sixth port P6, and the fifth layer third metal pattern is connected to the first dot post. The sixth layer circuit has a sixth layer first metal pattern printed on a ceramic dielectric substrate; wherein the first end of the sixth layer first metal pattern is connected to the second port P2, the sixth layer second metal pattern is connected to the fifth port P5, and the sixth layer third metal pattern is connected to the first point post. The seventh layer circuit is formed by printing a first metal coil, a second metal pattern, and a third metal pattern on a ceramic dielectric substrate. The first end of the first metal coil is connected to the first point post, the second end of the first metal coil is connected to the fourth point post, the first end of the second metal pattern is connected to the second point post, and the third metal pattern is connected to the third point post.

[0008] The eighth layer circuit comprises an eighth-layer first metal coil, an eighth-layer second metal pattern, an eighth-layer third metal pattern, an eighth-layer fourth metal pattern, an eighth-layer fifth metal pattern, and an eighth-layer sixth metal coil printed on a ceramic dielectric substrate. The first end of the eighth-layer third metal pattern is connected to the second port P2; the eighth-layer fourth metal pattern is connected to the fifth port P5; the first end of the eighth-layer first metal coil is connected to the fifth terminal; the second end of the eighth-layer first metal coil is connected to the fourth terminal; the first end of the eighth-layer second metal pattern is connected to the third terminal; the eighth-layer sixth metal coil is connected to the second terminal; and the eighth-layer fifth metal pattern is connected to the first terminal. Furthermore, the first end of the sixth-layer first metal pattern, the seventh-layer third metal pattern, and the eighth-layer third metal pattern combine to form a fourth capacitor C4; the second end of the sixth-layer first metal pattern and the seventh-layer second metal pattern combine to form a fifth bridging capacitor C5. The ninth layer circuit comprises a ninth-layer first metal coil, a ninth-layer second metal pattern, a ninth-layer third metal coil, a ninth-layer fourth metal coil, and a ninth-layer fifth metal coil printed on a ceramic dielectric substrate. The ninth-layer third metal coil is connected to the first port P1, and the second end of the ninth-layer first metal coil is connected to the sixth port P6. The ninth-layer fourth metal coil is connected to the first terminal post; the ninth-layer fifth metal coil is connected to the sixth terminal post; the first end of the ninth-layer first metal coil is connected to the fifth terminal post; the first end of the ninth-layer second metal pattern is connected to the second terminal post; and the seventh, eighth, and ninth-layer second metal patterns together form a sixth capacitor C6; the seventh, eighth, and ninth-layer first metal coils together form a second inductor L2. The tenth layer circuit is formed by printing a tenth layer first metal coil, a tenth layer second metal coil, and a tenth layer third metal pattern on a ceramic dielectric substrate; wherein the first end of the tenth layer first metal coil is connected to the first point post; the second end of the tenth layer first metal coil is connected to the seventh point post; the first end of the tenth layer second metal coil is connected to the sixth point post; the second end of the tenth layer second metal coil is connected to the eighth point post; and the tenth layer third metal pattern is connected to the second point post. The eleventh layer circuit consists of an eleventh-layer first metal coil, an eleventh-layer second metal coil, and an eleventh-layer third metal coil printed on a ceramic dielectric substrate. The first end of the eleventh-layer first metal coil is connected to the seventh terminal, and the second end of the eleventh-layer first metal coil is connected to the ninth terminal. The first end of the eleventh-layer second metal coil is connected to the eighth terminal, and the second end of the eleventh-layer second metal coil is connected to the tenth terminal. The first end of the eleventh-layer third metal coil is connected to the second terminal, and the second end of the eleventh-layer third metal coil is connected to the thirteenth terminal. The twelfth layer circuit consists of a first metal coil, a second metal coil, and a third metal coil printed on a ceramic dielectric substrate. The first terminal of the first metal coil is connected to the fifteenth post, and the second terminal is connected to the ninth post. The first terminal of the second metal coil is connected to the sixteenth post, and the second terminal is connected to the tenth post. The first terminal of the third metal coil is connected to the fourteenth post, and the second terminal is connected to the thirteenth post. The thirteenth layer circuit consists of a thirteenth-layer first metal coil, a thirteenth-layer second metal coil, and a thirteenth-layer third metal coil printed on a ceramic dielectric substrate. The first end of the thirteenth-layer first metal coil is connected to the fifteenth terminal, and the second end is connected to the second port P2. The first end of the thirteenth-layer second metal coil is connected to the sixteenth terminal, and the second end is connected to the fifth port P5. The first end of the thirteenth-layer third metal coil is connected to the fourteenth terminal, and the second end is connected to the fourth port P4. The tenth-layer first metal coil, the eleventh-layer first metal coil, and the twelfth-layer first metal coil together form the first inductor L1. The second metal coil of the tenth layer, the second metal coil of the eleventh layer, and the second metal coil of the twelfth layer together form the third grounding inductor L3; the third metal pattern of the tenth layer, the third metal coil of the eleventh layer, and the third metal coil of the twelfth layer together form the fourth inductor L4.

[0009] Furthermore, the top surface of the ceramic substrate is printed with a directional marking pattern.

[0010] Furthermore, the duplexer is composed of a low-pass and a high-pass filter. The low-pass filter provides a low-frequency DC~960MHz signal channel, and the high-pass filter provides a 1710~5000MHz signal channel. The low-pass filter is composed of a first inductor L1, a second inductor L2, a first ground capacitor C1, a second capacitor C2, and a third ground capacitor C3. L2 and C2 form a parallel resonance, creating a zero in the low-pass stopband to enhance the out-of-band suppression of the low-pass filter. The high-pass filter is composed of a third ground inductor L3, a fourth inductor L4, a fourth capacitor C4, a fifth bridging capacitor C5, and a sixth capacitor C6. The fifth bridging capacitor C5 forms a transmission zero in the low-end stopband of the high-pass filter, effectively improving the stopband attenuation of the bandpass filter. In addition, the fourth inductor L4 connected in series widens the high-frequency bandwidth.

[0011] The beneficial effects of this invention are as follows: Based on LTCC (Low Temperature Co-fired Ceramic) technology, this invention employs a lumped parameter model to design and achieve the special electrical performance requirements of a novel multilayer duplexer for 5G terminals. In the low-frequency band, a transmission zero is introduced outside the low-frequency passband using parallel resonance, enhancing out-of-band suppression. In the high-frequency band, a bridging capacitor is introduced to form a transmission zero in the low-frequency passband, enhancing the high-frequency passband's low-frequency suppression capability. Furthermore, the introduction of a series inductor at the high-frequency port effectively and simply widens the high-frequency passband range. This invention not only effectively achieves frequency division between low-frequency and high-frequency signals but also effectively widens the high-frequency passband bandwidth, meeting the requirements of the 5G N77 and N79 bands. It possesses advantages such as low loss, high suppression, high isolation, high reliability, low cost, excellent consistency, and suitability for large-scale production. Additionally, it adapts to the new trend of electronic component integration and miniaturization. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the equivalent circuit of the novel stacked chip duplexer of the present invention; Figure 2 This is a three-dimensional schematic diagram of the external structure of the novel stacked plate duplexer of the present invention; Figure 3 This is a schematic diagram of the internal structure of the novel stacked plate duplexer of the present invention; Figure 4 The electrical characteristic curves of the novel stacked plate duplexer of this invention are shown. Figure 5 This is a schematic diagram of the first layer circuit planar structure of the present invention; Figure 6 This is a schematic diagram of the second-layer circuit planar structure of the present invention; Figure 7 This is a schematic diagram of the via connection planar structure between the second and third layers of circuits, between the third and fourth layers of circuits, between the fourth and fifth layers of circuits, between the fifth and sixth layers of circuits, and between the sixth and seventh layers of the present invention; Figure 8This is a schematic diagram of the third-layer circuit planar structure of the present invention; Figure 9 This is a schematic diagram of the fourth layer circuit planar structure of the present invention; Figure 10 This is a schematic diagram of the fifth layer circuit planar structure of the present invention. Figure 11 This is a schematic diagram of the sixth layer circuit planar structure of the present invention; Figure 12 This is a schematic diagram of the seventh layer circuit planar structure of the present invention; Figure 13 This is a schematic diagram of the via connection planar structure between the seventh and eighth layers of the present invention; Figure 14 This is a schematic diagram of the eighth layer circuit planar structure of the present invention; Figure 15 This is a schematic diagram of the via connection planar structure between the eighth and ninth layers of the present invention; Figure 16 This is a schematic diagram of the ninth layer circuit planar structure of the present invention; Figure 17 This is a schematic diagram of the via connection planar structure between the ninth and tenth layers of the present invention; Figure 18 This is a schematic diagram of the tenth layer circuit planar structure of the present invention; Figure 19 This is a schematic diagram of the via connection planar structure between the tenth and eleventh layers of the present invention; Figure 20 This is a schematic diagram of the eleventh layer circuit planar structure of the present invention; Figure 21 This is a schematic diagram of the via connection planar structure between the eleventh and twelfth layers of the present invention; Figure 22 This is a schematic diagram of the twelfth layer circuit planar structure of the present invention; Figure 23 This is a schematic diagram of the via connection planar structure between the twelfth and thirteenth layers of the present invention; Figure 24 This is a schematic diagram of the thirteenth layer circuit planar structure of the present invention. Detailed Implementation

[0013] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0014] A novel miniaturized stacked chip duplexer includes a substrate, terminals disposed on the outside of the substrate, and a circuit layer disposed inside the substrate, wherein the circuit layer inside the substrate has a stacked structure.

[0015] Figure 1This is the equivalent circuit diagram of a multilayer chip duplexer. The duplexer consists of a low-pass and a high-pass filter. The low-pass filter provides a low-frequency (DC~960MHz) signal channel, and the high-frequency filter provides a 1710~5000MHz signal channel. The low-pass filter is composed of a first inductor L1, a second inductor L2, a first ground capacitor C1, a second capacitor C2, and a third ground capacitor C3. L2 and C2 form a parallel resonance, creating a zero in the low-pass stopband to enhance the out-of-band rejection of the low-pass filter. The high-frequency high-pass filter is composed of a third ground inductor L3, a fourth inductor L4, a fourth capacitor C4, a fifth bridging capacitor C5, and a sixth capacitor C6. The fifth bridging capacitor C5 creates a transmission zero in the low-end stopband of the high-pass filter, effectively improving the stopband attenuation of the bandpass filter. Additionally, the fourth inductor L4 connected in series widens the high-frequency bandwidth.

[0016] ① constitutes the common port of the duplexer, ② is the low-frequency input / output port, and ③ is the high-frequency input / output port.

[0017] Figure 2 The appearance structure of the new 5G terminal stacked chip duplexer includes the following: the first port P1, the third port P3, and the fifth port P5 are grounding ports; the second port P2 is the common port of the chip duplexer; the fourth port P4 is the high-frequency bandpass output port; the sixth port P6 is the low-frequency output port; and Mark is its direction indicator.

[0018] The internal structure of a stacked plate duplexer is as follows: Figure 3 As shown, the circuit structure is distributed inside the ceramic substrate, and the circuit structure has a total of 13 layers, namely: First layer circuit 1, such as Figure 5 A first metal pattern 1-1, a second metal pattern 1-2, and a third metal pattern 1-3 are printed on a ceramic dielectric substrate. The first end 1-1a of the first metal pattern is connected to the first port P1, the third metal pattern 1-3 is connected to the second port P2, the second end 1-1b of the first metal pattern is connected to the fifth port P5, and the second metal pattern 1-2 is connected to the sixth port P6.

[0019] Second layer circuit 2, such as Figure 6 and Figure 7 A second layer of first metal pattern 2-1 is printed on a ceramic dielectric substrate, and the second layer of first metal pattern 2-1 is connected to the first dot column 27.

[0020] The third layer circuit 3, such as Figure 8Metal patterns are printed on a ceramic dielectric substrate, namely, a third-layer first metal pattern 3-1, a third-layer second metal pattern 3-2, and a third-layer third metal pattern 3-3. The second end 3-2a of the third-layer second metal pattern is connected to the first port P1, the first end 3-1a of the third-layer first metal pattern is connected to the sixth port P6, and the third-layer third metal pattern 3-3 is connected to the first point post 27. The first-layer first metal pattern 1-1, the second-layer first metal pattern 2-1, the third-layer second metal pattern 3-2, and the fourth-layer first metal pattern 4-1 together form the first grounding capacitor C1 of the low-pass filter in the schematic diagram; the third-layer first metal pattern 3-1 and the second-layer first metal pattern 2-1 together form the second capacitor C2 of the low-pass filter in the schematic circuit.

[0021] Fourth layer circuit, such as Figure 9 A fourth layer of first metal pattern 4-1, a fourth layer of second metal pattern 4-2, and a fourth layer of third metal pattern 4-3 are printed on a ceramic dielectric substrate. The fourth layer of third metal pattern 4-3 is connected to the second port P2. The first end 4-2a of the fourth layer of second metal pattern is connected to the fifth port P5. The fourth layer of second metal pattern 4-2, the third layer of first metal pattern 3-1, and the fifth layer of first metal pattern 5-1 together form the third grounding capacitor C3 of the low-pass filter in the schematic circuit.

[0022] Fifth layer circuit 5, such as Figure 10 A fifth layer first metal pattern 5-1, a fifth layer second metal pattern 5-2, and a fifth layer third metal pattern 5-3 are printed on a ceramic dielectric substrate; the fifth layer second metal pattern 5-2 is connected to the first port P1, the first end 5-1a of the fifth layer first metal pattern is connected to the sixth port P6, and the fifth layer third metal pattern 5-3 is connected to the first dot post 27.

[0023] Sixth layer circuit 6, such as Figure 11 A sixth layer first metal pattern 6-1 is printed on a ceramic dielectric substrate; wherein the first end 6-1c of the sixth layer first metal pattern is connected to the second port P2, the sixth layer second metal pattern 6-2 is connected to the fifth port P5, and the sixth layer third metal pattern 6-3 is connected to the first point post 27.

[0024] The seventh layer circuit 7, such as Figure 12 and 13 A seventh layer first metal coil 7-1, a seventh layer second metal pattern 7-2, and a seventh layer third metal pattern 7-3 are printed on a ceramic dielectric substrate; wherein the first end 7-1a of the seventh layer first metal coil is connected to the first point post 27, the second end 7-1b of the seventh layer first metal coil is connected to the fourth point post 14, the first end 7-2a of the seventh layer second metal pattern is connected to the second point post 18, and the seventh layer third metal pattern 7-3 is connected to the third point post 16.

[0025] The eighth layer circuit, such as Figure 14 and 15 On a ceramic dielectric substrate, an eighth layer is printed with a first metal coil 8-1, a second metal pattern 8-2, a third metal pattern 8-3, a fourth metal pattern 8-4, a fifth metal pattern 8-5, and a sixth metal coil 8-6. The first end 8-3a of the third metal pattern is connected to the second port P2, the fourth metal pattern 8-4 is connected to the fifth port P5, the first end 8-1a of the first metal coil is connected to the fifth post 15, the second end 8-1b of the first metal coil is connected to the fourth post 14, the first end 8-2a of the second metal pattern is connected to the third post 16, and the sixth metal coil 8-6 ​​is connected to the second post 18. The fifth metal pattern 8-5 of the eighth layer and the first point pillar 27; and the first end 6-1a of the first metal pattern of the sixth layer, the third metal pattern 7-3 of the seventh layer and the third metal pattern 8-3 of the eighth layer combine to form the fourth capacitor C4 of the high-pass filter in the schematic circuit diagram; the second end 6-1b of the first metal pattern of the sixth layer and the second metal pattern 7-2 of the seventh layer combine to form the fifth bridging capacitor C5 of the high-pass filter in the schematic circuit diagram; Ninth layer circuit 9, such as Figure 16 and 18 A ninth-layer first metal coil 9-1, a ninth-layer second metal pattern 9-2, a ninth-layer third metal coil 9-3, a ninth-layer fourth metal coil 9-4, and a ninth-layer fifth metal coil 9-5 are printed on a ceramic dielectric substrate. The ninth-layer third metal coil 9-3 is connected to the first port P1, and the second end 9-1b of the ninth-layer first metal coil is connected to the sixth port P6. The ninth-layer fourth metal coil 9-4 is connected to the first point post 27. The ninth-layer fifth metal coil 9-5 is connected to the sixth point post 17. The first end 9-1a of the ninth-layer first metal coil is connected to the fifth point post 15. The first end 9-2a of the ninth-layer second metal pattern is connected to the second point post 18. The seventh-layer second metal pattern 7-2, the eighth-layer second metal pattern 8-2, and the ninth-layer second metal pattern 9-2 together form the sixth capacitor C6 of the high-pass filter in the schematic diagram. The seventh-layer first metal coil 7-1, the eighth-layer first metal coil 8-1, and the ninth-layer first metal coil 9-1 together form the inductor L2 of the low-pass filter in the schematic diagram.

[0026] The tenth layer circuit, such as Figure 18 and 19A tenth-layer first metal coil 10-1, a tenth-layer second metal coil 10-2, and a tenth-layer third metal pattern 10-3 are printed on a ceramic dielectric substrate; wherein the first end 10-1a of the tenth-layer first metal coil is connected to the first point post 27; the second end 10-1b of the tenth-layer first metal coil is connected to the seventh point post 19; the first end 10-2a of the tenth-layer second metal coil is connected to the sixth point post 17; the second end 10-2b of the tenth-layer second metal coil is connected to the eighth point post 23; and the tenth-layer third metal pattern 10-3 is connected to the second point post 18.

[0027] Eleventh layer circuit, such as Figure 20 and 21 Eleventh-layer first metal coil 11-1, eleventh-layer second metal coil 11-2, and eleventh-layer third metal coil 11-3 are printed on a ceramic dielectric substrate; wherein the first end 11-1a of the eleventh-layer first metal coil is connected to the seventh point post 19, and the second end 11-1b of the eleventh-layer first metal coil is connected to the ninth point post 20; the first end 11-2a of the eleventh-layer second metal coil is connected to the eighth point post 23, and the second end 11-2b of the eleventh-layer second metal coil is connected to the tenth point post 22; the first end 11-3a of the eleventh-layer third metal coil is connected to the second point post 18, and the second end 11-3b of the eleventh-layer third metal coil is connected to the thirteenth point post 25.

[0028] The twelfth layer circuit, such as Figure 22 and 23 A twelfth-layer first metal coil 12-1, a twelfth-layer second metal coil 12-2, and a twelfth-layer third metal coil 12-3 are printed on a ceramic dielectric substrate. The first end 12-1a of the twelfth-layer first metal coil is connected to the fifteenth point post 21, and the second end 12-1b of the twelfth-layer first metal coil is connected to the ninth point post 20. The first end 12-2a of the twelfth-layer second metal coil is connected to the sixteenth point post 24, and the second end 12-2b of the twelfth-layer second metal coil is connected to the tenth point post 22. The first end 12-3a of the twelfth-layer third metal coil is connected to the fourteenth point post 26, and the second end 12-3b of the twelfth-layer third metal coil is connected to the thirteenth point post 25.

[0029] The thirteenth layer circuit, such as Figure 24Thirteenth-layer first metal coil 13-1, thirteenth-layer second metal coil 13-2, and thirteenth-layer third metal coil 13-3 are printed on a ceramic dielectric substrate. The first end 13-1a of the thirteenth-layer first metal coil is connected to the fifteenth point post 21, and the second end 13-1b of the thirteenth-layer first metal coil is connected to the second port P2. The first end 13-2a of the thirteenth-layer second metal coil is connected to the sixteenth point post 24, and the second end 13-2b of the thirteenth-layer second metal coil is connected to the fifth port P5. The first end 12-3a of the thirteenth-layer third metal coil is connected to the fourteenth point post 26, and the second end 12-3b of the thirteenth-layer third metal coil is connected to the fourth port P4. Furthermore, the tenth-layer first metal coil 10-1, the eleventh-layer first metal coil 11-1, and the twelfth-layer first metal coil 12-1 together form the first inductor L1 of the low-pass filter in the schematic diagram. The second metal coil 10-2 of the tenth layer, the second metal coil 11-2 of the eleventh layer, and the second metal coil 12-2 of the twelfth layer together form the third grounding inductor L3 of the low-pass filter in the schematic diagram; the third metal pattern 10-3 of the tenth layer, the third metal coil 11-3 of the eleventh layer, and the third metal coil 12-3 of the twelfth layer together form the fourth inductor L4 of the low-pass filter in the schematic diagram.

[0030] Figure 4 These are the electrical characteristic curves of a new type of LTCC low insertion loss, high suppression duplexer, where 1 is the common port, 2 is the high frequency port output, and 3 is the low frequency port output.

Claims

A 1.5G terminal uses a stacked-chip duplexer equivalent circuit, comprising a common port, a low-frequency input / output port, and a high-frequency input / output port, characterized in that... in A first inductor L1 and a second inductor L2 are connected in series between the common port and the low-frequency input / output port. A first grounding capacitor C1 is connected between the first inductor L1 and the second inductor L2. A third grounding capacitor C1 is connected between the second inductor L2 and the low-frequency input / output port. A second capacitor C2 is also connected between the first inductor L1 and the second inductor L2. The other end of the second capacitor C2 is connected between the second inductor L2 and the low-frequency input / output port. A fourth capacitor C4, a sixth capacitor C6, and a fourth inductor L4 are connected in series between the common port and the high-frequency input / output port. A third grounding inductor L3 is connected between the fourth capacitor C4 and the sixth capacitor C6. A fifth bridging capacitor C5 is connected between the common port 1 and the fourth capacitor C4. The other end of the fifth bridging capacitor C5 is connected between the sixth capacitor C6 and the fourth inductor L4.

2. A duplexer that implements the equivalent circuit of the 5G terminal stacked-chip duplexer as described in claim 1, characterized in that, The duplexer includes a ceramic substrate, a connection port disposed on the bottom surface of the ceramic substrate, and a circuit structure layer disposed inside the ceramic substrate, wherein the circuit structure layer includes: The first layer circuit has a first metal pattern (1-1), a second metal pattern (1-2), and a third metal pattern (1-3) printed on a ceramic dielectric substrate. The first end of the first metal pattern is connected to the first port P1, the third metal pattern (1-3) is connected to the second port P2, the second end of the first metal pattern is connected to the fifth port P5, and the second metal pattern (1-2) is connected to the sixth port P6. The second layer circuit has a second layer first metal pattern (2-1) printed on a ceramic dielectric substrate, and the second layer first metal pattern (2-1) is connected to the first dot column (27); The third layer circuit has metal patterns printed on a ceramic dielectric substrate, namely the third layer first metal pattern (3-1), the third layer second metal pattern (3-2), and the third layer third metal pattern (3-3); the second end of the third layer second metal pattern is connected to the first port P1, the first end of the third layer first metal pattern is connected to the sixth port P6, and the third layer third metal pattern (3-3) is connected to the first point post (27); the first layer first metal pattern (1-1), the second layer first metal pattern (2-1), the third layer second metal pattern (3-2), and the fourth layer first metal pattern (4-1) together form the first grounding capacitor C1; the third layer first metal pattern (3-1) and the second layer first metal pattern (2-1) together form the second capacitor C2; The fourth layer circuit consists of a fourth layer first metal pattern (4-1), a fourth layer second metal pattern (4-2), and a fourth layer third metal pattern (4-3) printed on a ceramic dielectric substrate; the fourth layer third metal pattern (4-3) is connected to the second port P2; the first end of the fourth layer second metal pattern is connected to the fifth port P5; the fourth layer second metal pattern (4-2), the third layer first metal pattern (3-1), and the fifth layer first metal pattern (5-1) together form the third grounding capacitor C3; The fifth layer circuit has a fifth layer first metal pattern (5-1), a fifth layer second metal pattern (5-2), and a fifth layer third metal pattern (5-3) printed on a ceramic dielectric substrate; the fifth layer second metal pattern (5-2) is connected to the first port P1, the first end of the fifth layer first metal pattern is connected to the sixth port P6, and the fifth layer third metal pattern (5-3) is connected to the first dot column (27); The sixth layer circuit is formed by printing a first metal pattern (6-1) on a ceramic dielectric substrate; wherein the first end of the first metal pattern is connected to the second port P2, the second metal pattern (6-2) is connected to the fifth port P5, and the third metal pattern (6-3) is connected to the first point post (27). The seventh layer circuit is formed by printing a first metal coil (7-1), a second metal pattern (7-2), and a third metal pattern (7-3) on a ceramic dielectric substrate. The first end of the first metal coil is connected to the first point post (27), the second end of the first metal coil is connected to the fourth point post (14), the first end of the second metal pattern is connected to the second point post (18), and the third metal pattern (7-3) is connected to the third point post (16). The eighth layer circuit is formed by printing the eighth layer first metal coil (8-1), eighth layer second metal pattern (8-2), eighth layer third metal pattern (8-3), eighth layer fourth metal pattern (8-4), eighth layer fifth metal pattern (8-5), and eighth layer sixth metal coil (8-6) on a ceramic dielectric substrate; wherein the first end of the eighth layer third metal pattern is connected to the second port P2, the eighth layer fourth metal pattern (8-4) is connected to the fifth port P5, the first end of the eighth layer first metal coil is connected to the fifth point post (15), the second end of the eighth layer first metal coil is connected to the fourth point post (14), the first end of the eighth layer second metal pattern is connected to the third point post (16), the eighth layer sixth metal coil (8-6) is connected to the second point post 18, and the eighth layer fifth metal pattern (8-5) and the first point post (27). Furthermore, the first end of the first metal pattern of the sixth layer, the third metal pattern of the seventh layer (7-3), and the third metal pattern of the eighth layer (8-3) combine to form the fourth capacitor C4; the second end of the first metal pattern of the sixth layer and the second metal pattern of the seventh layer (7-2) combine to form the fifth bridging capacitor C5; The ninth layer circuit comprises a first metal coil (9-1), a second metal pattern (9-2), a third metal coil (9-3), a fourth metal coil (9-4), and a fifth metal coil (9-5) printed on a ceramic dielectric substrate. The third metal coil (9-3) is connected to the first port P1, and the second end (9-1b) of the first metal coil is connected to the sixth port P6. The fourth metal coil (9-4) is connected to the first point post (27). The fifth metal coil... The coil (9-5) is connected to the sixth point post (17); the first end of the first metal coil of the ninth layer is connected to the fifth point post (15); the first end of the second metal pattern of the ninth layer is connected to the second point post 18; and the second metal pattern of the seventh layer (7-2), the second metal pattern of the eighth layer (8-2), and the second metal pattern of the ninth layer (9-2) together form the sixth capacitor C6; the first metal coil of the seventh layer (7-1), the first metal coil of the eighth layer (8-1), and the first metal coil of the ninth layer (9-1) together form the second inductor L2; The tenth layer circuit is formed by printing a tenth layer first metal coil (10-1), a tenth layer second metal coil (10-2), and a tenth layer third metal pattern (10-3) on a ceramic dielectric substrate; wherein the first end of the tenth layer first metal coil is connected to the first point post (27); the second end of the tenth layer first metal coil is connected to the seventh point post (19); the first end of the tenth layer second metal coil is connected to the sixth point post (17); the second end of the tenth layer second metal coil is connected to the eighth point post (23); and the tenth layer third metal pattern (10-3) is connected to the second point post (18). The eleventh layer circuit is formed by printing the first metal coil (11-1), the second metal coil (11-2), and the third metal coil (11-3) on a ceramic dielectric substrate. The first end of the first metal coil is connected to the seventh point post (19), and the second end of the first metal coil is connected to the ninth point post (20). The first end of the second metal coil is connected to the eighth point post (23), and the second end of the second metal coil is connected to the tenth point post (22). The first end of the third metal coil is connected to the second point post (18), and the second end of the third metal coil is connected to the thirteenth point post (25). The twelfth layer circuit is formed by printing a first metal coil (12-1), a second metal coil (12-2), and a third metal coil (12-3) on a ceramic dielectric substrate. The first end of the first metal coil is connected to the fifteenth post (21), and the second end of the first metal coil is connected to the ninth post (20). The first end of the second metal coil is connected to the sixteenth post (24), and the second end of the second metal coil is connected to the tenth post (22). The first end of the third metal coil is connected to the fourteenth post (26), and the second end of the third metal coil (12-3b) is connected to the thirteenth post (25). The thirteenth layer circuit consists of a thirteenth layer first metal coil (13-1), a thirteenth layer second metal coil (13-2), and a thirteenth layer third metal coil (13-3) printed on a ceramic dielectric substrate. The first end of the thirteenth layer first metal coil is connected to the fifteenth point post (21), and the second end of the thirteenth layer first metal coil is connected to the second port P2. The first end of the thirteenth layer second metal coil is connected to the sixteenth point post (24), and the second end of the thirteenth layer second metal coil is connected to the fifth port P5. The first end of the thirteenth layer third metal coil is connected to the fourteenth point post (26), and the second end of the thirteenth layer third metal coil is connected to the fourth port P4. The tenth layer first metal coil (10-1), the eleventh layer first metal coil (11-1), and the twelfth layer first metal coil (12-1) are combined to form the first inductor L1. The second metal coil of the tenth layer (10-2), the second metal coil of the eleventh layer (11-2), and the second metal coil of the twelfth layer (12-2) are combined to form the third grounding inductor L3; the third metal pattern of the tenth layer (10-3), the third metal coil of the eleventh layer (11-3), and the third metal coil of the twelfth layer (12-3) are combined to form the fourth inductor L4.

3. The duplexer as described in claim 2, characterized in that, The top surface of the ceramic substrate is printed with directional marking patterns.

4. The duplexer as described in claim 2, characterized in that, The duplexer is composed of a low-pass and a high-pass filter. The low-pass filter provides a low-frequency DC~960MHz signal channel, and the high-pass filter provides a 1710~5000MHz signal channel. The low-pass filter consists of a first inductor L1, a second inductor L2, a first ground capacitor C1, a second capacitor C2, and a third ground capacitor C3. L2 and C2 form a parallel resonance, creating a zero in the low-pass stopband to enhance the out-of-band suppression of the low-pass filter. The high-pass filter consists of a third ground inductor L3, a fourth inductor L4, a fourth capacitor C4, a fifth bridging capacitor C5, and a sixth capacitor C6. The fifth bridging capacitor C5 creates a transmission zero in the low-end stopband of the high-pass filter, effectively improving the stopband attenuation of the bandpass filter. In addition, the fourth inductor L4 connected in series widens the high-frequency bandwidth.

5. The duplexer as described in claim 2, characterized in that, The duplexer is manufactured using LTCC technology and is produced by low-temperature co-firing at around 900℃.

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