Multipath interleaving pipelined noise shaping analog-to-digital converter and residual compensation method

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a multipath interleaving pipelined noise shaping analog-to-digital converter and a residual compensation method. The multipath interleaving pipelined noise shaping analog-to-digital converter comprises a first-stage analog-to-digital converter and a second-stage analog-to-digital converter. The first-stage analog-to-digital converter comprises a four-channel time-interleaved analog-to- The first-stage analog-to-digital conversion is used for acquiring an analog signal, sampling and converting the acquired analog signal, generating a residual error and amplifying the residual error; and the second-stage analog-to-digital conversion is used for acquiring the residual error processed by the first-stage analog-to-digital conversion, performing conversion, decoding and noise reduction on the residual error, and combining the residual error with the output result of the first-stage analog-to-digital conversion. The overall energy efficiency and the overall sampling rate of the analog-to-digital converter can be improved while high resolution is achieved, the noise requirement of a single-stage successive approximation type analog-to-digital converter comparator is lowered, and the problem that a successive approximation type analog-to-digital converter is low in conversion speed is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a multi-path interleaving pipeline type noise shaping analog-to-digital converter and a residual error compensation method. BACKGROUND

[0002] In the face of 4K or 8K video streams, immersive AR or VR development, remote collaboration and cloud gaming, and other scenarios, the rapid development of unlimited transmission requires that the Wi-Fi 7 standard gradually replace the Wi-Fi 6 or 6E standard. The Wi-Fi 7 standard needs to support a 4K QAM of up to 320MHz bandwidth, and requires an analog-to-digital converter to have a high enough dynamic range of more than 68dB to cover a 160MHz baseband. At the same time, the analog-to-digital converter also needs a certain oversampling rate to reduce the design overhead of the front-end anti-aliasing filter, thereby ensuring the overall high energy efficiency of the system. In addition, the increase in the number of links also puts higher requirements on the high energy efficiency of the analog-to-digital converter itself. For high energy efficiency, time-to-digital converters benefit from process advances and successive approximation type analog-to-digital converters that use an efficient binary search method.

[0003] However, in the prior art, for a noise shaping successive approximation type analog-to-digital converter, the successive comparison characteristic of the successive approximation type analog-to-digital converter and the residual error processing process after conversion greatly limit the bandwidth of the noise shaping successive approximation type analog-to-digital converter. For a pipeline type successive approximation type analog-to-digital converter, in order to further improve the bandwidth of the pipeline type successive approximation type analog-to-digital converter, the resolution of the first stage is often reduced to reduce the quantization time. However, the large residual error of the first stage makes the design of the inter-stage amplifier very difficult, especially in the case of high speed and high precision. For a time interleaving type successive approximation type analog-to-digital converter, the error caused by the mismatch between channels often needs complex calibration to solve, thereby degrading the energy efficiency of the analog-to-digital converter. For a time-to-digital converter, especially a flash type time-to-digital converter, the resolution is often limited to less than 5 bits, so it is difficult to use in the high precision field. The traditional error feedback structure successive approximation type analog-to-digital converter needs to wait for the completion of the conversion of the successive approximation type analog-to-digital converter before processing the residual error, and the serial processing method combined with the slow conversion speed of the successive approximation type analog-to-digital converter makes the noise shaping successive approximation type analog-to-digital converter unable to be used in higher bandwidth applications. The passive error feedback method weakens the noise transfer function, thereby affecting the noise shaping effect, and an additional amplifier needs to be introduced to compensate for the attenuation.

[0004] In summary, the technical problems in the related art need to be improved. SUMMARY

[0005] The main purpose of the embodiment of the present application is to provide a multi-path interleaving pipeline type noise shaping analog-digital converter and a residual compensation method, which can realize high resolution while improving the overall energy efficiency and overall sampling rate of the analog-digital converter, reducing the noise requirement of the comparator of the single-stage successive approximation type analog-digital converter, and solving the problem of slow conversion speed of the successive approximation type analog-digital converter.

[0006] To achieve the above purpose, one aspect of the embodiment of the present application provides a multi-path interleaving pipeline type noise shaping analog-digital converter, which comprises a first-stage analog-digital conversion and a second-stage analog-digital conversion.

[0007] The first-stage analog-digital conversion comprises a four-channel time interleaving analog-digital converter.

[0008] The first-stage analog-digital conversion is used to acquire an analog signal, sample, convert, generate a residual error and amplify the residual error of the acquired analog signal.

[0009] The second-stage analog-digital conversion is used to acquire the residual error processed by the first-stage analog-digital conversion, convert, decode, denoise the residual error, and merge the output result of the first-stage analog-digital conversion.

[0010] In some embodiments, each channel of the four-channel time interleaving analog-digital converter comprises a gate voltage self-boosting sampling switch, a sampling capacitor, a capacitor-digital-analog converter, a voltage-time converter, a time-domain sub-analog-digital converter and a successive approximation type analog-digital converter.

[0011] The gate voltage self-boosting sampling switch, the sampling capacitor, the capacitor-digital-analog converter, the voltage-time converter, the time-domain sub-analog-digital converter and the successive approximation type analog-digital converter are connected in sequence.

[0012] In some embodiments, the second-stage analog-digital conversion comprises a sampling capacitor, a three-input trans-impedance amplifier, a voltage-time converter, a four-bit time-digital converter, a time-voltage converter and a residual sampling capacitor.

[0013] The time-voltage converter is two and alternately works, and the sampling capacitor, the three-input trans-impedance amplifier, the voltage-time converter, the four-bit time-digital converter, the time-voltage converter and the residual sampling capacitor are connected in sequence.

[0014] To achieve the above purpose, another aspect of the embodiment of the present application provides a residual compensation method of a multi-path interleaving pipeline type noise shaping analog-digital converter, which is applied to the multi-path interleaving pipeline type noise shaping analog-digital converter described above, and comprises the following steps:

[0015] sample the analog signal through the gate voltage bootstrap sampling switch and the sampling capacitor;

[0016] perform a front four-bit conversion on the sampled analog signal through the time domain sub-ADC, and feed back the converted signal to the capacitor digital-analog converter;

[0017] perform a back four-bit conversion on the signal switched by the capacitor digital-analog converter through the successive approximation ADC to obtain a residual signal;

[0018] amplify the residual signal through a residual amplifier;

[0019] process the amplified residual signal through the three-input trans-impedance amplifier and the voltage-time converter to obtain a time signal;

[0020] quantize the time signal through the time-to-digital converter to obtain a digital signal.

[0021] In some embodiments, the sampling of the analog signal through the gate voltage bootstrap sampling switch and the sampling capacitor comprises the following steps:

[0022] the two gate voltage bootstrap sampling switches of each channel in the first-stage ADC sample the input analog signal;

[0023] store the analog signal with a continuous sampling duration of 300 ps to the sampling capacitor.

[0024] In some embodiments, the front four-bit conversion of the sampled analog signal through the time domain sub-ADC and the feedback of the converted signal to the capacitor digital-analog converter comprises the following steps:

[0025] under the control of the clock of the time domain sub-ADC, perform a fast quantization conversion on the analog signal stored in the sampling capacitor to obtain a front four-bit digital code;

[0026] feed back the front four-bit digital code to the capacitor digital-analog converter.

[0027] In some embodiments, the back four-bit conversion of the signal switched by the capacitor digital-analog converter through the successive approximation ADC to obtain a residual signal comprises the following steps:

[0028] the capacitor digital-analog converter switches the voltage according to the front four-bit digital code;

[0029] the successive approximation ADC starts the back four-bit conversion under the control of the clock to obtain a back four-bit digital code; wherein the first bit is a redundant bit for compensating for the error.

[0030] The successive approximation analog-to-digital converter generates a reference voltage corresponding to the last four bits of the digital code through the capacitor digital-to-analog converter;

[0031] A residual signal is obtained by comparing the reference voltage with the input analog signal.

[0032] In some embodiments, the amplifying the residual signal through the residual amplifier comprises the following steps:

[0033] The residual amplifier performs an amplification process on the residual signal for a duration of 300 ps during a clock phase.

[0034] The amplified residual signal is transmitted to the sampling capacitor in the second stage analog-to-digital conversion through a signal link.

[0035] In some embodiments, the processing the amplified residual signal through the three-input transconductance amplifier and the voltage-to-time converter to obtain a time signal comprises the following steps:

[0036] The sampling capacitor in the second stage analog-to-digital conversion receives the amplified residual signal.

[0037] The three-input transconductance amplifier combines the amplified residual signal with a first residual voltage and a second residual voltage during a clock amplification phase, and the combining comprises a current conversion and summation process.

[0038] The combined residual signal is converted by the voltage-to-time converter to obtain the time signal.

[0039] In some embodiments, the obtaining the first residual voltage and the second residual voltage comprises:

[0040] The time voltage converter is controlled by the digital signal to convert the digital signal into a time interval signal.

[0041] The time interval signal is converted into the first residual voltage by a current source and a capacitor network.

[0042] The first residual voltage is sampled by the residual sampling capacitor in a capacitive proportion to obtain the second residual voltage.

[0043] The first residual voltage and the second residual voltage are used for the combining operation of the three-input transconductance amplifier in the next cycle.

[0044] The embodiments of the present application at least have the following beneficial effects: the present application provides a multi-path interleaving pipeline type noise shaping analog-to-digital converter and a residual compensation method, the scheme divides the multi-path interleaving pipeline type noise shaping analog-to-digital converter into first stage analog-to-digital conversion and second stage analog-to-digital conversion, and the first stage analog-to-digital conversion includes a four-channel time interleaving analog-to-digital converter. This hybrid architecture combines the speed advantage of the pipeline type analog-to-digital converter and the time interleaving type analog-to-digital converter, and the precision advantage of the pipeline type analog-to-digital converter and the noise shaping successive approximation type analog-to-digital converter. At the same time, this structure also overcomes the requirement of the pipeline type analog-to-digital converter for high-energy consumption residual amplifier, the speed limitation of the noise shaping successive approximation type analog-to-digital converter, and the error caused by the mismatch between channels of the time interleaving analog-to-digital converter. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 is a schematic diagram of the first stage analog-to-digital conversion architecture;

[0046] Figure 2 is a timing control schematic diagram of the first stage analog-to-digital conversion;

[0047] Figure 3 is a schematic diagram of the second stage analog-to-digital conversion architecture;

[0048] Figure 4 is a timing control schematic diagram of the second stage analog-to-digital conversion;

[0049] Figure 5 is a flowchart of the residual compensation method of the multi-path interleaving pipeline type noise shaping analog-to-digital converter. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementation described in the following exemplary embodiments does not represent all the implementations consistent with the embodiments of the present application, but is only an example of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0051] It can be understood that the terms "first", "second", and the like used in the present application can be used herein to describe various concepts, but unless specifically stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon determining" or "in response to determining".

[0052] The terms "at least one", "multiple", "each", "any", and the like used in the present application include one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0054] Before the embodiments of the present application are described in detail, first, some nouns and terms involved in the embodiments of the present application are described, and the nouns and terms involved in the embodiments of the present application are applicable to the following explanations.

[0055] ADC: analog-to-digital converter, converts analog signals to digital signals;

[0056] TDC: time-to-digital converter, converts time intervals to digital codes;

[0057] SAR ADC: successive approximation ADC, determines digital codes by successive comparison, and has both precision and speed;

[0058] Time-voltage hybrid subranging: combines time and voltage domains, converts in stages, and improves conversion efficiency and precision;

[0059] CDAC: capacitor digital-to-analog converter, uses a capacitor array to realize digital-to-analog conversion;

[0060] FIA: floating inverter type amplifier, high-speed low-power amplifier that reduces threshold voltage by floating power rail;

[0061] TVC: time-voltage converter, a circuit that converts time intervals to voltage, and is functionally reciprocal to TDC, used in the feedback loop or residual generation of time-domain ADC;

[0062] PVT: process, voltage, temperature variation, three factors that affect the performance of integrated circuits;

[0063] VTC: voltage-to-time converter, a circuit that converts a voltage difference into a time interval, used in time-domain ADCs;

[0064] time-domain-voltage-domain hybrid subranging: a hierarchical conversion, first voltage coarse quantity, then time-domain fine quantity residual error ADC architecture;

[0065] SAR: successive approximation register, a core component of analog-to-digital conversion technology, which determines the digital code corresponding to the input analog signal through successive approximation method.

[0066] An aspect of the embodiments of the present application proposes a multi-channel interleaved pipeline noise shaping analog-to-digital converter, which includes first-stage analog-to-digital conversion and second-stage analog-to-digital conversion. The first-stage analog-to-digital conversion includes a four-channel time-interleaved analog-to-digital converter, and is used to acquire an analog signal, sample, convert, generate a residual error, and amplify the residual error. The second-stage analog-to-digital conversion is used to acquire the residual error processed by the first-stage analog-to-digital conversion, and convert, decode, and denoise the residual error, and combine the output results of the first-stage analog-to-digital conversion. The analog voltage is first coarsely quantized by the first-stage analog-to-digital conversion, and then the residual error is converted to a time-domain fine quantization by the second-stage analog-to-digital conversion, so that the quantization noise is distributed in a wider frequency band, the signal-to-noise ratio is effectively improved, and the noise is dispersed by hierarchical quantization. The four-channel time-interleaved in the first-stage analog-to-digital conversion improves the overall sampling rate of the ADC, and solves the speed limitation of the single-channel pipeline ADC.

[0067] In some embodiments, each channel of the four-channel time-interleaved analog-to-digital converter includes a gate voltage self-boosting sampling switch, a sampling capacitor, a capacitor-digital-analog converter, a voltage-to-time converter, a time-domain sub-analog-to-digital converter, and a successive approximation analog-to-digital converter connected in sequence. Specifically, each channel is composed of two gate voltage self-boosting sampling switches and an 8-bit ADC. In the 8-bit ADC, there is a sampling capacitor, a capacitor-digital-analog converter, a time-domain sub-ADC composed of a voltage-to-time converter and a 4-bit TDC, and a SAR ADC. The first-stage analog-to-digital conversion improves the conversion speed of the single channel through the time-domain-voltage-domain hybrid subranging structure, while achieving high resolution, thereby solving the bottleneck between speed and accuracy in the first-stage analog-to-digital conversion of the pipeline ADC, effectively solving the error generated by the subranging structure during sampling, and reducing the residual error of the first stage. Due to the small first-stage residual error, the inter-stage amplification of the first-stage analog-to-digital conversion and the second-stage analog-to-digital conversion is performed by a high-energy-efficiency floating inverter type amplifier, which solves the problem of large power consumption of the residual error amplifier in the high-speed pipeline ADC.

[0068] In some embodiments, as shown in FIG. 2, Figure 1 Figure 1 ​is a schematic diagram of the first-stage analog-to-digital conversion architecture, which embodies the signal processing and inter-stage connection process of the first-stage analog-to-digital conversion. The first-stage adopts a time-interleaved architecture, and the four channels are illustrated by a multi-layer overlapping structure. Each channel is equipped with a gate voltage self-boosting sampling switch, a capacitor digital-to-analog converter (CDAC) generating a reference voltage in cooperation with a clock, a successive approximation register (SAR) logic performing voltage-domain coarse quantization controlled by the CDAC, a voltage-to-time converter (VTC) converting the residual voltage generated by the CDAC and the SAR into a time interval, and a 4-bit time-to-digital converter (TDC) quantizing the time signal output by the VTC. The analog signal processing process is as follows: an input signal V IN After parallel sampling through multiple channels, the CDAC and the SAR logic first complete voltage-domain coarse quantization, and the residual error is converted to the time domain by the VTC, and then the low bits are supplemented by the 4-bit TDC. The generated residual error signal is transmitted to the noise shaping TDC module in the second-stage analog-to-digital conversion through the inter-stage residual error amplifier RA controlled by the Φ RA1 , Φ RA2 clock, to achieve a two-stage sub-range conversion in the voltage-time domain, thereby improving the conversion accuracy and speed through hierarchical processing.

[0069] In some embodiments, as shown in Figure 2 , Figure 2 is a timing control schematic diagram of the first-stage analog-to-digital conversion. In the diagram, the work of each stage of circuit is coordinated by a plurality of phase clocks. The diagram includes four clock signals of Φ S1-4 , Φ TDADC1 , Φ SAR1 , and Φ RA1-2 . Φ S1-4 controls the gate voltage self-boosting sampling switch of the four channels of the first stage, and first performs a sample sampling operation in a 300 ps window; Φ TDADC1 triggers the time-domain sub-ADC after sampling to perform fast conversion of the first four bits; Φ SAR1 then starts to drive the SAR ADC to complete conversion of the last four bits; and Φ RA1-2 amplifies the residual error signal through the inter-stage residual error amplifier in a 300 ps window after conversion. The phases and pulse widths of the different clocks are accurately matched to ensure the orderly connection of the sampling, conversion, and residual error processing processes of the first stage, and to provide time-synchronized signals for the second-stage processing.

[0070] In some embodiments, the second-stage analog-to-digital conversion includes a sampling capacitor, a three-input transconductance amplifier, a voltage-to-time converter, a 4-bit time-to-digital converter, a time-to-voltage converter, and a residual error sampling capacitor connected in sequence. Specifically, the second-stage analog-to-digital conversion includes one sampling capacitor C S , one three-input G ma three-input transconductance amplifier, a voltage-to-time converter TVC, a 4-bit TDC, two time-to-voltage converters and a residual sampling capacitor C Z2 The voltage-to-time converter TVC comprises a discharge capacitor C V2T , a discharge current source I V2T , a threshold detector TCD, and the time-to-voltage converter comprises the discharge current source I T2V and the capacitor array C Z1 . The second-stage analog-to-digital conversion adopts a single-channel time-domain-voltage-domain hybrid parallel error feedback second-order noise shaping TDC, solving the problems of slow conversion speed and serial residual processing of traditional noise shaping SAR ADC. The single-channel noise shaping TDC solves the problem of difficult residual transfer in multi-channel noise shaping ADC, and solves the problem of requiring an additional amplifier in the traditional passive error feedback structure, thereby simplifying the circuit while achieving an ideal noise transfer function, while effectively reducing the load of the inter-stage amplifier, further reducing the design requirements of the amplifier.

[0071] In some embodiments, as shown in Figure 3 , Figure 3 is a schematic diagram of the architecture of the second-stage analog-to-digital conversion, representing the conversion and quantization process of the residual voltage to the time signal. The input signal is the residual voltage V res1 transferred by the first-stage analog-to-digital conversion, which is first processed by the transconductance amplifier G and temporarily stored by the sampling capacitor C S . Then the three-input transconductance amplifier G m receives V res1 and two reference voltages V Z1 , V Z2 , wherein the two reference voltages are provided by the lower capacitor array and controlled by the digital signal D<3:0>, converting the voltage difference into a current. The current drives the threshold detector TCD, converting the current signal into a time pulse T YZT by combining the current source I YZT and the capacitor C P / N . Finally, the 4-bit time-to-digital converter 4bit TDC quantizes T P / N and outputs the low-bit digital code, while feeding back the digital signal to control the lower capacitor array and update the two reference voltages V Z1 , V Z2 , realizing fine processing and iterative optimization of the residual signal.

[0072] In some embodiments, as shown in Figure 4 , Figure 4is a timing control schematic diagram of second-stage analog-to-digital conversion, representing a multi-module cross-cycle signal processing flow. The figure contains five timing tracks of the AMP amplifier, VTC voltage-time converter, TDC time-to-digital converter, and CH-A and CH-B residual processing channels. The AMP track alternates through Amp1 and Amp2 to achieve phased amplification of the residual signal; the VTC track triggers voltage-time conversion in the V2T period to convert the amplified voltage into a time signal; the TDC track performs time-to-digital quantization in the T2D period to output low-bit codes; and the CH-A and CH-B tracks complete iterative processing of the residual signal through the alternation of residual voltage sampling by Z1 and Z2 and time-to-voltage feedback by T2V, in coordination with the timing of VTC and TDC. The modules precisely connect in different cycle timing windows, such as Amp1 corresponding to Z1 and Amp2 corresponding to Z2, through pipelined cooperation to ensure continuous operation of the two-stage ADC from residual amplification, voltage-time conversion to digital quantization, and achieve high-precision analog-to-digital conversion.

[0073] To achieve the above object, another aspect of the embodiments of the present application proposes a residual compensation method for a multi-path interleaved pipelined noise-shaping analog-to-digital converter, as shown in Figure 5 Figure 5 is a flowchart of a residual compensation method for a multi-path interleaved pipelined noise-shaping analog-to-digital converter, including but not limited to steps S100 to S600:

[0074] S100: sample the analog signal through a gate voltage bootstrap sampling switch and a sampling capacitor;

[0075] S200: perform front four-bit conversion on the sampled analog signal through a time-domain sub-analog-to-digital converter, and feed back the converted signal to a capacitor digital-to-analog converter;

[0076] S300: perform back four-bit conversion on the signal switched by the capacitor digital-to-analog converter through a successive approximation analog-to-digital converter to obtain a residual signal;

[0077] S400: amplify the residual signal through a residual amplifier;

[0078] S500: process the amplified residual signal through a three-input transconductance amplifier and a voltage-time converter to obtain a time signal;

[0079] S600: quantize the time signal through a time-to-digital converter to obtain a digital signal.

[0080] ​Specifically, the residual compensation method of the multi-path interleaving pipeline type noise shaping analog-to-digital converter realizes high-performance conversion through two-stage analog-to-digital conversion, timing accurate cooperation and cross-domain hierarchical optimization. First, the gate voltage bootstrap sampling switch and the time domain sub-analog-to-digital converter quickly complete the first four bits of coarse quantization, and the capacitor digital analog converter feedback improves the conversion accuracy of the last four bits of the successive approximation type analog-to-digital converter; then the residual amplifier strengthens the signal, the three-input transconductance amplifier combines multiple source voltages, the voltage-time converter and the time digital converter complete the cross-domain iteration of voltage-time-digital, and synchronously generate the next period residual to ensure the pipeline continuity; finally, the time digital converter quantization and the time voltage converter feedback closed loop rely on the capacitor ratio and redundant bit compensation PVT fluctuation to realize the cooperative gain of high-speed sampling, low noise and high precision, and balance the conversion speed and precision. The pipeline type ADC, time interleaving type ADC, time domain ADC and noise shaping ADC are combined. While having the advantages of each architecture ADC, the shortcomings of each architecture itself are avoided. Due to the high resolution of the first stage analog-to-digital conversion and the low sampling capacitor of the second stage analog-to-digital conversion, the requirement of the inter-stage amplifier is greatly reduced, so a low-power FIA can be used for inter-stage amplification, thereby improving the overall energy efficiency of the ADC.

[0081] In some embodiments, in step S100, two gate voltage bootstrap sampling switches of each channel in the first stage analog-to-digital conversion sample the input analog signal, and store the analog signal with a continuous sampling duration of 300ps to the sampling capacitor. Specifically, the two gate voltage bootstrap sampling switches of a single channel in the four-channel time interleaving analog-to-digital converter of the first stage analog-to-digital conversion capture the input analog signal. The bootstrap circuit eliminates the non-linear error caused by the threshold voltage variation by dynamically adjusting the switch tube gate voltage, ensuring high accuracy even at high frequency sampling. In Figure 1 the control of the sampling signal Φ S1 , the captured analog signal is stored to the sampling capacitor in the channel. The 300ps sampling window design takes into account the signal stable establishment time and overall sampling rate requirement, providing a stable voltage reference for subsequent quantization.

[0082] In some embodiments, in step S200, under the control of the clock of the time domain sub-analog-to-digital converter, the analog signal stored in the sampling capacitor is quickly quantized and converted for the first four bits to obtain the first four bits of digital code, and the first four bits of digital code are fed back to the capacitor digital analog converter. Specifically, after sampling is completed, the analog signal stored in the sampling capacitor is quickly quantized and converted for the first four bits under the control of the clock Φ Figure 1 in the time domain sub-analog-to-digital converter TDADC1The first four bits of the analog signal stored in the sampling capacitor are quantized and converted rapidly. The time-domain conversion maps the voltage difference to the time interval, and the high-precision characteristics of time measurement are used to improve the quantization speed. The first four bits of the digital code obtained by conversion are quickly fed back to the capacitor digital analog converter, i.e., the main CDAC. The digital code controls the switching state of the capacitor array in the CDAC, adjusts the reference voltage configuration, and prepares for the subsequent successive approximation comparison of the SAR ADC.

[0083] In some embodiments, in step S300, the capacitor digital analog converter switches the voltage according to the first four bits of the digital code, and the SAR ADC starts the conversion of the last four bits under the control of the clock to obtain the last four bits of the digital code, wherein the first bit is a redundant bit for compensating the error. The SAR ADC generates the reference voltage corresponding to the last four bits of the digital code through the capacitor digital analog converter, and compares the reference voltage with the input analog signal to obtain the residual signal. Specifically, after the capacitor digital analog converter completes the voltage switching according to the first four bits of the digital code, the SAR ADC starts the conversion of the last four bits under the control of the clock Figure 1 in the middle clock phase SAR1 . The redundant bit is designed to compensate for the possible comparator mismatch error and improve the conversion accuracy. The SAR ADC generates the reference voltage corresponding to the current digital code through the capacitor digital analog converter, and compares the reference voltage with the input signal. The comparison result drives the successive approximation register logic to update the digital code, and finally generates the residual signal, i.e., the voltage difference between the input analog signal and the current best estimate.

[0084] In some embodiments, in step S400, the residual amplifier amplifies the residual signal for a duration of 300 ps during the clock phase, and transmits the amplified residual signal to the sampling capacitor in the second-stage analog-to-digital conversion through the signal link. Specifically, the inter-stage residual amplifier amplifies the residual signal generated by the first-stage analog-to-digital conversion for a duration of 300 ps during the clock Figure 1 in the middle clock phase RA1 . The gain of 16 ensures that the residual signal is boosted to a sufficient amplitude to compensate for the noise in the second-stage analog-to-digital conversion while avoiding signal saturation. The amplified residual signal is transmitted to the sampling capacitor of the second stage through a low-impedance buffer. An anti-aliasing filter structure is integrated in the signal link to suppress high-frequency noise and ensure the quality of the residual signal transmitted to the second-stage analog-to-digital conversion.

[0085] In some embodiments, in step S500, the sampling capacitor in the second stage analog-to-digital conversion receives the amplified residual signal, and the three-input transconductance amplifier combines the amplified residual signal with the first residual voltage and the second residual voltage in the clock amplification stage, and the combination includes current conversion and summation processing. The combined residual signal is converted by the voltage-time converter to obtain a time signal. Specifically, after the second stage sampling capacitor receives the amplified residual signal, the three-input transconductance amplifier processes the signal in the clock amplification stage. Figure 4 Amp1 The three inputs are the amplified residual signal and the two residual voltages, and the three-input transconductance amplifier converts these voltage signals into current signals and sums them at the node, realizing the combination of multiple signals. The summed current signal drives the voltage-time converter, which converts the current signal into a time interval signal T P / N by charging and discharging the capacitor. The time interval is proportional to the size of the input residual voltage, realizing the mapping conversion between the voltage and time domains.

[0086] In some embodiments, the step of obtaining the two residual voltages includes: controlling the time-to-digital converter by a digital signal, converting the digital signal into a time interval signal, converting the time interval signal into the first residual voltage by a current source and a capacitor network, sampling the first residual voltage by a residual sampling capacitor in proportion to the capacitance to obtain the second residual voltage, and using the first residual voltage and the second residual voltage for the combination operation of the three-input transconductance amplifier in the next cycle. Specifically, the time-to-digital converter completes the quantization of the time signal and outputs a digital signal D<3:0>. The digital signal is fed back to the time-to-voltage converter, which controls the internal current source and capacitor network according to the digital signal, first converts the digital signal into a time interval signal, and then converts the time interval signal into the first residual voltage V Z1 by charging and discharging the capacitor network by the current source. This process realizes the conversion from time to voltage through the charging and discharging law of the capacitor. At the same time, the residual sampling capacitor samples the generated first residual voltage V Z1 in proportion to the preset capacitance, and the capacitance ratio is relatively stable under PVT variation, which can accurately obtain the second residual voltage V Z2 needed in the next cycle. Through such timing misalignment and capacitance ratio sampling, the continuous iteration of the residual processing of the two-stage analog-to-digital converter is ensured.

[0087] In some embodiments, in step S600, the time-to-digital converter quantizes the input time interval signal T T20 during the clock phase Φ P / N . The TDC with vernier structure realizes high-precision time measurement and generates a 4-bit digital output D<3:0>, i.e., a digital signal, completing the conversion from the time domain to the digital domain. ​

[0088] In some embodiments, the combination Figure 1 and Figure 2 is shown. First, the sampling capacitor (Cs) of the time-domain sub-ADC and the main CDAC (CMDAC) are controlled by the sampling signal Φ S1 to sample the signal for 300 ps. After sampling is completed, the time-domain sub-ADC is controlled by Φ TDADC1 to quickly convert the first four bits, and the conversion result is quickly fed back to the main CDAC. After the main CDAC completes switching, the SAR ADC is controlled by ΦSAR1to convert the last four bits, and the first-stage residual signal is generated through the main CDAC, wherein the first bit of the SAR ADC is a redundant bit. When the residual signal is generated, the inter-stage residual amplifier (RA) is controlled by Φ RA1 to amplify the residual for 300 ps, and the inter-stage gain is 16. After amplification is completed, the second-stage noise-shaping TDC starts to convert the last four bits. The ADC of the first-stage analog-digital conversion adopts a time-domain-voltage-domain subranging structure. This structure uses a time-domain ADC to perform coarse quantization, not only accelerating the quantization of the first four bits, solving the speed limitation of a single channel, but also avoiding invalid large-capacitance switching on the main CDAC, thereby reducing switching power consumption. In addition, the intra-stage redundancy inserted in the SAR ADC can effectively solve the error generated by the two sampling networks during sampling and the mismatch error in the time-domain ADC. Through the first-stage analog-digital conversion, high-speed conversion is realized while high resolution is achieved, and the structure can also effectively solve the problem of sampling error in the subranging ADC.

[0089] In combination Figure 3 and Figure 4 is shown, in the second-stage analog-digital conversion process in terms of the noise-shaping circuit structure, after the amplifier completes Φ Amp1 amplification, in the voltage-time conversion phase Φ V2T , the three-input Gm stage adds the processed residual voltage V res1 and V Z1 to the amplifier output G·V Z2 on the capacitor CS, and converts them into a time signal T V2T through the current source I P / N and the TCD. The generated time signal is transmitted to the 4-bit TDC and the TVC of CH-A for quantization and time-voltage conversion, corresponding to the Φ T20 phase and the Φ T2VPhase. And in the process of voltage-time-voltage conversion, the sum signal has been amplified. Since the voltage-time-voltage amplification factor is determined by the current and the proportion of the capacitor, the amplification factor is relatively stable. At the same time, this process is carried out at the same time as the TDC quantization, which does not occupy additional time, thereby greatly improving the working speed of the second stage. At the same time as the TDC quantization, the residual voltage V Z2 is generated. Since the input of VTC only needs to be kept to generate the required time signal, when the time signal is transmitted to the TDC, the residual voltage V Z2 on the CDAC can be sampled by the residual sampling capacitor, thereby generating the residual capacitor V Z1 required for the next period. And the ratio between the residual voltage V Z2 and V Z1 is determined by the proportion of the capacitor, so it can remain stable under PVT changes. When the TDC completes quantization, the digital output D<3:0> is fed back to the CDAC that completes the time-voltage conversion, thereby generating the residual voltage V Amp2 required for the next period. After the end of the Φ Amp2 phase, the working process of the second stage is the same as above. The second stage analog-to-digital conversion adopts a hybrid time domain-voltage domain parallel second-order error feedback TDC, which not only speeds up the quantization process, but also processes the residual process in parallel with the quantization process, thereby greatly improving the working speed of the noise shaping. And due to the high stability of the voltage-time-voltage conversion and the proportion of the capacitor, the noise transfer function of this noise shaping TDC is also relatively stable. In addition, compared with the traditional passive error feedback, this noise shaping method will not bring a large residual signal attenuation, thereby avoiding the need for additional gain, thereby reducing power consumption. The noise shaping TDC used in the second stage analog-to-digital conversion not only effectively improves the conversion and noise shaping speed, but also efficiently realizes a relatively stable and ideal second-order noise shaping transfer function. In addition, this structure can also reduce the load capacitance of the front-end amplifier, thereby improving the overall energy efficiency of the system.

[0090] The embodiments described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0091] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and can include more or fewer steps than the figures shown, or combine certain steps, or different steps.

[0092] The apparatus embodiments described above are merely illustrative, and units described as separate components may or may not be physically separate, i.e., may be located in one place or distributed over multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purposes of the embodiments.

[0093] Those skilled in the art can understand that all or some of the steps in the method disclosed above, the functional modules / units in the system and the device can be implemented as software, firmware, hardware and appropriate combinations thereof.

[0094] The terms "first", "second", "third", "fourth" and the like in the description of the application and in the claims, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of these terms herein is merely for distinguishing between the comparable objects and the use of these terms in the description and the claims should not be construed as requiring that the application is limited to the order in which the steps are described. Moreover, the use of the terms "first", "second", "third", "fourth", and the like, if any, in the description of the application and in the claims, is not necessarily used for characterizing a particular sequential order, or chronology, or hierarchy. It is to be understood that the use of these terms herein is merely for distinguishing between comparable objects, and the use of these terms in the description and the claims should not be construed as requiring that the application is limited to the order in which the steps are described. Furthermore, the terms "comprise", "comprising", "include", "including", and the like, if any, set forth in the description and the claims of the application, are used in the sense of "including" and not the sense of "consisting only of", and are not intended to exclude other steps, components, elements, items, or options that are not recited or that are otherwise well known in the art. In addition, it is to be understood that the use of the singular herein, including, but not limited to, the use of "a" or "an" herein, is only to illustrate a possible implementation of the application and should not be construed to exclude beforehand the use of "a plurality of" or "plural" thereof to describe the same situation(s).

[0095] It should be understood that, in the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the relationship between the associated objects, which means that there can be three relationships, for example, "A and / or B" can mean that there are only A, only B, and A and B at the same time. The character " / " generally represents that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can mean a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0096] In addition, the functional units in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be implemented in the form of hardware or software functional units.

[0097] The preferred embodiments of the present application are described above with reference to the accompanying drawings, and are not intended to limit the scope of the present application. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and spirit of the present application shall fall within the scope of the present application.

Claims

1. A multi-channel interleaved pipeline noise-shaping analog-to-digital converter, characterized in that, The multi-channel interleaved pipeline noise-shaping analog-to-digital converter includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter; The first-stage analog-to-digital converter includes a four-channel time-interleaved analog-to-digital converter; The first-stage analog-to-digital converter is used to acquire analog signals, and to sample, convert, generate residuals, and amplify the acquired analog signals. The second-level analog-to-digital conversion is used to obtain the residual after the first-level analog-to-digital conversion, and to convert, decode, denoise, and merge the residual with the output of the first-level analog-to-digital conversion.

2. The multi-channel interleaved pipeline noise-shaping analog-to-digital converter according to claim 1, characterized in that, Each channel of the four-channel time-interleaved analog-to-digital converter includes a gate voltage bootstrap sampling switch, a sampling capacitor, a capacitor digital-to-analog converter, a voltage-to-time converter, a time-domain sub-analog-to-digital converter, and a successive approximation analog-to-digital converter. The gate voltage bootstrap sampling switch, the sampling capacitor, the capacitor digital-to-analog converter, the voltage-to-time converter, the time-domain sub-analog-to-digital converter, and the successive approximation analog-to-digital converter are connected in sequence.

3. The multi-channel interleaved pipeline noise-shaping analog-to-digital converter according to claim 2, characterized in that, The second-stage analog-to-digital converter includes: a sampling capacitor, a three-input transconductance amplifier, a voltage-to-time converter, a four-bit time-to-digital converter, a time-to-voltage converter, and a residual sampling capacitor; The time-voltage converter consists of two components that operate alternately. The sampling capacitor, the three-input transconductance amplifier, the voltage-time converter, the four-bit time-to-digital converter, and the residual sampling capacitor are connected in sequence.

4. A residual compensation method for a multi-channel interleaved pipelined noise-shaping analog-to-digital converter, characterized in that, The method is applied to the multi-interleaved pipelined noise-shaping analog-to-digital converter of claim 3, and the method includes the following steps: The analog signal is sampled using the gate voltage bootstrap sampling switch and the sampling capacitor; The time-domain sub-analog-to-digital converter performs the first four-bit conversion on the sampled analog signal, and the converted signal is fed back to the capacitor digital-to-analog converter. The signal after switching from the capacitor digital-to-analog converter is converted to its last four bits by the successive approximation analog-to-digital converter to obtain the residual signal. The residual signal is amplified by a residual amplifier; The amplified residual signal is processed by the three-input transconductance amplifier and the voltage-time converter to obtain a time signal; The time signal is quantized by the time-to-digital converter to obtain a digital signal.

5. The residual compensation method for a multi-channel interleaved pipeline noise-shaping analog-to-digital converter according to claim 4, characterized in that, The sampling of the analog signal using the gate voltage bootstrap sampling switch and the sampling capacitor includes the following steps: In the first-stage analog-to-digital conversion, the two gate voltage bootstrap sampling switches of each channel sample the input analog signal; The analog signal, which is continuously sampled for 300 ps, ​​is stored in the sampling capacitor.

6. The residual compensation method for a multi-channel interleaved pipeline noise-shaping analog-to-digital converter according to claim 5, characterized in that, The step of performing the first four-bit conversion on the sampled analog signal using the time-domain sub-analog-to-digital converter, and then feeding the converted signal back to the capacitor-based digital-to-analog converter, includes the following steps: Under the control clock of the time-domain sub-analog-to-digital converter, the analog signal stored in the sampling capacitor is subjected to fast quantization conversion of the first four bits to obtain the first four bits of digital code. The first four digits are fed back to the capacitor-to-digital converter.

7. The residual compensation method for a multi-channel interleaved pipeline noise-shaping analog-to-digital converter according to claim 6, characterized in that, The step of converting the signal switched by the capacitor digital-to-analog converter to its last four bits using the successive approximation analog-to-digital converter to obtain the residual signal includes the following steps: The capacitor-to-digital converter switches voltages according to the first four digits of the digital code. The successive approximation analog-to-digital converter starts the last four-bit conversion under clock control to obtain the last four-bit digital code; wherein, the first bit is a redundant bit to compensate for the error; The successive approximation analog-to-digital converter generates a reference voltage corresponding to the last four digits of the digital code through the capacitor-to-digital converter. The residual signal is obtained by comparing the reference voltage with the input analog signal.

8. The residual compensation method for a multi-channel interleaved pipeline noise-shaping analog-to-digital converter according to claim 4, characterized in that, The amplification of the residual signal by the residual amplifier includes the following steps: The residual amplifier amplifies the residual signal for 300 ps during the clock phase. The amplified residual signal is transmitted to the sampling capacitor in the second-stage analog-to-digital converter via a signal link.

9. The residual compensation method for a multi-channel interleaved pipeline noise-shaping analog-to-digital converter according to claim 8, characterized in that, The process of processing the amplified residual signal using the three-input transconductance amplifier and the voltage-time converter to obtain a time signal includes the following steps: The sampling capacitor in the second-stage analog-to-digital conversion receives the amplified residual signal; The three-input transconductance amplifier combines the amplified residual signal with the first residual voltage and the second residual voltage during the clock amplification stage. The combination includes current conversion and summation processing. The voltage-time converter converts the merged residual signal to obtain the time signal.

10. The residual compensation method for a multi-channel interleaved pipeline noise-shaping analog-to-digital converter according to claim 9, characterized in that, The steps for obtaining the first residual voltage and the second residual voltage include: The digital signal is used to control the time-voltage converter, which inverts the digital signal into a time interval signal. The time interval signal is converted into the first residual voltage through a current source and a capacitor network; The second residual voltage is obtained by sampling the first residual voltage according to the capacitance ratio using the residual sampling capacitor; The first residual voltage and the second residual voltage are used for the merging operation of the three-input transconductance amplifier in the next cycle.

Images