Comparator, analog-to-digital converter and offset elimination method thereof
By combining a comparator circuit, an offset calculation circuit, and a hybrid offset voltage generation circuit, and utilizing charge transfer operations and voltage division mechanisms, the problems of increased circuit complexity and area in existing technologies are solved, achieving more accurate offset elimination and improved performance.
Patent Information
- Application Number
- CN202410610985.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-16
- Publication Date
- 2025-11-18
AI Technical Summary
In the prior art, the offset cancellation mechanism of the comparator requires an increase in the number of circuits to achieve a smaller offset value, which leads to an increase in circuit complexity and area, and may also introduce more noise and reduce circuit efficiency.
A comparator circuit, an offset calculation circuit, a hybrid offset voltage generation circuit, and an offset elimination circuit are employed. A correction voltage is generated through charge transfer operation to eliminate the offset. The hybrid offset voltage generation circuit uses a voltage divider mechanism and a switching capacitor circuit to reduce the number of circuit components and improve accuracy.
While reducing circuit area and cost, more accurate offset elimination is achieved, improving the overall performance and efficiency of the comparator.
Smart Images
Figure CN120979451A_ABST
Abstract
Description
Technical Field
[0001] This case concerns comparators, particularly comparators with offset cancellation mechanisms, analog-to-digital converters using these comparators, and offset cancellation methods. Background Technology
[0002] Comparators are commonly used in analog-to-digital converters for quantization. To provide better performance, it is usually necessary to eliminate the offset in the comparator. In existing technologies, after offset elimination mechanisms, the offset typically converges to a small value. To further reduce this offset to an even smaller value, or even to zero, it is usually necessary to increase the number of circuits used in the offset elimination mechanism to generate a finer correction voltage. This increases the overall circuit complexity and area. In addition, more circuit components may introduce more noise, causing a decrease in circuit performance. Summary of the Invention
[0003] In some embodiments, one of the objectives of this invention is (but not limited to) to provide comparators, analog-to-digital converters and offset cancellation methods thereof with offset cancellation mechanisms to improve the shortcomings of prior art.
[0004] In some embodiments, the comparator includes a comparator circuit, an offset calculation circuit, a hybrid offset voltage generation circuit, and an offset cancellation circuit. The comparator circuit generates a decision signal based on an input signal. The offset calculation circuit calculates an offset of the comparator circuit based on the decision signal to generate multiple control signals. The hybrid offset voltage generation circuit selects a first reference voltage and a second reference voltage from multiple reference voltages based on the multiple control signals, and performs a charge transfer operation using the first reference voltage and the second reference voltage to generate multiple correction voltages. The offset cancellation circuit cancels the offset based on the multiple correction voltages.
[0005] In some embodiments, the analog-to-digital converter includes multiple comparator circuits, an offset calculation circuit, a hybrid offset voltage generation circuit, and multiple offset cancellation circuits. The multiple comparator circuits generate multiple decision signals based on an input signal. The offset calculation circuit calculates an offset for the multiple comparator circuits based on the multiple decision signals to generate multiple sets of control signals. The hybrid offset voltage generation circuit selects a first reference voltage and a second reference voltage from multiple reference voltages based on the multiple sets of control signals, and performs a charge transfer operation using the first reference voltage and the second reference voltage to generate multiple sets of correction voltages. The multiple offset cancellation circuits cancel the offset based on the multiple sets of correction voltages.
[0006] In some embodiments, the offset cancellation method includes the following operations: generating a decision signal via a comparator circuit based on an input signal; calculating an offset of the comparator circuit based on the decision signal to generate a plurality of control signals; selecting a first reference voltage and a second reference voltage from a plurality of reference voltages based on the plurality of control signals to perform a charge transfer operation using the first reference voltage and the second reference voltage to generate a plurality of correction voltages; and canceling the offset of the comparator circuit based on the plurality of correction voltages.
[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Attached Figure Description
[0008] Figure 1 A schematic diagram of a comparator is provided based on some embodiments of this invention;
[0009] Figure 2 Drawing based on some embodiments of this case Figure 1 A schematic diagram of the comparator circuit and offset cancellation circuit in the diagram;
[0010] Figure 3A Drawing based on some embodiments of this case Figure 1 A schematic diagram of the hybrid offset voltage generation circuit in the diagram;
[0011] Figure 3B Drawing based on some embodiments of this case Figure 1 A schematic diagram of the hybrid offset voltage generation circuit in the diagram;
[0012] Figure 4A Drawing based on some embodiments of this case Figure 3A A schematic diagram of a switching capacitor circuit in the image;
[0013] Figure 4B Drawing based on some embodiments of this case Figure 3B A schematic diagram of a switching capacitor circuit in the image;
[0014] Figure 5A Drawing based on some embodiments of this case Figure 3A A schematic diagram of a switching capacitor circuit in the image;
[0015] Figure 5B Drawing based on some embodiments of this case Figure 3B A schematic diagram of a switching capacitor circuit in the image;
[0016] Figure 6A A schematic diagram of an analog-to-digital converter is provided based on some embodiments of this case.
[0017] Figure 6B Drawing based on some embodiments of this case Figure 6AA schematic diagram of a hybrid offset voltage generation circuit; and
[0018] Figure 7 An operation flowchart of an offset elimination method is drawn according to some embodiments of this case. Detailed Implementation
[0019] All terms used herein have their common meanings. The definitions of the terms used in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this document. Similarly, this document is not limited to the various embodiments shown in this specification.
[0020] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.
[0021] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the terms first, second, third, etc., are used to describe and distinguish individual elements. Therefore, a first element in this document may also be referred to as a second element without departing from the intent of this case. For ease of understanding, similar elements in the various diagrams will be assigned the same reference numerals.
[0022] Figure 1 A schematic diagram of a comparator 100 is provided according to some embodiments of this invention. The comparator 100 includes a comparator circuit 110, an offset calculation circuit 120, a hybrid offset voltage generation circuit 130, and an offset cancellation circuit 140. The comparator circuit 110 may be, but is not limited to, a dynamic comparator circuit with positive feedback, which generates a decision signal SD based on an input signal VIN. The offset calculation circuit 120 calculates the offset of the comparator circuit 110 based on the decision signal SD, thereby generating a plurality of control signals SC. In some embodiments, the offset calculation circuit 120 may be implemented by a digital signal processing circuit performing a statistical operation. The offset calculation circuit 120 performs this statistical operation (e.g., may be, but is not limited to, an averaging operation) based on the decision signal SD to estimate the offset of the comparator circuit 110 and accordingly generate a plurality of control signals SC.
[0023] The hybrid offset voltage generation circuit 130 can generate voltages from multiple reference voltages (e.g., based on the multiple control signals SC) according to the multiple reference voltages SC. Figure 3AMultiple reference voltages (VREF1 to VREFN) are used to select a first reference voltage and a second reference voltage. A charge transfer operation is then performed using these first and second reference voltages to generate multiple correction voltages VCP and VCN. The configuration of the hybrid offset voltage generation circuit 130 will be explained later with reference to other figures. The offset cancellation circuit 140 can eliminate the offset of the comparator circuit 110 based on the multiple correction voltages VCP and VCN. This reduces the negative impact of the offset on the comparator circuit 110 (e.g., the inclusion of unwanted noise), thereby improving the overall performance of the comparator 100.
[0024] Figure 2 Drawing based on some embodiments of this case Figure 1 A schematic diagram of comparator circuit 110 and offset cancellation circuit 140 is shown. Comparator circuit 110 includes input pair circuit 212 and latch circuit 214. Input pair circuit 212 and latch circuit 214 are coupled to nodes O1 and O2. Latch circuit 214 can perform the aforementioned positive feedback mechanism. Input pair circuit 212 can compare input signal VIN+ and input signal VIN- when clock signal CLKC is at a preset level (high level in this example) to output decision signal SD+ and decision signal SD- via nodes O1 and O2, respectively. In some embodiments, Figure 1 The input signal VIN can be a set of differential signals (e.g., ...). Figure 2 The input signals VIN+ and VIN- are respectively. Accordingly, in some embodiments, Figure 1 The decision signal SD can be a set of differential signals (e.g., ...). Figure 2 The decision signals SD+ and SD- are mentioned. In this example, the offset cancellation circuit 140 is configured to correspond to the input pair circuit 212, which can draw / or inject current from nodes O1 and O2 according to multiple correction voltages VCP and VCN when the clock signal CLKC is at a preset level, thereby eliminating the offset of the comparator circuit 110.
[0025] The above-described configuration of the offset cancellation circuit 140 is merely an example, and this invention is not limited thereto. Various related circuits that can eliminate the offset of the comparator circuit 110 based on multiple correction voltages VCP and VCN are all within the scope of this invention.
[0026] Figure 3A Drawing based on some embodiments of this case Figure 1A schematic diagram of a hybrid offset voltage generation circuit 130 is shown. The hybrid offset voltage generation circuit 130 may include a digital-to-analog converter circuit 332 and multiple switched capacitor circuits 334 and 336. The digital-to-analog converter circuit 332 can generate multiple reference voltages VREF1 to VREFN, and select reference voltage VR1 and reference voltage VR2 from the multiple reference voltages VREF1 to VREFN according to a first signal SC1 among multiple control signals SC. In some embodiments, the digital-to-analog converter circuit 332 may include a voltage divider circuit 332A and a selection circuit 332B. The voltage divider circuit 332A can divide the system voltage to generate multiple reference voltages VREF1 to VREFN. In some embodiments, the voltage divider circuit 332A may be implemented by multiple series-coupled resistors. The selection circuit 332B can select reference voltage VR1 and reference voltage VR2 from the multiple reference voltages VREF1 to VREFN according to the first signal SC1. In some embodiments, the selection circuit 332B may be a multiplexer implemented by several switches. For example, when the offset calculation circuit 120 determines that the average value of the decision signal SD is too large, the offset calculation circuit 120 can output multiple corresponding control signals SC to select the reference voltage VR1 with a higher level and the reference voltage VR2 with a lower level. Alternatively, when the offset calculation circuit 120 determines that the average value of the decision signal SD is low, the offset calculation circuit 120 can output multiple corresponding control signals SC to select the reference voltage VR1 with a lower level and the reference voltage VR2 with a higher level. In some embodiments, the difference between the multiple correction voltages VCP and VCN will converge to a stable voltage value and fluctuate around this stable voltage value. In some embodiments, the offset calculation circuit 120 can output multiple control signals SC according to the upper limit of the fluctuation range of the difference to select the corresponding reference voltage VR1 and reference voltage VR2. In some embodiments, the upper limit of the fluctuation range of the difference can be determined according to system requirements.
[0027] Multiple switching capacitor circuits 334 and 336 can perform charge transfer operations based on reference voltages VR1 and VR2 and a second signal SC2 and a third signal SC3 among multiple control signals SC to generate multiple correction voltages VCP and VCN. In this example, switching capacitor circuit 334 can perform charge transfer operations based on reference voltage VR1, ground voltage GND, and the second signal SC2 to generate correction voltage VCP. Correspondingly, switching capacitor circuit 336 can perform charge transfer operations based on reference voltage VR2, ground voltage GND, and the third signal SC3 to generate correction voltage VCN.
[0028] Figure 3B Drawing based on some embodiments of this case Figure 1 A schematic diagram of the hybrid offset voltage generation circuit 130 in the diagram. Unlike... Figure 3AIn this example, the switching capacitor circuit 334 can perform a charge transfer operation based on reference voltage VR1, reference voltage VR2, and the second signal SC2 to generate a correction voltage VCP. The switching capacitor circuit 336 can perform a charge transfer operation based on reference voltage VR1, reference voltage VR2, and the third signal SC3 to generate a correction voltage VCN. In other words, in different embodiments, the switching capacitor circuit 334 can perform a charge transfer operation based on one of ground voltage GND and reference voltage VR2, reference voltage VR1, and the second signal SC2 to generate a correction voltage VCP. Similarly, in different embodiments, the switching capacitor circuit 336 can perform a charge transfer operation based on one of ground voltage GND and reference voltage VR1, reference voltage VR2, and the third signal SC3 to generate a correction voltage VCN.
[0029] Figure 4A Drawing based on some embodiments of this case Figure 3A A schematic diagram of the switching capacitor circuit 334 is shown. In this example, the switching capacitor circuit 334 may include an inverter 410, multiple capacitors C1 to C6, and multiple switches SW1 to SW6. The inverter 410 is powered via a reference voltage VR1 and ground voltage GND, and generates an inverted signal SI according to a second signal SC2. The multiple switches SW1 to SW6 are turned on according to multiple clock signals PH1 and PH2 respectively, thereby transmitting the inverted signal SI to the multiple capacitors C1 to C6, so that the multiple capacitors C1 to C6 can perform charge transfer operations in response to the inverted signal SI to generate a correction voltage VCP.
[0030] In detail, the first terminal of switch SW1 is coupled to inverter 410 to receive the inverted signal SI, the second terminal of switch SW1 is coupled to capacitor C1, and the control terminal of switch SW1 receives clock signal PH1. The first terminal of switch SW2 is coupled to capacitor C1 and the second terminal of switch SW1, the second terminal of switch SW2 is coupled to capacitor C2, and the control terminal of switch SW2 receives clock signal PH2. And so on, the corresponding arrangement of the remaining switches SW3 to SW6 and capacitors C3 to C6 should be understood. With the above arrangement, when switch SW1 is turned on, capacitor C1 can be charged or discharged via the inverted signal SI. Then, when switch SW2 is turned on, capacitor C2 can transfer a portion of the charge from capacitor C1. Similarly, when the subsequent switches SW3 to SW6 are turned on, the capacitors C3 to C6 can correspondingly perform the above charge transfer operation, thereby generating a correction voltage VCP (corresponding to the amount of charge stored in capacitor C6) via capacitor C6.
[0031] It should be understood that a higher reference voltage VR1 results in more charge transferred through capacitors C1 to C6, leading to a higher change in the correction voltage VCP. Conversely, a lower reference voltage VR1 results in less charge transferred through capacitors C1 to C6, leading to a lower change in the correction voltage VCP. On the other hand, a larger number of switches and capacitors in the switching capacitor circuit 334 results in more charge transfer operations, reducing the amount of charge stored in the last capacitor and thus lowering the change in the correction voltage VCP. In other words, by using the above configuration, the digital-to-analog converter circuit 332 can generate reference voltages VR1 with different levels, and by setting the number of switches and capacitors in the switching capacitor circuit 334, the change in the correction voltage VCP can be reduced, resulting in a smaller difference fluctuation range. This allows for more precise elimination of offsets in the comparator circuit 110.
[0032] In some related technologies, only switched capacitor circuits or only resistive analog-to-digital converters are used to generate the correction voltage. As a result, a larger number of capacitors and switches (or resistors) are required to reduce the amount of change in the correction voltage in order to more accurately eliminate the offset. In contrast to these related technologies, in some embodiments of this invention, the hybrid offset voltage generation circuit 130 uses a voltage divider mechanism to generate a lower reference voltage, allowing the switched capacitor circuit 334 (and / or switched capacitor circuit 336) to reduce the amount of change in the correction voltage VCP without using an excessive number of capacitors and switches. This allows for more accurate offset elimination while saving circuit area.
[0033] Figure 4B Drawing based on some embodiments of this case Figure 3B A schematic diagram of the switching capacitor circuit 334 in the diagram. Different from... Figure 4A In this example, inverter 410 is powered via reference voltages VR1 and VR2, and generates an inverted signal SI based on the second signal SC2. In some embodiments, reference voltage VR1 is higher than reference voltage VR2. With the above configuration, both the upper limit (i.e., reference voltage VR1) and lower limit (i.e., reference voltage VR2) of the inverted signal SI can be further adjusted. This allows for the generation of a finer correction voltage VCP.
[0034] In some embodiments, the switching capacitor circuit 336 is configured in the same way as the switching capacitor circuit 334. For example, according to Figure 4A In this configuration, the inverter of the switching capacitor circuit 336 (corresponding to inverter 410) is powered via a reference voltage VR2 and ground voltage GND, and generates an inverted signal SI based on the third signal SC3. Alternatively, based on... Figure 4BIn this configuration, the inverter of the switching capacitor circuit 336 (corresponding to inverter 410) is powered by reference voltages VR1 and VR2, and generates an inverted signal SI based on the third signal SC3. Other configuration methods can be found in [reference needed]. Figure 4A and Figure 4B As explained above, it will not be repeated here.
[0035] Figure 5A Drawing based on some embodiments of this case Figure 3A A schematic diagram of the switching capacitor circuit 334 is shown. In this example, the switching capacitor circuit 334 may include multiple switches 501-505, multiple capacitors C01-C04, multiple switches 511-515, multiple capacitors C11-C14, an inverter 510, and multiple switches 521 and 522. Multiple switches 501-505 are connected in series between node N1 and output node NO, and are selectively turned on according to the second signal SC2 and the enable signal EN. Node N1 is used to receive the reference voltage VR1, and output node NO is used to output the correction voltage VCP. Multiple switches 521 and 522 are turned on according to the enable signal EN to selectively transmit the second signal SC2 and the third signal SC3 to the corresponding switches among multiple switches 501-505 and multiple switches 511-515. In detail, the first terminal of switch 501 is coupled to node N1, the second terminal of switch 501 is coupled to the first terminal of switch 502 and capacitor C01, and the control terminal of switch 501 receives the second signal SC2 via switch 521. The second terminal of switch 502 is coupled to the first terminal of switch 503 and capacitor C02, and the control terminal of switch 502 receives the enable signal EN via inverter 510 (i.e., switch 502 receives the inverted enable signal EN). Similarly, the corresponding configurations of the remaining switches 503-505 and capacitors C03-C04 can be understood.
[0036] Similarly, multiple switches 511-515 are connected in series between output node NO and node N2, and are selectively turned on according to the third signal SC3 and the enable signal EN, wherein node N2 is used to receive the ground voltage GND. Specifically, the first terminal of switch 511 is coupled to output node NO, the second terminal of switch 501 is coupled to the first terminal of switch 512 and capacitor C11, and the control terminal of switch 511 receives the third signal SC3 via switch 522. The second terminal of switch 512 is coupled to the first terminal of switch 513 and capacitor C12, and the control terminal of switch 512 receives the enable signal EN via inverter 510. And so on, the corresponding arrangement of the remaining switches 513-514 and capacitors C13-C14 should be understood.
[0037] With the above configuration, multiple capacitors C01-C04 and C11-C14 can perform charge transfer operations via multiple switches 501-505 and 511-515 to output a correction voltage VCP via output node NO. For example, multiple capacitors C01-C04 can be charged and / or discharged in response to the switching of multiple switches 501-505, and multiple capacitors C11-C14 can be charged and / or discharged in response to the switching of multiple switches 511-515. After the charge in multiple capacitors C01-C04 and C11-C14 is redistributed via multiple switches 501-505 and 511-515, the switching capacitor circuit 334 can output the corresponding correction voltage VCP via output node NO. Similarly, if the reference voltage VR1 is higher, the amount of charge that can be transferred will increase, resulting in a higher change in the correction voltage VCP. Alternatively, if the reference voltage VR1 is lower, the amount of charge that can be transferred will decrease, resulting in a lower change in the correction voltage VCP. The more switches and capacitors used in the switching capacitor circuit 334, the more times the charge transfer operation is performed, thereby reducing the change in the correction voltage VCP. In other words, the above configuration can effectively reduce the change in the correction voltage VCP, so as to more accurately eliminate the offset in the comparator circuit 110.
[0038] Figure 5B Drawing based on some embodiments of this case Figure 3B A schematic diagram of the switching capacitor circuit 334 in the diagram. Different from... Figure 5A In this example, node N2 receives the reference voltage VR2, not the ground voltage GND. In other words, in different embodiments, node N2 can be used to receive either the ground voltage GND or the reference voltage VR2. This configuration allows for a finer correction voltage VCP.
[0039] In some embodiments, the switching capacitor circuit 336 is configured in the same way as the switching capacitor circuit 334. For example, according to Figure 5A In this configuration, node N1 of the switching capacitor circuit 336 receives the reference voltage VR1. Alternatively, according to... Figure 5B In this configuration, nodes N1 and N2 in the switching capacitor circuit 336 receive reference voltages VR1 and VR2, respectively. Other configuration methods can be found in [reference needed]. Figure 5A and Figure 5B As explained above, it will not be repeated here.
[0040] Figure 6A A schematic diagram of an analog-to-digital converter 600 is shown according to some embodiments of this invention. In some embodiments, the analog-to-digital converter 600 may be a time-interleaved analog-to-digital converter or an analog-to-digital converter using multiple comparators.
[0041] The analog-to-digital converter 600 may include multiple comparator circuits 610[1] to 610[M], an offset calculation circuit 620, a hybrid offset voltage generation circuit 630, and multiple offset cancellation circuits 640[1] to 640[M]. The multiple comparator circuits 610[1] to 610[M] can perform analog-to-digital conversion according to the input signal VIN to generate multiple decision signals SD[1] to SD[M]. The offset calculation circuit 620 can perform the aforementioned statistical operation according to the multiple decision signals SD[1] to SD[M] to determine the offset in the multiple comparator circuits 610[1] to 610[M], thereby generating multiple sets of control signals SC[1] to SC[M].
[0042] In some embodiments, multiple decision signals SD[1] to SD[M] can be combined into a digital code with N bits, where both the value M and the value N are positive integers greater than 1. Under this condition, the offset calculation circuit 620 can also perform statistical operations based on the digital code to determine the generation of multiple sets of control signals SC[1] to SC[M]. The hybrid offset voltage generation circuit 630 can select a first reference voltage and a second reference voltage (e.g., the aforementioned reference voltages VR1 and VR2) from multiple reference voltages based on the multiple sets of control signals SC[1] to SC[M], and perform charge transfer operations using the first reference voltage and the second reference voltage to generate multiple sets of correction voltages VC[1] to VC[M]. Multiple offset cancellation circuits 640[1] to 640[M] can cancel the offset in multiple comparator circuits 610[1] to 610[M] based on the multiple sets of correction voltages VC[1] to VC[M]. For example, offset cancellation circuit 640[1] can correct comparator circuit 610[1] according to a corresponding set of correction voltages VC[1], and offset cancellation circuit 640[2] can correct comparator circuit 610[2] according to a corresponding set of correction voltages VC[2]. Similarly, the correspondence between the aforementioned multiple circuits and multiple correction voltages should be understood. In this example, each of the multiple sets of correction voltages VC[1] to VC[M] may include the aforementioned multiple correction voltages VCP and VCN. The relevant configuration of the aforementioned multiple circuits can be referred to the descriptions of the aforementioned embodiments, and will not be repeated here.
[0043] Figure 6B Drawing based on some embodiments of this case Figure 6A A schematic diagram of the hybrid offset voltage generation circuit 630 is shown. The hybrid offset voltage generation circuit 630 includes a digital-to-analog converter circuit 632 and multiple sets of switching capacitor circuits 634[1]~634[M]. The configuration of the digital-to-analog converter circuit 632 can be found in the following diagram. Figure 3A The digital-to-analog converter 332 is configured in this way. Similarly, each of the multiple sets of switched capacitor circuits 634[1] to 634[M] may containFigure 3A , Figure 3B , Figure 4A or Figure 4B Multiple switching capacitor circuits 334 and 336. Detailed configuration methods can be found in the aforementioned embodiments, and will not be repeated here. Multiple switching capacitor circuits 634[1]~634[M] can perform charge transfer operations according to the corresponding signals in multiple control signals SC[1]~SC[M] (e.g., including the aforementioned second signal SC2 and third signal SC3) to generate multiple correction voltages VC[1]~VC[M]. Specifically, in some embodiments, the first control signal SC[1] may include three signals, for example, it may be... Figure 3A or Figure 3B The first signal SC1, the second signal SC2, and the third signal SC3, wherein the first signal SC1 can be provided to the digital-to-analog converter circuit 632. On the other hand, each of the remaining control signals SC[2] to SC[M] can contain two signals, for example, they can be... Figure 3A or Figure 3B The second signal SC2 and the third signal SC3 can be used to control one corresponding group of circuits in the multiple switching capacitor circuits 634[2] to 634[M]. The above-mentioned setting method of multiple control signals SC[1] to SC[M] is only an example, and this case is not limited to it.
[0044] from Figure 6B It can be seen that the number of multiple sets of switching capacitor circuits 634[1] to 634[M] (for example, the value M) is the same as the number of multiple comparator circuits 610[1] to 610[M], and all multiple sets of switching capacitor circuits 634[1] to 634[M] receive reference voltages VR1 and VR2 generated by the same digital-to-analog converter circuit 632. In other words, multiple sets of switching capacitor circuits 634[1] to 634[M] can share the digital-to-analog converter circuit 632. In this way, the number of circuit components can be further reduced, thereby reducing the circuit area and cost required for the analog-to-digital converter 600.
[0045] Figure 7 A flowchart illustrating the operation of an offset elimination method 700 according to some embodiments of this invention is provided. In operation S710, a decision signal is generated via a comparator circuit based on an input signal. In operation S720, an offset of the comparator circuit is calculated based on the decision signal to generate multiple control signals. In operation S730, a first reference voltage and a second reference voltage are selected from multiple reference voltages based on the multiple control signals, and a charge transfer operation is performed using the first reference voltage and the second reference voltage to generate multiple correction voltages. In operation S740, the offset of the comparator circuit is eliminated based on the multiple correction voltages.
[0046] The descriptions of the above operations can be found in the foregoing embodiments, and therefore will not be repeated here. The multiple operations of the offset elimination method 700 are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operational mode and scope of the embodiments of this invention, the various operations of the offset elimination method 700 may be appropriately added, replaced, omitted, or performed in a different order. Alternatively, one or more operations of the offset elimination method 700 may be performed simultaneously or partially simultaneously.
[0047] In summary, the comparators, analog-to-digital converters, and offset cancellation methods provided in some embodiments of this invention can utilize various configurations to generate fine correction voltages, thereby more accurately eliminating comparator offsets. Furthermore, the aforementioned various configurations can reduce the number of circuits required, thereby reducing circuit area and cost.
[0048] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection of this case shall be determined by the scope of the patent application in this specification.
[0049] [Symbol Explanation]
[0050] 100: Comparator
[0051] 110,610[1]~610[M]: Comparator circuit
[0052] 120,620: Offset Calculation Circuit
[0053] 130,630: Hybrid Offset Voltage Generation Circuit
[0054] 140,640[1]~640[M]: Offset cancellation circuit
[0055] 212: Input pair circuit
[0056] 214: Latch Circuit
[0057] 332, 632: Digital-to-Analog Converter Circuits
[0058] 332A: Voltage divider circuit
[0059] 332B: Selection Circuit
[0060] 334, 336: Switching capacitor circuits
[0061] 410, 510: Inverters
[0062] 501~505, 511~515, 521~522: Switches
[0063] 600: Analog-to-Digital Converter
[0064] 634[1]~634[M]: A set of switching capacitor circuits
[0065] 700: Offset Removal Method
[0066] C1~C6, C01~C04, C11~C14: Capacitors
[0067] CLKC, PH1, PH2: Clock signals
[0068] EN: Enable signal
[0069] GND: Ground voltage
[0070] N1, N2, O1, O2: Nodes
[0071] NO: Output Node
[0072] S710, S720, S730, S740: Operation
[0073] SC: Control Signal
[0074] SC1: First signal
[0075] SC2: Second signal
[0076] SC3: Third signal
[0077] SC[1]~SC[M]: A set of control signals
[0078] SD,SD[1]~SD[M]: Decision signals
[0079] SI: Inverted signal
[0080] SW1~SW6: Switches
[0081] VC[1]~VC[M]: A set of correction voltages
[0082] VCN, VCP: Correction voltage
[0083] VIN, VIN+, VIN-: Input signals
[0084] VR1, VR2, VREF1~VREFN: Reference voltages.
Claims
1. A comparator comprising: A comparator circuit for generating a decision signal based on an input signal; An offset calculation circuit is used to calculate an offset of the comparator circuit based on the decision signal in order to generate multiple control signals; A hybrid offset voltage generation circuit is used to select a first reference voltage and a second reference voltage from a plurality of reference voltages according to a plurality of control signals, so as to perform a charge transfer operation using the first reference voltage and the second reference voltage to generate a plurality of correction voltages. as well as An offset cancellation circuit is used to eliminate the offset based on the plurality of correction voltages.
2. The comparator of claim 1, wherein the hybrid offset voltage generation circuit comprises: A digital-to-analog converter circuit is used to generate the plurality of reference voltages and select a first reference voltage and a second reference voltage from the plurality of reference voltages based on a first signal among the plurality of control signals; and Multiple switching capacitor circuits are used to perform the charge transfer operation based on the first reference voltage, the second reference voltage, and a second signal and a third signal among the multiple control signals, so as to generate the multiple correction voltages.
3. The comparator of claim 2, wherein the plurality of switching capacitor circuits comprises: A first switching capacitor circuit is configured to perform the charge transfer operation based on one of a ground voltage and a second reference voltage, the first reference voltage and the second signal, to generate a first correction voltage among the plurality of correction voltages; and A second switching capacitor circuit is used to perform the charge transfer operation based on one of the ground voltage and the first reference voltage, the second reference voltage and the third signal to generate a second correction voltage among the plurality of correction voltages.
4. The comparator of claim 3, wherein the first switching capacitor circuit comprises: An inverter is used to be powered via one of the ground voltage and the second reference voltage and the first reference voltage, and to generate an inverted signal according to the second signal; Multiple capacitors; as well as Multiple switches are configured to be turned on according to multiple clock signals to transmit the inverted signal to the multiple capacitors, wherein the multiple capacitors are configured to perform the charge transfer operation in response to the inverted signal to generate the first correction voltage.
5. The comparator of claim 3, wherein the first switching capacitor circuit comprises: Multiple first switches are connected in series between a first node and an output node and are used to selectively turn on according to the second signal and a reference voltage signal, wherein the first node is used to receive the first reference voltage; Multiple first capacitors are coupled to the multiple first switches; Multiple second switches are connected in series between the output node and a second node, and are used to selectively turn on according to the third signal and the enable signal, wherein the second node receives one of the ground voltage and the second reference voltage; Multiple second capacitors are coupled to the multiple second switches, wherein the multiple first capacitors and the multiple second capacitors are used to perform the charge transfer operation via the multiple first switches and the multiple second switches to output the first correction voltage via the output node; as well as Multiple third switches are configured to be turned on according to the enable signal, so as to transmit the second signal and the third signal to a corresponding switch among the multiple first switches and a corresponding switch among the multiple second switches respectively.
6. The comparator of claim 2, wherein the digital-to-analog converter circuit comprises: A voltage divider circuit is used to generate the plurality of reference voltages; and A selection circuit is used to select the first reference voltage and the second reference voltage from the plurality of reference voltages based on the first signal.
7. An analog-to-digital converter, comprising: Multiple comparator circuits are used to generate multiple decision signals based on an input signal; An offset calculation circuit is used to calculate an offset of the multiple comparator circuits based on the multiple decision signals in order to generate multiple sets of control signals; A hybrid offset voltage generation circuit is used to select a first reference voltage and a second reference voltage from multiple reference voltages according to the multiple sets of control signals, so as to perform a charge transfer operation using the first reference voltage and the second reference voltage to generate multiple sets of correction voltages. as well as Multiple offset cancellation circuits are used to eliminate the offset based on the multiple sets of correction voltages.
8. The analog-to-digital converter of claim 7, wherein the hybrid offset voltage generation circuit comprises: A digital-to-analog converter circuit is used to generate the plurality of reference voltages and select a first reference voltage and a second reference voltage from the plurality of reference voltages based on a first signal from the plurality of control signals; and Multiple sets of switching capacitor circuits are used to perform the charge transfer operation according to the first reference voltage, the second reference voltage and multiple corresponding signals in the multiple sets of control signals, so as to generate multiple correction voltages.
9. The analog-to-digital converter according to claim 8, wherein the number of multiple sets of switching capacitor circuits is the same as the number of multiple comparator circuits.
10. A method for offset elimination, comprising: A decision signal is generated based on an input signal via a comparator circuit; The offset of the comparator circuit is calculated based on the decision signal to generate multiple control signals; Based on the multiple control signals, a first reference voltage and a second reference voltage are selected from multiple reference voltages, and a charge transfer operation is performed using the first reference voltage and the second reference voltage to generate multiple correction voltages; as well as The offset of the comparator circuit is eliminated by the multiple correction voltages.