TFET device and forming method thereof
By introducing a tunneling dielectric layer into the TFET device and replacing the BTB-tunneling mechanism with the FN-tunneling mechanism, the bipolar effect problem of the TFET device is solved, resulting in a steeper subthreshold slope and lower leakage current, thus improving device performance.
Patent Information
- Application Number
- CN202410591727.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-13
- Publication Date
- 2025-11-18
AI Technical Summary
Existing TFET devices suffer from bipolar effects, which lead to increased leakage current and a less steep subthreshold slope, thus limiting the improvement of device performance.
The FN-tunneling mechanism is adopted instead of the traditional BTB-tunneling mechanism. By introducing a tunneling dielectric layer for isolation between the source and the channel, the FN tunneling mechanism is used to control the on and off of the device.
The bipolar effect of TFET devices is weakened, the subthreshold slope is steeper, and the leakage current is reduced, thereby improving device performance.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a TFET device and a forming method thereof. BACKGROUND
[0002] The critical dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) is continuously reduced according to the Moore's Law, and along with the continuous improvement of device performance, its static power consumption is also increasing, which has become a bottleneck restricting the further development of integrated circuit industry. For the traditional MOSFET, the key factor hindering the reduction of power consumption is that the subthreshold slope of the device is limited by the thermodynamic limit (the minimum is 60 mV / dec at room temperature). Therefore, in order to achieve a subthreshold slope lower than 60 mV / dec, a low-power semiconductor device based on other physical mechanisms must be used. The special current injection mechanism of tunneling field effect transistor (TFET) makes it the most promising device for new integrated circuit design.
[0003] Tunneling field effect transistor (TFET) is a P-I-N structure, and above the I region is a gate dielectric and a gate electrode. It controls the turn-on and turn-off of the device by modulating the energy band of the I region through the change of the gate voltage. The current working principle of the TFET is band-to-band tunneling (BTB-tunneling). When a positive voltage is applied to the gate, the channel energy band is lowered until the conduction band bottom of the channel is lower than the valence band top of the source region, and the band-to-band tunneling of the TFET device begins. However, the current band-to-band tunneling mechanism will produce a bipolar effect, causing an increase in leakage current and a decrease in device performance.
[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to weaken the bipolar effect of the TFET device, make the subthreshold slope of the TFET device more steep, reduce the leakage current, and thus improve the device performance. SUMMARY
[0005] The present application provides a TFET device and a forming method thereof. The FN-tunneling (Fowler-Nordheim tunneling, FN-tunneling occurs when an electron tunnels through the conduction band of the oxide layer and then drifts through the oxide layer) mechanism is used to replace the traditional BTB-tunneling mechanism by isolating the source and the channel through a tunneling dielectric layer, which can weaken the bipolar effect of the TFET device, make the subthreshold slope of the TFET device more steep, reduce the leakage current, and thus improve the device performance.
[0006] One aspect of the present application provides a method for forming a TFET device, comprising: providing a semiconductor substrate, a gate structure is formed on a surface of the semiconductor substrate, the gate structure comprises opposite first side and second side; forming a source trench in the semiconductor substrate on the first side of the gate structure; forming a tunneling dielectric layer on the sidewall of the gate structure on the first side and the sidewall of the source trench close to the gate structure; forming a source in the source trench.
[0007] In some embodiments of the present application, the method for forming a source trench in the semiconductor substrate on the first side of the gate structure comprises: forming a mask material layer on the surface of the semiconductor substrate and the sidewall and top surface of the gate structure; etching to remove part of the mask material layer to expose the semiconductor substrate on the first side of the gate structure, the sidewall on the first side of the gate structure and part of the top surface of the gate structure; etching the semiconductor substrate on the first side of the gate structure to form the source trench.
[0008] In some embodiments of the present application, after forming a source in the source trench, further comprising: removing the mask material layer on the top surface of the gate structure and the surface of the semiconductor substrate on the second side of the gate structure, retaining the mask material layer on the sidewall on the second side of the gate structure as a sidewall of the gate structure; forming a drain in the semiconductor substrate on the second side.
[0009] In some embodiments of the present application, the thickness of the tunneling dielectric layer is less than the thickness of the sidewall.
[0010] In some embodiments of the present application, the gate structure comprises a gate dielectric layer, a gate layer and a hard mask layer in sequence on the surface of the semiconductor substrate.
[0011] In some embodiments of the present application, the ratio of the thickness of the tunneling dielectric layer to the thickness of the gate dielectric layer is 1:(2-3).
[0012] In some embodiments of the present application, the thickness of the tunneling dielectric layer is 0.5-1.5 nm.
[0013] In some embodiments of the present application, when forming a source trench in the semiconductor substrate on the first side of the gate structure, a drain trench is also formed in the semiconductor substrate on the second side of the gate structure.
[0014] In some embodiments of the present application, when forming a tunneling dielectric layer on the sidewall of the gate structure on the first side and the sidewall of the source trench close to the gate structure, a tunneling dielectric layer is also formed on the sidewall of the gate structure on the second side and the sidewall of the drain trench close to the gate structure.
[0015] Another aspect of the present application also provides a TFET device, comprising: a semiconductor substrate, a gate structure is formed on a surface of the semiconductor substrate, the gate structure comprising opposite first and second sides; a source in the semiconductor substrate on the first side of the gate structure; a tunneling dielectric layer on the sidewall of the first side of the gate structure and the sidewall of the source close to the gate structure; a source.
[0016] In some embodiments of the present application, the TFET device further comprises: a spacer on the sidewall of the second side of the gate structure and a drain in the semiconductor substrate on the second side of the gate structure.
[0017] In some embodiments of the present application, the tunneling dielectric layer is also on the sidewall of the second side of the gate structure and the sidewall of the drain trench close to the gate structure.
[0018] In some embodiments of the present application, the thickness of the tunneling dielectric layer is less than the thickness of the spacer.
[0019] In some embodiments of the present application, the gate structure comprises a gate dielectric layer, a gate layer and a hard mask layer on the surface of the semiconductor substrate in turn.
[0020] In some embodiments of the present application, the ratio of the thickness of the tunneling dielectric layer to the thickness of the gate dielectric layer is 1:(2-3).
[0021] In some embodiments of the present application, the thickness of the tunneling dielectric layer is 0.5-1.5 nm.
[0022] The present application provides a TFET device and a method for forming the same. The FN-tunneling mechanism is used to replace the conventional BTB-tunneling mechanism by separating the source and the channel through a tunneling dielectric layer, which can weaken the bipolar effect of the TFET device, make the subthreshold slope of the TFET device more steep, reduce the leakage current, and thus improve the performance of the device. BRIEF DESCRIPTION OF DRAWINGS
[0023] The following drawings describe the exemplary embodiments disclosed in the present application in detail. The same reference signs in the several views of the drawings represent similar structures. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other ways of embodiments can also achieve the same intention of the invention in the present application. It should be understood that the drawings are not drawn to scale.
[0024] Wherein:
[0025] Figures 1 to 8Structure diagrams of steps in a method of forming a TFET device according to some embodiments of the present application.
[0026] Figures 9 to 14 Structure diagrams of steps in a method of forming a TFET device according to some embodiments of the present application. DETAILED DESCRIPTION
[0027] The following description provides specific applications and requirements of the present application, which is to enable a person skilled in the art to manufacture and use the contents of the present application. Various local modifications of the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but is consistent with the widest scope of the claims.
[0028] The technical solutions of the present application will be described in detail below in combination with embodiments and drawings.
[0029] Figures 1 to 8 Structure diagrams of steps in a method of forming a TFET device according to some embodiments of the present application. The method of forming a TFET device according to some embodiments of the present application will be described in detail below in combination with drawings.
[0030] Reference Figure 1 As shown, a semiconductor substrate 100 is provided, which has a gate structure 110 formed on the surface thereof, the gate structure 110 including opposite first and second sides 101 and 102.
[0031] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or indium gallium phosphide, etc.; or (iv) a combination of the above.
[0032] In some embodiments of the present application, the semiconductor substrate 100 also has structures formed therein, such as well regions, which are possessed by conventional TFET devices, which are omitted here for the purpose of brevity.
[0033] In some embodiments of the present application, the first and second sides 101 and 102 refer to the areas on the left and right sides of the gate structure 110 in the drawings.
[0034] In some embodiments of the present application, the gate structure 110 includes a gate dielectric layer 111, a gate layer 112 and a hard mask layer 113 sequentially on the surface of the semiconductor substrate 100. The gate structure 110 is a conventional structure in a TFET device, and the detailed structure and forming method thereof will not be described herein.
[0035] Referring to Figures 2 to 4 As shown, a source trench 120 is formed in the semiconductor substrate 100 at the first side 101 of the gate structure 110.
[0036] Referring to Figure 2 As shown, a mask material layer 130a is formed on the surface of the semiconductor substrate 100 and the sidewall and top surface of the gate structure 110.
[0037] In some embodiments of the present application, the material of the mask material layer 130a includes silicon nitride. The thickness of the mask material layer 130a is 3-10 nm.
[0038] Referring to Figure 3 As shown, a part of the mask material layer 130a is etched to expose the semiconductor substrate 100 at the first side 101 of the gate structure 110, the sidewall at the first side 101 of the gate structure 110 and a part of the top surface of the gate structure 110.
[0039] Referring to Figure 4 As shown, the semiconductor substrate 100 at the first side 101 of the gate structure 110 is etched to form the source trench 120.
[0040] Referring to Figure 5 As shown, a tunneling dielectric layer 140 is formed on the sidewall at the first side 101 of the gate structure 110 and the sidewall of the source trench 120 close to the gate structure 110.
[0041] In some embodiments of the present application, the ratio of the thickness of the tunneling dielectric layer 140 to the thickness of the gate dielectric layer 111 is 1:(2-3). The thickness of the tunneling dielectric layer 140 is smaller than the thickness of the gate dielectric layer 111, so that the FN-tunneling probability can be increased and the tunneling current can be increased.
[0042] In some embodiments of the present application, the thickness of the tunneling dielectric layer 140 is 0.5-1.5 nm.
[0043] In some embodiments of the present application, the material of the tunneling dielectric layer 140 includes high dielectric constant material or low dielectric constant material, etc. For example, hafnium oxide, silicon oxide, etc.
[0044] In some embodiments of the present application, the method for forming the tunneling dielectric layer 140 includes atomic layer deposition process and etching process.
[0045] Reference is made to Figure 6 As shown, a source 150 is formed in the source trench 120. The source 150 can have P-type doping or N-type doping.
[0046] In some embodiments of the present application, the method of forming the source 150 includes an epitaxial growth process.
[0047] In the technical solution of the present application, the source 150 and the channel (i.e., the region of the semiconductor substrate 100 under the gate structure 110) are isolated by the tunneling medium layer 140, which replaces the conventional BTB-tunneling mechanism with the FN-tunneling mechanism, weakens the bipolar effect of the TFET device, makes the subthreshold slope of the TFET device more steep, reduces the leakage current, and thus improves the performance of the device.
[0048] Reference is made to Figure 7 As shown, the mask material layer 130a on the top surface of the gate structure 110 and the semiconductor substrate 100 on the second side 102 of the gate structure 110 is removed, and the mask material layer 130a on the sidewall of the second side 102 of the gate structure 110 is retained as the sidewall 130 of the gate structure 110.
[0049] In some embodiments of the present application, the thickness of the tunneling medium layer 140 is less than the thickness of the sidewall 130. Therefore, the distance between the subsequently formed drain and the gate structure 110 is greater than the distance between the source 120 and the gate structure 110, which can further reduce the off-state current and the bipolar effect.
[0050] Reference is made to Figure 8 As shown, a drain 160 is formed in the semiconductor substrate 100 on the second side 102. The drain 160 can have P-type doping or N-type doping. The doping type of the drain 160 and the source 150 is opposite.
[0051] In some embodiments of the present application, the method of forming the drain 160 includes an ion implantation process.
[0052] Some embodiments of the present application provide a method of forming a TFET device, which isolates the source and the channel by a tunneling medium layer, replaces the conventional BTB-tunneling mechanism with the FN-tunneling mechanism, weakens the bipolar effect of the TFET device, makes the subthreshold slope of the TFET device more steep, reduces the leakage current, and thus improves the performance of the device.
[0053] Some embodiments of the present application also provide a TFET device, which is described with reference to Figure 8As shown, it comprises: a semiconductor substrate 100, a gate structure 110 is formed on the surface of the semiconductor substrate 100, the gate structure 110 comprises opposite first side 101 and second side 102; a source 150 is located in the semiconductor substrate 100 on the first side 101 of the gate structure 110; a tunneling dielectric layer 140 is located on the sidewall of the first side 101 of the gate structure 110 and the sidewall of the source 150 close to the gate structure 110.
[0054] In some embodiments of the present application, the material of the semiconductor substrate 100 comprises (i) elemental semiconductor, such as silicon or germanium, etc.; (ii) compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide, etc.; or (iv) combination of the above.
[0055] In some embodiments of the present application, the semiconductor substrate 100 is also formed with structures such as well region that conventional TFET devices have, which are omitted here for the purpose of brevity.
[0056] In some embodiments of the present application, the first side 101 and the second side 102 refer to the areas on the left and right sides of the gate structure 110 in the drawing.
[0057] In some embodiments of the present application, the gate structure 110 comprises a gate dielectric layer 111, a gate layer 112 and a hard mask layer 113 which are sequentially located on the surface of the semiconductor substrate 100. The gate structure 110 is a conventional structure in TFET devices, and its detailed structure and forming method are not described here.
[0058] In some embodiments of the present application, the ratio of the thickness of the tunneling dielectric layer 140 to the thickness of the gate dielectric layer 111 is 1:(2-3). The thickness of the tunneling dielectric layer 140 is less than the thickness of the gate dielectric layer 111, so that the probability of FN-tunneling occurrence can be increased and the tunneling current can be increased.
[0059] In some embodiments of the present application, the thickness of the tunneling dielectric layer 140 is 0.5 nanometers to 1.5 nanometers.
[0060] In some embodiments of the present application, the material of the tunneling dielectric layer 140 comprises high dielectric constant material or low dielectric constant material, etc. For example, hafnium oxide, silicon oxide, etc.
[0061] In some embodiments of the present application, the source 150 can have P-type doping or N-type doping.
[0062] In the technical solution of the present application, the source 150 and the channel (i.e. the region of the semiconductor substrate 100 under the gate structure 110) are separated by the tunneling medium layer 140, which replaces the traditional BTB-tunneling mechanism with the FN-tunneling mechanism, weakens the bipolar effect of the TFET device, makes the subthreshold slope of the TFET device more steep, reduces the leakage current, and thus improves the performance of the device.
[0063] In some embodiments of the present application, the TFET device further comprises a side wall 130 on the sidewall of the second side 102 of the gate structure 110 and a drain 160 in the semiconductor substrate 100 on the second side 102 of the gate structure 110.
[0064] In some embodiments of the present application, the material of the side wall 130 comprises silicon nitride. The thickness of the side wall 130 is 3-10 nanometers.
[0065] In some embodiments of the present application, the thickness of the tunneling medium layer 140 is less than the thickness of the side wall 130. Therefore, the distance between the subsequently formed drain 160 and the gate structure 110 is greater than the distance between the source 120 and the gate structure 110, which can further reduce the off-state current and the bipolar effect.
[0066] In some embodiments of the present application, the drain 160 can have P-type doping or N-type doping. The doping type of the drain 160 and the source 150 is opposite.
[0067] Some embodiments of the present application provide a TFET device and a forming method thereof. The source and the channel are separated by a tunneling medium layer, which replaces the traditional BTB-tunneling mechanism with the FN-tunneling mechanism, weakens the bipolar effect of the TFET device, makes the subthreshold slope of the TFET device more steep, reduces the leakage current, and thus improves the performance of the device.
[0068] Figures 9 to 14 The structure schematic diagrams of the steps in the forming method of the TFET device of some other embodiments of the present application are shown. The forming method of the TFET device of some other embodiments of the present application is described in detail below with reference to the accompanying drawings.
[0069] Reference Figure 9 As shown, a semiconductor substrate 200 is provided, and a gate structure 210 is formed on the surface of the semiconductor substrate 200. The gate structure 210 comprises opposite first and second sides 201 and 202.
[0070] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or indium gallium phosphide, etc.; or (iv) combinations thereof.
[0071] In some embodiments of the present application, the semiconductor substrate 200 is also formed with structures that are common to TFET devices, such as well regions, which are omitted here for brevity.
[0072] In some embodiments of the present application, the first side 201 and the second side 202 refer to the areas on the left and right sides of the gate structure 210 in the drawing.
[0073] In some embodiments of the present application, the gate structure 210 includes, in order, a gate dielectric layer 211, a gate layer 212, and a hard mask layer 213 on the surface of the semiconductor substrate 200. The gate structure 210 is a common structure in TFET devices, and its detailed structure and formation method are not described here.
[0074] Referring to Figure 10 As shown, a source trench 220 is formed in the semiconductor substrate 200 on the first side 201 of the gate structure 210, and at the same time, a drain trench 290 is also formed in the semiconductor substrate 200 on the second side 202 of the gate structure 210.
[0075] Referring to Figure 11 As shown, a tunneling dielectric layer 240 is formed on the sidewall of the first side 201 of the gate structure 210 and on the sidewall of the source trench 220 close to the gate structure 210, and at the same time, the tunneling dielectric layer 240 is also formed on the sidewall of the second side 202 of the gate structure 210 and on the sidewall of the drain trench 290 close to the gate structure 210.
[0076] In some embodiments of the present application, the ratio of the thickness of the tunneling dielectric layer 240 to the thickness of the gate dielectric layer 211 is 1:(2-3). The thickness of the tunneling dielectric layer 240 is less than the thickness of the gate dielectric layer 211, so that the probability of FN-tunneling occurrence can be increased, and the tunneling current can be increased.
[0077] In some embodiments of the present application, the thickness of the tunneling dielectric layer 240 is 0.5 nanometers to 1.5 nanometers.
[0078] In some embodiments of the present application, the material of the tunneling dielectric layer 240 includes high-dielectric-constant materials or low-dielectric-constant materials, etc. For example, hafnium oxide, silicon oxide, etc.
[0079] In some embodiments of the present application, the method of forming the tunneling dielectric layer 240 includes a deposition process and an etching process.
[0080] Referring to Figure 12 As shown, an epitaxial layer 280 is formed in the source trench 220 and the drain trench 290 by epitaxial growth.
[0081] Referring to Figure 13 As shown, a sidewall of the tunneling dielectric layer 240 of the second side 202 of the gate structure 210 forms a side wall 230.
[0082] In some embodiments of the present application, the material of the side wall 230 includes silicon nitride or the like.
[0083] In some embodiments of the present application, the side wall 230 can not be formed.
[0084] Referring to Figure 14 As shown, a source 250 and a drain 260 are formed in the epitaxial layer 280 of the first side 201 and the second side 202, respectively. The source 250 can have a P-type doping or an N-type doping. The drain 260 can have a P-type doping or an N-type doping. The doping type of the drain 260 and the source 250 are opposite.
[0085] In some embodiments of the present application, the method of forming the source 250 and the drain 260 includes an ion implantation process.
[0086] In the technical solution of the present application, the source 250, the drain 260 and the channel (i.e. the region of the semiconductor substrate 200 under the gate structure 210) are isolated by the tunneling dielectric layer 240, the FN-tunneling mechanism is used to replace the conventional BTB-tunneling mechanism, the bipolar effect of the TFET device is weakened, the subthreshold slope of the TFET device is steeper, the leakage current is reduced, and thus the device performance is improved.
[0087] In some embodiments of the present application, the distance between the drain 260 and the gate structure 210 is greater than the distance between the source 220 and the gate structure 210, which can further reduce the off-state current and the bipolar effect.
[0088] Some embodiments of the present application provide a method of forming a TFET device, the source and the channel are isolated by the tunneling dielectric layer, the FN-tunneling mechanism is used to replace the conventional BTB-tunneling mechanism, the bipolar effect of the TFET device is weakened, the subthreshold slope of the TFET device is steeper, the leakage current is reduced, and thus the device performance is improved.
[0089] Some embodiments of the present application also provide a TFET device, referring to Figure 14 as shown, comprising: a semiconductor substrate 200, a gate structure 210 is formed on the surface of the semiconductor substrate 200, the gate structure 210 includes opposite first side 201 and second side 202; epitaxial layer 280 is respectively located in the semiconductor substrate 200 of the first side 201 and the second side 202; source 250 and drain 260 are respectively located in the epitaxial layer 280 of the first side 201 and the second side 202; tunneling dielectric layer 240 is located on the side wall of the first side 201 of the gate structure 210 and the side wall of the gate structure 210 close to the source 250, the side wall of the second side 202 of the gate structure 210 and the side wall of the gate structure 210 close to the drain 260; side wall 230 is located on the side wall of the second side 202 of the gate structure 210.
[0090] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) elemental semiconductor, such as silicon or germanium, etc.; (ii) compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide, etc.; or (iv) a combination of the above.
[0091] In some embodiments of the present application, the semiconductor substrate 200 is also formed with structures such as well regions that conventional TFET devices have, which are omitted here for the purpose of brevity.
[0092] In some embodiments of the present application, the first side 201 and the second side 202 refer to the areas on the left and right sides of the gate structure 210 in the drawings.
[0093] In some embodiments of the present application, the gate structure 210 includes gate dielectric layer 211, gate layer 212 and hard mask layer 213 which are sequentially located on the surface of the semiconductor substrate 200. The gate structure 210 is a conventional structure in TFET devices, and its detailed structure and forming method are not described here.
[0094] In some embodiments of the present application, the ratio of the thickness of the tunneling dielectric layer 240 to the thickness of the gate dielectric layer 211 is 1:(2-3). The thickness of the tunneling dielectric layer 240 is less than the thickness of the gate dielectric layer 211, so that the FN-tunneling occurrence probability can be increased and the tunneling current can be increased.
[0095] In some embodiments of the present application, the thickness of the tunneling dielectric layer 240 is 0.5 nanometers to 1.5 nanometers.
[0096] In some embodiments of the present application, the material of the tunneling dielectric layer 240 includes high dielectric constant material or low dielectric constant material, etc. For example, hafnium oxide, silicon oxide, etc.
[0097] In some embodiments of the present application, the material of the epitaxial layer 280 is the same as the semiconductor substrate 200.
[0098] In some embodiments of the present application, the material of the sidewall 230 includes silicon nitride.
[0099] In some embodiments of the present application, the source 250 can have P-type doping or N-type doping. The drain 260 can have P-type doping or N-type doping. The doping type of the drain 260 and the source 250 are opposite.
[0100] In the technical solution of the present application, the source 250, the drain 260 and the channel (i.e. the region of the semiconductor substrate 200 under the gate structure 210) are isolated by the tunneling dielectric layer 240, which realizes the replacement of the conventional BTB-tunneling mechanism with the FN-tunneling mechanism, can weaken the bipolar effect of the TFET device, makes the subthreshold slope of the TFET device more steep, and reduces the leakage current, thereby improving the device performance.
[0101] In some embodiments of the present application, the distance between the drain 260 and the gate structure 210 is greater than the distance between the source 220 and the gate structure 210, which can further reduce the off-state current and the bipolar effect.
[0102] Some other embodiments of the present application provide a TFET device and a forming method thereof, which isolates the source and the channel by the tunneling dielectric layer, replaces the conventional BTB-tunneling mechanism with the FN-tunneling mechanism, can weaken the bipolar effect of the TFET device, makes the subthreshold slope of the TFET device more steep, and reduces the leakage current, thereby improving the device performance.
[0103] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only in an exemplary manner and can not be limiting. Although it is not explicitly stated here, those skilled in the art can understand that the present application intends to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.
[0104] It will be understood that the term "and / or," as used herein in the specification and in the claims, can connote any or all possible combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, the term "directly" means that there are no intervening elements.
[0105] Similarly, it will be understood that, when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, the term "directly on" means that there are no intervening elements present. It will also be understood that, when an element or layer is referred to as being "formed on, " "formed over, " or "formed onto" another element or layer, it can be directly formed, or intervening elements can also be present. In addition, it will be understood that the term "includes," "including," "comprises," or "comprising, " as used herein, specifies the presence of stated features, integers, steps, operations, elements, components, or a combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
[0106] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section in some cases without departing from the teachings of the present application. The same reference number or symbol can be used throughout the specification to represent the same element, component, region, layer or section.
[0107] Further, the description herein makes reference to exemplary embodiments and illustrations that are described in the context of idealized illustrative cross-sectional and / or plan views and / or perspective views. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the precise shapes and / or illustrations shown herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a TFET device, characterized in that, include: A semiconductor substrate is provided, wherein a gate structure is formed on the surface of the semiconductor substrate, the gate structure including a first side and a second side opposite to each other; A source trench is formed in the semiconductor substrate on the first side of the gate structure; A tunneling dielectric layer is formed on the sidewall of the first side of the gate structure and on the sidewall of the source trench near the gate structure; A source electrode is formed in the source trench.
2. The method for forming a TFET device as described in claim 1, characterized in that, A method for forming a source trench in a semiconductor substrate on the first side of the gate structure includes: A masking material layer is formed on the surface of the semiconductor substrate and on the sidewalls and top surface of the gate structure; Etching removes part of the mask material layer, exposing the semiconductor substrate on the first side of the gate structure, the sidewall on the first side of the gate structure, and part of the top surface of the gate structure; The source trench is formed by etching the semiconductor substrate on the first side of the gate structure.
3. The method for forming a TFET device as described in claim 2, characterized in that, After the source electrode is formed in the source trench, the method further includes: Remove the mask material layer from the top surface of the gate structure and the surface of the semiconductor substrate on the second side of the gate structure, and retain the mask material layer of the sidewall on the second side of the gate structure as the sidewall of the gate structure; A drain is formed in the semiconductor substrate on the second side.
4. The method for forming a TFET device as described in claim 3, characterized in that, The thickness of the tunneling medium layer is less than the thickness of the sidewall.
5. The method for forming a TFET device as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer, a gate layer, and a hard mask layer, which are sequentially located on the surface of the semiconductor substrate.
6. The method for forming a TFET device as described in claim 5, characterized in that, The ratio of the thickness of the tunneling dielectric layer to the thickness of the gate dielectric layer is 1:(2-3).
7. The method for forming a TFET device as described in claim 1, characterized in that, The thickness of the tunneling medium layer is 0.5 nanometers to 1.5 nanometers.
8. The method for forming a TFET device as described in claim 1, characterized in that, When forming a source trench in the semiconductor substrate on the first side of the gate structure, a drain trench is also formed in the semiconductor substrate on the second side of the gate structure.
9. The method for forming a TFET device as described in claim 8, characterized in that, While forming a tunneling dielectric layer on the sidewall of the first side of the gate structure and the source trench near the sidewall of the gate structure, a tunneling dielectric layer is also formed on the sidewall of the second side of the gate structure and the drain trench near the sidewall of the gate structure.
10. A TFET device, characterized in that, include: A semiconductor substrate, wherein a gate structure is formed on the surface of the semiconductor substrate, the gate structure including a first side and a second side opposite to each other; The source is located in the semiconductor substrate on the first side of the gate structure; The tunneling dielectric layer is located on the sidewall of the first side of the gate structure and on the sidewall of the source near the gate structure.
11. The TFET device as claimed in claim 10, characterized in that, Also includes: The sidewall located on the second side wall of the gate structure and the drain in the semiconductor substrate located on the second side of the gate structure.
12. The TFET device as claimed in claim 11, characterized in that, The tunneling dielectric layer is also located on the sidewall of the second side of the gate structure and on the sidewall of the drain near the gate structure.
13. The TFET device as claimed in claim 11, characterized in that, The thickness of the tunneling medium layer is less than the thickness of the sidewall.
14. The TFET device as claimed in claim 10, characterized in that, The gate structure includes a gate dielectric layer, a gate layer, and a hard mask layer, which are sequentially located on the surface of the semiconductor substrate.
15. The TFET device as claimed in claim 14, characterized in that, The ratio of the thickness of the tunneling dielectric layer to the thickness of the gate dielectric layer is 1:(2-3).
16. The TFET device as claimed in claim 10, characterized in that, The thickness of the tunneling medium layer is 0.5 nanometers to 1.5 nanometers.