Double-sided three-dimensional stacked transistor standard cell layout generation method

Abstract

The invention discloses a double-sided three-dimensional stacked transistor standard cell layout generation method, which comprises the following steps of: applying a multi-row relative position constraint and a separation grid constraint to a transistor through a multi-row layout design and field region merging insertion, and applying a merging structure lower limit constraint to double-sided wire nets of N-type and P-type field effect transistors; the layout of the double-sided transistors is obtained through two times of solving, so that each double-sided wire net can complete wiring by combining the wire nets; in a wiring stage in the double-sided standard unit, a commodity flow conservation constraint and a design rule constraint are constructed, local iteration type wiring optimization is performed according to the obtained transistor layout and input / output pin front and back placement configuration and an initial solution, whether metal exists on edges connected with different nodes or not is obtained, and double-sided wiring is completed; and generating a double-sided three-dimensional stacked transistor standard cell layout. According to the invention, the area of the transistor standard cell can be optimized, and the flexible design space exploration capability is provided.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit design automation, and relates to a digital integrated circuit standard cell layout generation technology, in particular to a standard cell layout generation method for double-sided three-dimensional stacked transistors. BACKGROUND

[0002] With the transistor size shrinking gradually approaching the physical limit, three-dimensional stacked transistor technology has become a key development direction to improve the chip integration density and performance. Currently, two promising technical solutions are single-sided three-dimensional stacked transistors and double-sided three-dimensional stacked transistors. Among them, the single-sided three-dimensional stacked transistor technology is the current mainstream solution, which significantly reduces the standard cell height by vertically stacking N-type field effect transistors (N-FET) and P-type field effect transistors (P-FET); when combined with the backside power supply technology (BSPDN), the standard cell height can be further reduced to 3T (i.e. 3 track height).

[0003] In contrast, the double-sided three-dimensional stacked transistor technology can achieve a smaller standard cell height (up to 2.5T) due to its unique back-to-back transistor stacking architecture and double-sided interconnection structure. However, this structural characteristic also introduces new design challenges. Existing standard cell layout automatic generation techniques for three-dimensional stacked transistors are based on single-sided stacking structure and are difficult to effectively handle the complex double-sided connection relationship specific to double-sided three-dimensional stacked transistors. In order to fully utilize the double-sided connection capability of double-sided three-dimensional stacked transistors, the number of pin assignment scheme variants for standard cell design based on double-sided three-dimensional stacked transistors increases exponentially. Obviously, under the increasingly complex design rule constraints, it is difficult to efficiently explore the vast transistor design space and ensure optimal performance relying on existing manual design methods. SUMMARY

[0004] In order to overcome the deficiencies of the prior art, the present application provides a double-sided three-dimensional stacked transistor standard cell layout generation method, which can efficiently handle the unique structural characteristics of double-sided three-dimensional stacked transistors, automatically generate double-sided three-dimensional stacked transistor standard cell layout, optimize transistor standard cell area under the premise of meeting design rules, and provide flexible design space exploration capability.

[0005] The technical solution of the present application is:

[0006] A double-sided three-dimensional stacked transistor standard cell layout generation method includes the processes of merging the perception of double-sided transistor layout and wiring within the double-sided standard cell.

[0007] The process of the merged-aware dual-side transistor placement is based on the Satisfiability Modulo Theories (SMT) method, adopts the multi-row relative positioning constraint (RPC) considering diffusion sharing, and simultaneously performs the placement of the dual-side N-FET and P-FET; in addition, a merged-aware dual-side transistor placement method is designed to ensure that the dual-side wire net can pass through the source-drain merge, gate merge and field-drain merge (FDM) structure to complete the wiring.

[0008] Specifically, the method comprises the following steps:

[0009] A. Merged-aware dual-side transistor placement stage

[0010] The merged-aware dual-side transistor placement method is designed to simultaneously complete the transistor placement of the dual-side N-type field effect transistor (N-FET) and P-type field effect transistor (P-FET), insert the multi-row placement design and FDM field region merge, and ensure that each dual-side wire net can pass through the merged structure to complete the wiring.

[0011] The input of the process is a transistor netlist and a row number configuration, and the output is a dual-side transistor layout. The merged-aware dual-side transistor placement process comprises:

[0012] 11) First, analyze the transistor netlist, identify all dual-side wire nets and the transistors connected thereto;

[0013] 12) Apply the multi-row relative positioning constraint considering diffusion sharing and the separate gate constraint to all transistors, and apply the lower limit constraint of the merged structure to all dual-side wire nets;

[0014] 13) Solve the merged-aware dual-side transistor placement, and the optimization target of the merged-aware dual-side transistor placement is to minimize the standard cell area and the total dual-side bus length;

[0015] The method of SMT modeling is used to solve the merged perception layout problem twice to determine whether the FDM field region is merged and the specific positions of all transistors.

[0016] The method of SMT modeling is used to solve the layout twice, and in the first time of solving the layout, it is determined whether the FDM is inserted, if yes, the position of the FDM is determined in the second time of solving the layout, otherwise, the first time of solving the layout result is directly output.

[0017] 14) According to the transistors' abscissa and row number obtained, the transistor layout is determined.

[0018] B. Double-sided standard cell internal wiring stage;

[0019] The application models the double-sided standard cell internal wiring as a Boolean satisfiability problem (SAT problem), and completes the double-sided wiring according to the transistor layout obtained from A and the front or back placement configuration of the I / O pin (input / output pin).

[0020] 21) First, the pin positions of each wire net are determined according to the transistor layout,

[0021] 22) Then, the commodity flow conservation constraint and the design rule constraint (SAT constraint) are constructed according to the multi-commodity flow theory and the design rule; the standard cell wiring framework based on the multi-commodity flow theory is expanded to double-sided wiring, that is, the commodity flow conservation constraint is modified according to the double-sided interconnection relationship, which is used to correctly handle the connectivity of the merged structure in the double-sided wiring.

[0022] 23) Based on the SAT constraint, an initial solution of the double-sided standard cell internal wiring is obtained; based on the obtained initial solution, local iterative wiring optimization based on SMT is carried out, and the target of the iterative optimization is to minimize the weighted total metal length; each time, one wire net is selected for local iterative optimization, and the iteration is terminated after a set number of iterations, and the wiring solution and the SAT constraint are updated.

[0023] 24) According to the local iterative wiring optimization solution, it is determined whether there is metal on the edge connecting different nodes to determine the transistor wiring.

[0024] Through the above steps, the double-sided three-dimensional stacked transistor standard cell layout can be generated.

[0025] Compared with the prior art, the application has the beneficial effects that:

[0026] The existing technology for generating a three-dimensional stacked transistor standard cell layout is all for single-sided three-dimensional stacked transistors, and the double-sided three-dimensional stacked transistor standard cell layout generation method provided by the application is developed for the double-sided interconnection characteristics of double-sided three-dimensional stacked transistors, and a standard cell layout generation method is developed, which can efficiently generate a standard cell layout of double-sided three-dimensional stacked transistors. The double-sided transistor layout method with merging awareness provided by the application guarantees the generation of the merging structure by applying constraints and introducing a field area merging insertion step, and improves the routability of the double-sided line net; the double-sided standard cell internal routing method provided by the application can effectively process the connectivity of the merging structure in double-sided routing, and quickly generates a routing solution through an iterative optimization mode, so as to optimize the transistor standard cell area and improve the flexibility and efficiency of the double-sided three-dimensional stacked transistor standard cell layout generation. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a comparison schematic diagram of single-sided three-dimensional stacked transistors and double-sided three-dimensional stacked transistors.

[0028] Figure 2 It is a flow block diagram of the double-sided three-dimensional stacked transistor standard cell layout generation method provided by the application.

[0029] Figure 3 It is a schematic diagram of the double-sided transistor layout with merging awareness. The figure is the layout result of AOI22, the upper half is the front N-FET, and the lower half is the back P-FET. S is the corresponding part of the first layout solution, S ′ It is the corresponding part of the layout solution after inserting FDM.

[0030] Figure 4 It is a schematic diagram of the line net pin of the double-sided standard cell routing. The commodity flow conservation constraints of the single-sided pin (such as A2, B1) and the double-sided pin (such as A1, B2) are different. DETAILED DESCRIPTION

[0031] The application will be further described below by combining with the drawings and through embodiments.

[0032] The application provides a double-sided three-dimensional stacked transistor standard cell layout generation method. The method includes a double-sided transistor layout process with merging awareness and a double-sided standard cell internal routing process. Specifically, the following steps are included:

[0033] A. Double-sided transistor layout process with merging awareness;

[0034] The double-sided transistor layout process with merging awareness is as follows Figure 2As shown, firstly, the whole transistor netlist is traversed to find all nets connected to both N-FET and P-FET, i.e. double-sided nets. To ensure that all double-sided nets have corresponding merge structures to realize double-sided routing, an at-least-one merge constraint (ALOMerge) is imposed. In the present application, without loss of generality, N-FET and P-FET are placed on the front side and the back side respectively, and the layout areas of the two overlap at the lower left, and N-FET and P-FET with the same horizontal coordinate and row number are stacked vertically back to back, which can generate a merge structure in the case of source-drain or gate connected to the same net. Then the SMT method is used to solve the layout twice. In the first layout, it is determined whether to insert FDM, and if so, the position of FDM is determined in the second layout; otherwise, the first layout result is directly output. The two layout results are shown in Figure 3 The present application imposes specific constraints on the characteristics of double-sided three-dimensional stacked transistors in the layout, and introduces a field region merge insertion step to ensure the generation of merge structures and improve the routability of double-sided nets. Considering that the height of double-sided three-dimensional stacked transistor standard cells is low, and the standard cells with complex structures are usually implemented using multi-row structures. Therefore, the present application imposes a multi-row relative position constraint on all transistors:

[0035]

[0036] where ∧ is a conjunction operator; t, s represent transistors (N-FET or P-FET), T is a set of transistors (all N-FET or P-FET); r t represents the row number of t; RPC(t, s) represents the relative position constraint between t and s considering source-drain sharing, which is used in transistor layout to ensure that they do not overlap or can share source-drain.

[0037] For all double-sided nets, an at-least-one merge constraint is imposed:

[0038]

[0039] where merge(n) is:

[0040]

[0041] where ∨ is a disjunction operator; t represents N-FET, N represents a set of all N-FET, s represents P-FET, and P represents a set of all P-FET; x t represents the horizontal coordinate of transistor t, r t represents the row number of transistor t; i∈{L,R,G} represents the pin of the transistor, L, R, and G represent the left pin, the right pin, and the gate pin, respectively, such as n L(t) = n represents that the left pin of transistor t is connected to wire net n. The left and right pins of a transistor are source or drain, which is determined by the flip of the transistor.

[0042] Considering the manufacturing process of double-sided stacked transistors, compared with single-sided stacked transistors, the gate signals of the transistors in the vertical stack do not need to be the same, so the present application proposes the following separate gate constraints to relax this restriction:

[0043]

[0044] where CPP represents the adjacent gate pitch, and k is an adjustable parameter, which can be taken as k = 0 for a C 2 The standard cell of the MOS structure needs to take k = 1, and the selector (MUX) or more complex standard cell needs to take k = 2 or a larger value.

[0045] The optimization objective of the merged perception double-sided transistor layout is solved using the SMT method, which is represented as:

[0046]

[0047] where CW represents the width of the standard cell, which is taken as the width of the widest row on the front and back of each row (0 ≤ i ≤ R represents the 0th to Rth row); the present application simultaneously considers the optimization of the wire length on the front and back in the layout stage, and HPWL front (n) represents the half-perimeter wire length (HPWL) of wire net n on the front; HPWL back (n) represents the half-perimeter wire length of wire net n on the back; respectively represent the width of the ith row on the front and back, and the calculation method thereof is different in the two layouts in the present application. In the first layout, the lower limit constraint of the merged structure (ALO Merge constraint) is not directly required to be met, and the case of violating the lower limit constraint of the merged structure is added as a penalty to the calculation of , which is specifically represented as:

[0048]

[0049] where w t represents the width of transistor t, w FDM represents the width of the FDM structure; I i,n ∈ {0, 1}, indicates whether the FDM corresponding to wire net n needs to be inserted into the ith row, which is greedily selected according to the pin distribution of wire net n. After the first layout, merge (n) = 0 corresponds to wire net n, which means that the FDM structure needs to be inserted, and in the second layout, the FDM is inserted in the form of a pair of N-FET and P-FET, which is specifically:

[0050] N←N∪{t},n D (t)=n,n S,G (t) = null, (7)

[0051] P←P∪{s},n D (s)=n,n S,G (s) = null, (8)

[0052] x t =x s ∧r t =r s (9)

[0053] n S,G (t) = null means that the gate and source pins of transistor t are not connected to any wire, that is, it can share the source and drain of any transistor; (9) ensure that transistors t and s are stacked back to back vertically. In the second layout, the width of the i-th row on the front and back sides is calculated normally:

[0054]

[0055] Finally, x is obtained from SMT. t ,r t ,t∈N∪P, determine the transistor layout.

[0056] B. Wiring within double-sided standard units

[0057] Double-sided standard cell routing is a typical detailed routing problem based on multi-commodity flow theory. Commodity flow conservation constraints and design rule constraints (SAT constraints) are constructed based on multi-commodity flow theory and design rules. The main improvement in this invention lies in extending the standard cell routing framework based on multi-commodity flow theory to double-sided routing. Specifically, the commodity flow conservation constraints are modified according to the double-sided interconnection relationship to correctly handle the connectivity of merged structures in double-sided routing. Figure 4 Let me introduce it.

[0058] For single-sided pins (such as) Figure 4 In the context of A2 and B1), the corresponding supernode v s And for the m-th commodity flow of the corresponding network n, we have:

[0059]

[0060] Where a(v) s ) represents v s Adjacent node set Represents connection v s The edge between u and u is occupied by the j-th commodity flow of net i. i is the net index, which can take the value n; j is the commodity flow index of the corresponding net, which can take the value m;

[0061] For double-sided pins (e.g. Figure 4 A1, B2), the commodity flow conservation constraint is changed to:

[0062]

[0063] where ∧ is the conjunction operator and ∨ is the disjunction operator.

[0064] In the traditional standard cell routing framework based on multi-commodity flow theory, since only single-sided routing scenarios are supported, the super node corresponding to a transistor pin is usually set to support only one-way flow (only flow in or out, e.g. Figure 4 A2, B1). In the double-sided routing scenario, double-sided pins (e.g. Figure 4 A1, B2, usually merge structures) have inter-surface connectivity, and their corresponding super nodes need to be modeled as bidirectional flow structures to accurately capture the connectivity of the merge structure.

[0065] In addition, the present application supports placing I / O pins on the specified front and back surfaces by adjusting the connection relationship of the super node corresponding to the I / O pin.

[0066] The SAT problem is constructed using the commodity flow conservation constraint and the design rule constraint supporting double-sided routing, and the solution obtained by solving the SAT is used as the initial solution of the iterative optimization. The constraints constructed according to the multi-commodity flow theory and the design rules are retained, as shown in Figure 1 N , G N , S N represent the source, gate, and drain of the N-FET (the same for the P-FET). In the single-sided three-dimensional stack schematic diagram, a via in the red dashed box connects the gates of the vertically stacked N-FET and P-FET. Such a structure is also applicable to the source and drain; in addition, as shown in the figure, D P is directly connected to the bottommost metal layer (M0) through a via. In the double-sided three-dimensional stack schematic diagram, the red dashed box is a merge structure specific to double-sided three-dimensional transistor technology, which can connect the source, drain, or gate across the front and back surfaces; in addition, both the front and back surfaces have metal layers, which can be interconnected.

[0067] Start the local iterative routing optimization based on SMT, and the optimization objective is to minimize the weighted total metal length, which is represented as:

[0068]

[0069] where V represents the set of all nodes in the routing region; m v,u ∈{0,1} indicates that the edge e u,v ​Whether there is metal on the upper surface, w v,u Corresponding weights.

[0070] The local iterative routing optimization selects one line network n each time, only optimizes the commodity flow occupation variable related to the line network n, and keeps the variables corresponding to the remaining line networks as the results of the last iteration, and the specific expression is shown as (14).

[0071]

[0072] Finally, the value of whether there is metal (m v,u ) on the edge connecting different nodes determined by the local iterative routing optimization solution determines the transistor routing, and a double-sided three-dimensional stacked transistor standard cell layout is automatically generated.

[0073] It should be noted that the purpose of the disclosed embodiments is to help further understand the present application, but those skilled in the art can understand that various replacements and modifications are possible without departing from the scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed content of the embodiments, and the scope of the present application claimed is defined by the scope of the claims.

Claims

1. A method for generating a standard cell layout of a double-sided three-dimensional stacked transistor, characterized in that, Includes the following steps: 1) Design a merge sensing double-sided transistor layout method. Through multi-row layout design and FDM field region merging insertion, multi-row relative position constraints and gate separation constraints are applied to the transistors. Merging structure lower limit constraints are applied to the double-sided nets of N-type field-effect transistors and P-type field-effect transistors. The double-sided transistor layout is obtained through two solutions, so that each double-sided net can complete the routing through the merging structure. 2) During the double-sided standard cell routing stage, based on the obtained transistor layout and the front and back placement configuration of the input / output pins, complete the double-sided routing; including: The wiring within the double-sided standard cell is modeled as a Boolean satisfiability problem. Commodity flow conservation constraints and design rule constraints are constructed, and the initial solution for the wiring within the double-sided standard cell is obtained. Based on the initial solution, local iterative wiring optimization is performed to determine whether there is metal on the edges connecting different nodes, thereby determining the transistor wiring. By following the steps above, a standard cell layout of double-sided three-dimensional stacked transistors can be generated.

2. The method for generating standard cell layouts of double-sided three-dimensional stacked transistors as described in claim 1, characterized in that, In step 1), the multi-row relative position constraint is represented as: Where ∧ is the conjunction giant operator; t and s represent N-FET or P-FET transistors; T is the set of transistors; r t The row number represents t; RPC(t,s) represents the relative positional constraint between t and s considering source-drain sharing. The lower bound constraint of the merged structure is expressed as: Where merge(n) is: Where ∨ is the disjunction giant operator; t represents N-FET, N is the set of all N-FETs, s represents P-FET; P represents the set of all P-FETs; x t The x-coordinate of transistor t, r t The row number of transistor t; i∈{L,R,G}, where i represents the transistor pin, and L, R,G represent the left and right pins and the gate pin, respectively.

3. The method for generating standard cell layouts of double-sided three-dimensional stacked transistors as described in claim 2, characterized in that, In step 1), the gate separation constraint is expressed as: Where CPP represents the spacing between adjacent gates, and k is an adjustable parameter.

4. The method for generating standard cell layouts of double-sided three-dimensional stacked transistors as described in claim 3, characterized in that, In step 1), the SMT method is specifically used to optimize the layout of the double-sided transistors in the merging sensing; the optimization objective is expressed as: Where CW represents the standard cell width, which is the width of the widest row on both the front and back sides; 0≤i≤R represents rows 0 to R; HPWL front (n) represents the half-circle length of net n on the front side, HPWL back (n) represents the half-circle length of net n on the back side; These represent the widths of the i-th row on the front and back sides, respectively.

5. The method for generating standard cell layouts of double-sided three-dimensional stacked transistors as described in claim 4, characterized in that, Step 1) Obtain the double-sided transistor layout by solving twice using the satisfiability modulus modeling method. In the first layout, violations of the lower bound constraint of the merged structure are added as a penalty to the width. The calculation is expressed as: Among them, w t w represents the width of transistor t. FDM Represents the width of the FDM structure; I i,n ∈{0,1} indicates whether the FDM corresponding to net n should be inserted into the i-th row; merge(n) = 0 indicates that the corresponding net n needs to be inserted into the FDM structure.

6. The method for generating standard cell layouts of double-sided three-dimensional stacked transistors as described in claim 5, characterized in that, In the second layout, when the net n needs to insert an FDM structure, the FDM is inserted in the form of a pair of N-FETs and P-FETs, ensuring that transistors t and s are stacked back-to-back vertically; represented as: N←N∪{t},n D (t)=n,n S,G (t)=null, P←P∪{s},n D (s)=n,n S,G (s)=null, x t =x s ∧r t =r s Where, n S,G (t) = null means that the gate and source pins of transistor t are not connected to any wire.

7. The method for generating standard cell layouts of double-sided three-dimensional stacked transistors as described in claim 6, characterized in that, In the second layout, the width of the i-th row of the front and back sides is calculated using the following formula. Then, based on the obtained x t ,r t ,t∈N∪P, determine the transistor layout.

8. The method for generating standard cell layouts of double-sided three-dimensional stacked transistors as described in claim 7, characterized in that, In step 2), the commodity flow conservation constraint is expressed as: Where a(v) s ) represents v s Adjacent node set Represents connection v s The edge of u is occupied by the m-th commodity flow of the net n; Represents connection v s The edge of u is occupied by the j-th commodity flow of the net i; ∧ is the conjunction operator, and ∨ is the disjunction operator.

9. The method for generating standard cell layouts of double-sided three-dimensional stacked transistors as described in claim 8, characterized in that, Local iterative routing optimization is performed based on the initial solution, with the goal of minimizing the weighted total metal length.

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