Groove type IGBT cellular structure, IGBT device and preparation method

Abstract

The invention relates to a groove type IGBT cellular structure, an IGBT device and a preparation method, the groove type IGBT cellular structure comprises an N-drift layer and an active region, and the active region is provided with a P-body region, a plurality of grooves and an N + emitter region; the trenches comprise a plurality of gate trenches and emitter trenches which are transversely arranged, and each trench vertically passes through the P-body region and enters the N-drift layer; the table board width on the two sides of the gate trench is set as a first value; at least two adjacent emitter trenches exist, the mesa width between the two adjacent emitter trenches is set as a second numerical value, the first numerical value is greater than the mesa threshold, and the second numerical value is smaller than the mesa threshold. By designing the gate trench and the emitter trench with specific mesa width distribution, the hole outflow path is balanced, the conductivity of the channel inversion layer is kept stable, the collector induced barrier lowering effect of the device is effectively improved, and the reliability of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a trench-type IGBT cell structure, an IGBT device, and a fabrication method. Background Technology

[0002] The mainstream IGBT (Insulated Gate Bipolar Transistor) structure is currently the Trench IGBT, whose cell structure typically includes multiple functional regions such as substrate, drift layer, body region, emitter, and gate. Microtrench IGBTs represent a significant direction in current IGBT technology development because smaller cell sizes allow for higher channel current densities, improving device performance, while simultaneously reducing chip area and cost.

[0003] The continuous reduction in cell size is typically achieved by shrinking the key dimensions within the cell, such as the width of the trenches, the width of the mesa between the trenches, and the width of the holes. Currently, due to process limitations, the range of reduction for trench and hole widths is limited, thus requiring the sacrifice of more mesa width to achieve the goal of microcells.

[0004] However, the narrow mesa reduces the outflow path of hole carriers between the trenches. When the IGBT is on, this lowers the potential barrier between the body region and the emitter in the cell, triggering the collector-induced barrier lowering (CIBL) effect. The CIBL effect further impacts device reliability. Especially in the IGBT short-circuit state, such as a load short circuit, the applied bus voltage (usually a high voltage) is fully applied to the IGBT. The IGBT simultaneously bears high voltage and high current. The CIBL effect causes more electrons to cross the barrier region and enter the inversion layer of the cell structure, resulting in a larger short-circuit saturation current or unsaturated short-circuit current. This significantly reduces the device's short-circuit robustness, greatly affecting its reliability.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention discloses a trench-type IGBT cell structure, an IGBT device, and a fabrication method.

[0007] The technical solutions adopted in the embodiments of the present invention are as follows: A trench-type IGBT cell structure, comprising: N-drift layer; The active region includes a P-body region, several trenches, and an N+ emitter region; the P-body region is formed on the front side of the drift layer. The trench includes a plurality of gate trenches and emitter trenches arranged laterally, each trench vertically passing through the P-body region into the N-drift layer; the N+ emitter region is formed in the mesa on both sides of the gate trench, and the back side of the N+ emitter region is in contact with the front side of the P-body region. The mesa width on both sides of the gate trench is set to a first value; there are at least two adjacent emitter trenches, and the mesa width between two adjacent emitter trenches is set to a second value; the first value is greater than a preset mesa threshold, and the second value is less than a preset mesa threshold.

[0008] Preferably, an emitter contact hole is formed in the platform between two adjacent trenches, with the top of each emitter contact hole exposed on the front side of the active region and the bottom located in the active region and forming a hole injection region; The hole injection region includes multiple longitudinally arranged P+ injection regions with overlapping areas between adjacent P+ injection regions, forming an overall chain structure. The bottom of the hole injection region extends into the N-drift layer.

[0009] Preferably, two emitter contact holes are formed in a platform with a width of a first value, and one emitter contact hole is formed in a platform with a width of a second value.

[0010] Preferably, both the emitter trench and the gate trench are filled with polysilicon material; All polysilicon materials in the gate trenches are connected by a first polysilicon trace disposed at the top of the gate trench; all electrode materials in the emitter trenches are connected by a second polysilicon trace disposed at the top of the emitter trench.

[0011] Preferably, an N+ field cutoff layer and a P+ collector layer located outside the N+ field cutoff layer are formed on the back side of the N- drift layer.

[0012] An IGBT device includes: an emitter metal region, multiple gate metal layers, a P+ collector layer and a collector metal layer, and the trench-type IGBT cell structure, wherein the emitter metal region and each gate metal layer are disposed on the active region, the P+ collector layer is disposed on the back side of the N-drift layer, and the collector metal layer is disposed outside the P+ collector layer. In the cell structure, the electrode materials in all gate trenches are connected by a first polysilicon trace disposed at the top of the gate trench, and the first polysilicon trace is connected to the gate metal layer by a metal contact hole; the electrode materials in all emitter trenches are connected by a second polysilicon trace disposed at the top of the emitter trench, and the second polysilicon trace is connected to the emitter metal region by a metal contact hole; the active region forms a plurality of emitter contact holes, which are connected to the emitter metal region.

[0013] A method for fabricating an IGBT device, comprising the following steps: Formation of an N-drift layer; An active region is formed on the front side of the drift layer; Trench etching is performed laterally on the front side of the active region. The trench includes several gate trenches and emitter trenches. Each trench vertically passes through the active region and enters the N-drift layer. A P-body region and an N+ emitter region are formed on both sides of each gate trench, with the N+ emitter region located on the P-body region; a P-body region and an N+ emitter region are formed on the mesa between adjacent emitter trenches. The mesa width on both sides of the gate trench is set to a first value; there are at least two adjacent emitter trenches, and the mesa width between two adjacent emitter trenches is set to a second value; the first value is greater than a preset mesa threshold, and the second value is less than a preset mesa threshold.

[0014] Preferably, after completing the trench etching, the following steps are performed: An insulating material is deposited on the front side of the device, and then etched to form an insulating oxide layer on the front side of the active region. Polysilicon material is deposited on the front side of the device to form a polysilicon layer on the front side of the active region, as well as polysilicon filling the gate trench and emitter trench; polysilicon etching is performed to form the first polysilicon trace and the second polysilicon trace. An insulating material is deposited again on the front side of the device to form an insulating layer covering the first polysilicon trace and the second polysilicon trace; Through photolithography and etching processes, several metal contact holes are formed on the first polysilicon trace within the insulating layer, several metal contact holes are formed on the second polysilicon trace, and several emitter contact holes are formed in the active region between the trenches. P+ impurities are injected into the bottom of the emitter contact hole to form a hole injection region; An emitter metal region is formed on the insulating layer, and the emitter contact hole and the emitter metal region form an ohmic contact.

[0015] Preferably, two emitter contact holes are formed in a platform with a width of a first value, and one emitter contact hole is formed in a platform with a width of a second value.

[0016] Preferably, the hole injection region is formed by multiple injections, with each injection forming a P+ injection region. The P+ injection regions are arranged longitudinally, and adjacent P+ injection regions have overlapping areas. The top of the formed hole injection region is located within the active region, and the bottom extends into the N-drift layer.

[0017] The beneficial effects of the embodiments of the present invention are as follows: (i) The present invention proposes a trench-type IGBT cell structure, including a gate trench and an emitter trench with a specific mesa width distribution. By reducing the mesa width on both sides of the emitter trench and increasing the mesa width on both sides of the gate trench, the hole outflow path is balanced, the conductivity of the channel inversion layer is kept stable, and the collector-induced barrier reduction effect of the device is effectively improved.

[0018] (ii) The trench-type IGBT cell structure proposed in this invention has a vertically chain-like hole injection region designed at the bottom of the emitter contact hole. This improves the conventional single hole injection by changing it to chain injection, resulting in a deeper and more concentrated hole injection region. This can reduce the resistance of the P-body region, suppress the potential rise of the P-body region caused by hole inflow, suppress the CIBL effect, and improve the performance of the IGBT device.

[0019] (iii) The trench-type IGBT cell structure proposed in this invention provides two emitter contact holes on each side of the widened trench, providing more paths for holes to flow to the emitter, thus dispersing the number of holes flowing into the inversion layer of the channel, which can further improve the CIBL effect caused by holes penetrating into the inversion layer of the channel. Attached Figure Description

[0020] Figure 1 This is a cross-sectional schematic diagram of a conventional grooved IGBT cell structure.

[0021] Figure 2 This is a partial cross-sectional view of the grooved cell structure of Embodiment 1 of the present invention.

[0022] In the picture: 1. N- Drift layer; 2. Active region; 3. Gate trench; 4. Emitter trench; 5. P- Body region; 6. N+ Emitter region; 7. Channel inversion layer; 8. Collector metal layer; 9. Emitter contact hole; 10. Hole injection region; 11. Emitter metal region; 12. P+ Collector layer; 13. N+ Field cutoff layer; 14. Insulating layer. Detailed Implementation

[0023] The specific embodiments of the present invention will now be described with reference to the accompanying drawings.

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the device proposed by this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0025] Example 1 First, using examples, we will explain why reducing the mesa width may lead to the CIBL effect. In this invention, the mesa refers to the area between two adjacent trenches. Furthermore, in this invention, the direction pointing towards the front side of the IGBT device, i.e., the side where the emitter / gate is located, is defined as the front side of each layer or region in the cell structure / IGBT device; the direction pointing towards the back side of the IGBT device, i.e., the side where the collector is located, is defined as the back side of each layer or region in the cell structure / IGBT device. The direction parallel to the front side is called the lateral direction, and the direction perpendicular to the front side is called the longitudinal direction.

[0026] Figure 1 This is a cross-sectional schematic diagram of a conventional trench IGBT cell structure. (Example) Figure 1 As shown, the cell structure includes: an N-drift layer 1, a P-body region 5, an N+ emitter region 6, and a collector metal layer 8. When the IGBT device is forward-biased, an N-type channel inversion layer 7 is formed on the surface of the P-body region 5 outside the gate trench 3. As the cell mesa shrinks, more hole current penetrates into the channel inversion layer 7, increasing the hole concentration in the channel inversion layer 7. This leads to more electrons flowing in from the emitter, ultimately modulating the conductivity of the entire P-body region 5. Due to the modulation of the conductivity of the P-body region 5, as the collector voltage of the device increases, the potential of the P-body region 5 near the N-drift layer 1 is raised. The PN junction barrier between the P-body region 5 and the N+ emitter region 6 gradually decreases, resulting in the CIBL effect.

[0027] To improve the CIBL effect of the cell structure, this embodiment proposes a grooved IGBT cell structure with a unique mesa distribution design.

[0028] Figure 2 This is a partial cross-sectional view of the trench-type IGBT cell structure according to Embodiment 1 of the present invention. Figure 2 As shown, this embodiment provides a trench-type IGBT cell structure, including an N-drift layer 1, an active region 2 formed on the front side of the N-drift layer 1, the active region 2 including a P-body region 5 formed on the front side of the N-drift layer 1, and then a plurality of horizontally arranged trenches formed on the front side of the active region 2, each trench vertically passing through the P-body region 5 and entering the N-drift layer 1.

[0029] In this embodiment, two types of trenches are designed: gate trenches 3 and emitter trenches 4. N+ emitter regions 6 are formed only on the mesa on both sides of each gate trench 3, with the back side of the N+ emitter region 6 contacting the front side of the P-body region 5. The N+ emitter region 6 is a highly doped N-type semiconductor, providing free electrons. When the IGBT device is turned on, an electron channel is formed between two adjacent gate trenches 3; therefore, the area between two adjacent gate trenches 3 simultaneously serves as both an electron channel and a hole channel. However, no N+ emitter region 6 is provided between two adjacent emitter trenches 4, and no free electrons enter between them; therefore, they only serve as a hole channel.

[0030] like Figure 2 As shown, this embodiment further designs the mesa width between different types of trenches. The mesa width between the gate trench 3 and the adjacent emitter trench 4 is set to a first value w1, and the mesa width between two adjacent emitter trenches 4 is set to a second value w2. The first value w1 is greater than a preset mesa threshold w0, and the second value w2 is less than the preset mesa threshold w0. The mesa threshold w0 can be set to the width between conventional trenches. Exceeding the mesa threshold w0 means increasing the mesa width, and being lower than the mesa threshold w0 means reducing the mesa width. Through this design, the mesa width between the two emitter trenches 4 is reduced, while the mesa width on both sides of the gate trench 3 is increased. Therefore, when the cell structure is applied to the IGBT device, during the forward conduction process of the device, the hole outflow path between the two emitter trenches 4 is narrowed. However, since no electrons flow into this channel, electrons and holes will not recombine in the channel inversion layer 7 induced at the two emitter trenches 4, reducing the impact on the conductivity of the P-body region 5. Simultaneously, it widens the hole outflow path on both sides of the gate trench 3, allowing holes to flow smoothly to the emitter and making it less likely for them to penetrate into the inversion layer 7 induced at the gate trench 3. Therefore, it balances the mesa distribution of the entire cell structure, solves the PN junction barrier reduction effect between the P-body region 5 and the N+ emitter region 6 caused by continuously reducing the mesa width, and effectively prevents the generation of the CIBL effect.

[0031] In this embodiment, the cell structure includes a repeating unit consisting of one gate (gate trench 3) and two emitter (emitter trenches 4). It should be noted that this invention does not impose a limitation on the number of gate trenches 3 and emitter trenches 4 in the cell structure; these numbers can be adjusted according to the chip performance to which the cell structure is applied. The arrangement requires adjacent emitter trenches 4, and preferably, the emitter trenches 4 are arranged adjacent to each other. For example: There is one Gate and three Emitters, arranged as: gate / Emitter / Emitter / Emitter.

[0032] There is one Gate and four Emitters, arranged as: gate / Emitter / Emitter / Emitter / Emitter.

[0033] There are two Gates and two Emitters, arranged as: gate / gate / Emitter / Emitter.

[0034] There are two Gates and three Emitters, arranged as: gate / gate / Emitter / Emitter / Emitter.

[0035] And so on.

[0036] Specifically, in a structure with one gate and four emitters, taking a cell pitch (the width of a trench paired with a mesa) of 1.6µm as an example, the width of the emitter contact hole 9 is set to 0.2µm, and the width of the trench is set to 0.6µm. In a traditional structure, the mesa width is 0.8µm. In this invention, the hole width and trench width are consistent with the traditional structure; w1 can be set to 1.1-1.4µm, and w2 can be set to 0.4-0.6µm. An N+ emitter region 6 is provided in the active region 2 between two gate trenches 3 or between a gate trench 3 and an adjacent emitter trench 4. No N+ emitter region 6 is provided in the active region 2 between two emitter trenches 4.

[0037] Furthermore, such as Figure 2As shown, in this embodiment, emitter contact holes 9 are formed within the platform between two adjacent trenches. The top of each emitter contact hole 9 is exposed on the front side of the active region 2, and the bottom is located within the active region 2, forming a hole injection region 10. The side of the emitter contact hole 9 contacts the N+ emitter region 6, and the bottom extends beyond the bottom of the N+ emitter region 6 and is located within the P-body region 5. In this embodiment, the hole injection region 10 is set as an integral chain structure, that is, it includes multiple longitudinally arranged P+ injection regions with overlapping areas between adjacent P+ injection regions, and the bottom of the chain structure extends into the N-drift layer 1. The hole injection region 10 formed in this way is deeper and has a higher concentration. The hole injection region 10 still has a depth of 10 μm in areas with a depth greater than 0.4 μm. 19 cm -3 This reduces the resistance of the P-body region 5, thus suppressing the potential rise in the P-body region 5 caused by hole inflow and preventing the CIBL effect. Simultaneously, it prevents the voltage drop across the lateral resistance of the P-body region 5 caused by the large hole current during a short circuit from exceeding the parasitic thyristor trigger threshold, effectively preventing latch-up during short circuits and further improving the short-circuit robustness of the IGBT device.

[0038] Furthermore, such as Figure 2 As shown, in this embodiment, two emitter contact holes 9 are formed within a mesa with a width of a first value, and one emitter contact hole 9 is formed within a mesa with a width of a second value. The top of the emitter contact hole 9 is exposed on the front side of the active region 2, and the bottom is located within the active region 2, forming a hole injection region 10. Because the mesa width on both sides of the gate trench 3 is widened in this embodiment, it is possible to add emitter injection holes 9 within the mesa in terms of process technology. Conventional mesa widths cannot simultaneously accommodate two holes because the holes themselves have a certain width. By setting two emitter contact holes 9, the hole outflow path on both sides of the gate trench 3 is further widened, and as mentioned above, the holes can flow more smoothly to the emitter.

[0039] In this embodiment, both the emitter trench 4 and the gate trench 3 are filled with polysilicon material. The polysilicon material in the gate trench 3 is connected by a first polysilicon trace disposed at the top of the gate trench 3. All electrode materials in the emitter trench 4 are connected by a second polysilicon trace disposed at the top of the emitter trench 4. By designing the polysilicon trace, it is convenient to interconnect with the gate metal layer / emitter metal layer. The interconnection method is further described in Embodiment 2 and will not be repeated here.

[0040] like Figure 2As shown, in this embodiment, an N+ field-stop layer 13 and a P+ collector layer 12 of the N+ field-stop layer 13 are formed on the back side of the N-drift layer 1. By designing the N+ field-stop layer 13, the N-drift layer 1 can be made thinner at the same breakdown voltage. By precisely controlling the doping and thickness of the N+ field-stop layer 13, the hole concentration distribution within the N-drift layer 1 can be optimized, thereby better reducing conduction losses and switching losses and improving the overall performance of the device.

[0041] Example 2 This embodiment proposes an IGBT device, including: an emitter metal region 11, multiple gate metal layers, a P+ collector layer 12 and a collector metal layer 8, and at least one trench-type IGBT cell structure as described in Embodiment 1. The emitter metal region 11 and each gate metal layer are disposed on the active region 2, the P+ collector layer 12 is disposed on the back side of the N-drift layer 1, and the collector metal layer 8 is disposed outside the P+ collector layer 12.

[0042] Specifically, in this embodiment, the electrode materials in all gate trenches 3 of the cell structure are connected by a first polysilicon trace disposed at the top of the gate trench 3, and the first polysilicon trace is connected to the gate metal layer through a metal contact hole. The electrode materials in all emitter trenches 4 are connected by a second polysilicon trace disposed at the top of the emitter trench 4, and the second polysilicon trace is connected to the emitter metal region 11 through a metal contact hole. The active region 2 forms a plurality of emitter contact holes 9, which are connected to the emitter metal region 11.

[0043] The IGBT device proposed in this embodiment maintains the same external dimensions for each cell structure. It eliminates the need to alter the thickness of key areas within the cell structure, such as the drift layer and active region. By simply adjusting the distribution of mesa widths within the cell structure, the CIBL effect can be effectively improved. Therefore, there is no need to generate functional regions of varying thicknesses during fabrication, resulting in good cell structure consistency. This leads to a more uniform current distribution during IGBT operation and simplifies fabrication without increasing process complexity. The polysilicon within the trenches of each cell structure is laterally connected within the device via polysilicon traces, facilitating fabrication using standardized polysilicon deposition, photolithography, and etching processes, resulting in a more compact and sophisticated device structure.

[0044] Example 3 This embodiment proposes a method for fabricating an IGBT device, specifically for fabricating the IGBT structure shown in Embodiment 2. Combined with... Figure 2 The method includes the following steps: 1) Fabrication of N-drift layer 1: Obtain substrate materials such as wafers to form N-drift layer 1.

[0045] 2) Create active region 2: 2.1) An active region 2 is formed on the front side of the drift layer 1; 2.2) Trench etching is performed laterally on the front side of the active region 2. The trenches include several gate trenches 3 and emitter trenches 4. Each trench vertically passes through the P-body region 5 and enters the N-drift layer 1. 2.3) P-body regions 5 are generated by implanting P- impurities in the mesa on both sides of each gate trench 3, and N+ emitter regions are generated by implanting N+ impurities. N+ emitter regions 6 are located on the P-body regions 5; P-body regions 5 are generated in the mesa between adjacent emitter trenches 6. 2.4) An insulating material is deposited on the front side of the device, and then etched to form an insulating oxide layer on the front side of the active region 2; 2.5) Polysilicon material is deposited on the front side of the device to form a polysilicon layer on the front side of the active region 2, as well as polysilicon filling the gate trench 3 and emitter trench 4. The gate trench 3 and emitter trench 4 are filled with polysilicon of the same material, so it can be completed in one deposition. Polysilicon etching is performed to form the first polysilicon trace and the second polysilicon trace; 2.6) Deposit insulating material again on the front side of the device to form an insulating layer 14 covering the first polysilicon trace and the second polysilicon trace; 2.7) Through photolithography and etching processes, a number of metal contact holes are formed on the first polysilicon trace within the insulating layer 14, a number of metal contact holes are formed on the second polysilicon trace, and a number of emitter contact holes 9 are formed in the active region 2 between the trenches. 2.8) P+ impurities are injected into the bottom of the emitter contact hole 9 to form the hole injection region 10; 2.9) An emitter metal region 11 is formed on the insulating layer, and an ohmic contact is formed between the emitter contact hole 9 and the emitter metal region 11.

[0046] 3) Fabrication of the back structure: P+ collector layer 12 and collector metal layer 8 are sequentially formed on the back of N- drift layer 1, and N+ field cut-off layer 13 is further formed by implanting N+ impurities.

[0047] In step 2.2) above, when etching the trench, the mesa width on both sides of the gate trench 3 is set to a first value; there are at least two adjacent emitter trenches 4, and the mesa width between two adjacent emitter trenches 4 is set to a second value. The first value is greater than a preset mesa threshold, and the second value is less than a preset mesa threshold. Only the mesa width distribution inside the cell structure is adjusted, so the conventional trench etching process can be used without increasing the fabrication complexity.

[0048] In step 2.7) above, the formation of the pore injection region 10 is designed using a chain injection method, i.e., multiple consecutive injections, preferably three or more. Each injection has a higher energy and a deeper injection depth than the previous one. There are no special requirements for the injection dose. After injection, the injection regions formed by multiple injections connect together to form a unified chain structure. The conventional depth of the pore injection region 10 is generally about 0.4 μm below the pore. This embodiment, through this design, allows the depth of the pore injection region 10 to reach about 1.2 μm below the pore, so that the concentration of the formed pore injection region 10 is not a fixed value, but a quantity that varies with depth. This ensures that the pore injection region 10 still has a depth of 10 μm even in regions deeper than 0.4 μm. 19 cm -3 The concentration in the traditional structure's pore injection region 10, which only undergoes one pore injection, is almost identical to that in the P-body region 5 at depths greater than 0.4 μm, with a concentration of only 10. 16 cm -3 The magnitude of the increase in the hole injection region 10 can reduce the resistance of the P-body region 5, thus suppressing the potential rise of the P-body region 5 caused by hole inflow and preventing the CIBL effect. Furthermore, the chain injection method designed in this invention is easy to implement, allowing control over the concentration of the generated hole injection region 10 and ensuring it reaches a preset depth, width, and shape.

[0049] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0050] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A trench-type IGBT cell structure, characterized in that, include: N-drift layer (1); The active region (2) is provided with a P-body region (5), several trenches and an N+ emitter region (6); the P-body region (5) is formed on the front side of the drift layer (1); The trench includes a plurality of gate trenches (3) and emitter trenches (4) arranged laterally. Each trench passes vertically through the P-body region (5) and enters the N-drift layer (1). The N+ emitter region (6) is formed in the mesa on both sides of the gate trench (3). The back side of the N+ emitter region (6) is in contact with the front side of the P-body region (5). The mesa width on both sides of the gate trench (3) is set to a first value; there are at least two adjacent emitter trenches (4), and the mesa width between two adjacent emitter trenches (4) is set to a second value; the first value is greater than a preset mesa threshold, and the second value is less than a preset mesa threshold.

2. The trench-type IGBT cell structure according to claim 1, characterized in that: Emitter contact holes (9) are formed in the platform between two adjacent trenches. The top of each emitter contact hole (9) is exposed on the front of the active region (2), and the bottom is located in the active region (2) and forms a hole injection region (10). The hole injection region (10) includes multiple longitudinally arranged P+ injection regions with overlapping areas, forming an overall chain structure. The bottom of the hole injection region (10) extends into the N-drift layer (1).

3. The trench-type IGBT cell structure according to claim 2, characterized in that: Two emitter contact holes (9) are formed in a platform with a width of the first value, and one emitter contact hole (9) is formed in a platform with a width of the second value.

4. The trench-type IGBT cell structure according to claim 3, characterized in that: Both the emitter trench (4) and the gate trench (3) are filled with polycrystalline silicon material; All the polysilicon materials in the gate trenches (3) are connected by a first polysilicon trace at the top of the gate trenches (3); all the electrode materials in the emitter trenches (4) are connected by a second polysilicon trace at the top of the emitter trenches (4).

5. The trench-type IGBT cell structure according to claim 1, characterized in that: The back side of the N-drift layer (1) forms an N+ field cutoff layer (13) and a P+ collector layer (12) located outside the N+ field cutoff layer (13).

6. An IGBT device, characterized in that, include: The emitter metal region (11), multiple gate metal layers, P+ collector layer (12) and collector metal layer (8) and at least one trench IGBT cell structure as described in claim 1, wherein the emitter metal region (11) and each gate metal layer are disposed above the active region (2), the P+ collector layer (12) is disposed on the back side of the N-drift layer (1), and the collector metal layer (8) is disposed outside the P+ collector layer (12); In the cell structure, the electrode materials in all gate trenches (3) are connected by a first polysilicon trace at the top of the gate trench (3), and the first polysilicon line is connected to the gate metal layer by a metal contact hole; the electrode materials in all emitter trenches (4) are connected by a second polysilicon trace at the top of the emitter trench (4), and the second polysilicon line is connected to the emitter metal region (11) by a metal contact hole; the active region (2) forms a plurality of emitter contact holes (9), which are connected to the emitter metal region (11) through the emitter contact holes (9).

7. A method for fabricating an IGBT device, characterized in that, Including the following steps: An N-drift layer is formed (1); An active region (2) is formed on the front side of the drift layer (1); Trench etching is performed laterally on the front side of the active region (2). The trench includes a plurality of gate trenches (3) and emitter trenches (4). Each trench vertically passes through the active region (2) and enters the N-drift layer (1). A P-body region (5) and an N+ emitter region (6) are formed on both sides of each gate trench (3), wherein the N+ emitter region (6) is located on the P-body region (5); and a P-body region (5) is formed on the mesa between adjacent emitter trenches (4). The mesa width on both sides of the gate trench (3) is set to a first value; there are at least two adjacent emitter trenches (4), and the mesa width between two adjacent emitter trenches (4) is set to a second value; the first value is greater than a preset mesa threshold, and the second value is less than a preset mesa threshold.

8. The method for fabricating an IGBT device according to claim 7, characterized in that, To complete the trench etching, proceed with the following steps: An insulating material is deposited on the front side of the device and then etched to form an insulating oxide layer on the front side of the active region (2); Polysilicon material is deposited on the front side of the device to form a polysilicon layer on the front side of the active region (2), and polysilicon is filled in the gate trench (3) and emitter trench (4); polysilicon etching is performed to form the first polysilicon trace and the second polysilicon trace; An insulating material is deposited again on the front side of the device to form an insulating layer (14) covering the first polysilicon trace and the second polysilicon trace. Through photolithography and etching processes, a number of metal contact holes are formed on the first polysilicon trace in the insulating layer (14), a number of metal contact holes are formed on the second polysilicon trace, and a number of emitter contact holes (9) are formed in the active region (2) between the trenches. P+ impurities are injected into the bottom of the emitter contact hole (9) to form a hole injection region (10). An emitter metal region (11) is formed on the insulating layer (14), and the emitter contact hole (9) and the emitter metal region (11) form an ohmic contact.

9. The method for preparing the trench-type IGBT cell structure according to claim 8, characterized in that: Two emitter contact holes (9) are formed in a platform with a width of the first value, and one emitter contact hole (9) is formed in a platform with a width of the second value.

10. The method for preparing the trench-type IGBT cell structure according to claim 8, characterized in that: The hole injection region (10) is formed by multiple injections, each injection forming a P+ injection region. The P+ injection regions are arranged longitudinally, and adjacent P+ injection regions have overlapping areas. The top of the formed hole injection region (10) is located in the active region (2), and the bottom extends into the N-drift layer (1).

Images