Mask layout processing method and device, electronic equipment and storage medium

Abstract

The invention discloses a mask layout processing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a plurality of mask layouts including cutting mask layouts and to-be-processed mask layouts, each cutting mask layout including a cutting pattern, and the to-be-processed mask layouts including isolated cutting patterns; adding an initial pseudo graph corresponding to the isolated cut graph in the mask layout to be processed based on the cut graph in the cut mask layout; predicting a simulation ADI result of the isolated cutting graph based on graph information of the isolated cutting graph in the to-be-processed mask layout added with the initial pseudo graph; when the simulation ADI result does not meet the preset condition, the initial pseudo graph is adjusted, and the graph information is updated based on the adjusted initial pseudo graph until the simulation ADI result meets the preset condition, and a target cutting mask layout corresponding to the to-be-processed mask layout is obtained. The problem that the process manufacturing requirement cannot be met due to the fact that the etching deviation of isolated cutting patterns is small is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a mask layout processing method and device, an electronic device and a storage medium. BACKGROUND

[0002] With the continuous reduction of the critical dimension (CD) of semiconductor devices, the pattern density is becoming much higher than the limit that can be handled by a single exposure, so the multi-patterning (MP) technology and the lithography etching cut (LE+cut) technology are introduced to make the CD and pitch of the patterns on a single mask layout meet the process production capacity.

[0003] In addition, with the increasingly advanced node process, the critical dimension and pitch of the patterns are becoming smaller and smaller, resulting in more and more prominent effects of uneven etching load. Generally, the patterns in the dense region tend to have a larger etching bias, while the patterns in the isolated (ISO) region tend to have a smaller etching bias, and as the critical dimension gradually decreases, the influence of the uneven etching bias caused by the inconsistent pattern density on the overall process stability becomes more and more prominent.

[0004] In the process of implementing the present application, the inventors found that when using multi-pattern technology and lithography etching cut technology for layout splitting, the cut patterns on the split single cut mask layout have the typical characteristic of uneven density distribution, and the etching bias of the isolated pattern region is extremely small, and there is a problem that the ADI (After-Develop Inspection) value is less than the minimum CD of the lithography process, so that the process manufacturing requirements cannot be met. SUMMARY

[0005] To solve the problems of the prior art, the embodiments of the present application provide a mask layout processing method and device, an electronic device and a storage medium. The technical solution is as follows:

[0006] In one aspect, a mask layout processing method is provided, comprising:

[0007] Obtaining a plurality of mask layouts, the plurality of mask layouts including cut mask layouts and a to-be-processed mask layout, each of the cut mask layouts including a cut pattern, and the to-be-processed mask layout including an isolated cut pattern;

[0008] Based on the cut pattern in the cut mask layout, adding an initial pseudo pattern corresponding to the isolated cut pattern in the to-be-processed mask layout;

[0009] predict a simulation developing result of the isolated cutting pattern according to pattern information of the cutting pattern in the to-be-processed mask layout to which the initial dummy pattern is added;

[0010] In a case where the simulation developing result does not satisfy a preset condition, the initial dummy pattern is adjusted, and the pattern information is updated based on the adjusted initial dummy pattern until the simulation developing result satisfies the preset condition, so as to obtain a target cutting mask layout corresponding to the to-be-processed mask layout.

[0011] In another aspect, a mask layout processing apparatus is provided, comprising:

[0012] a to-be-processed layout obtaining module configured to obtain a plurality of mask layouts, the plurality of mask layouts comprising cutting mask layouts and a to-be-processed mask layout, each of the cutting mask layouts comprising a cutting pattern, and the to-be-processed mask layout comprising an isolated cutting pattern;

[0013] an initial dummy pattern adding module configured to add an initial dummy pattern corresponding to the isolated cutting pattern in the to-be-processed mask layout based on the cutting pattern in the cutting mask layout;

[0014] a detection result predicting module configured to predict a simulation developing result of the isolated cutting pattern according to pattern information of the cutting pattern in the to-be-processed mask layout to which the initial dummy pattern is added;

[0015] an iteration module configured to, in a case where the simulation developing result does not satisfy a preset condition, adjust the initial dummy pattern, and update the pattern information based on the adjusted initial dummy pattern until the simulation developing result satisfies the preset condition, so as to obtain a target cutting mask layout corresponding to the to-be-processed mask layout.

[0016] In some exemplary embodiments, the initial dummy pattern adding module comprises:

[0017] a candidate dummy pattern adding module configured to add a candidate dummy pattern corresponding to a target cutting pattern in the to-be-processed mask layout based on the target cutting pattern in the cutting mask layout, the target cutting pattern being a cutting pattern falling within a significant influence range corresponding to the isolated cutting pattern;

[0018] a conflict detecting module configured to perform conflict detection on the to-be-processed mask layout to which the candidate dummy pattern is added based on mask manufacturing constraints and / or lithography constraints, so as to add an initial dummy pattern in the to-be-processed mask layout according to the candidate dummy pattern.

[0019] In some exemplary embodiments, the conflict detecting module comprises:

[0020] a graphic conflict detection module, configured to perform graphic conflict detection on the to-be-processed mask layout to which the candidate dummy graphic is added based on mask manufacturing constraints and / or photolithography constraints, to obtain a graphic conflict detection result;

[0021] a candidate dummy graphic adjustment module, configured to, in a case where the graphic conflict detection result indicates that there is a conflict candidate dummy graphic, adjust the conflict candidate dummy graphic, and perform the graphic conflict detection based on the adjusted conflict candidate dummy graphic until the graphic conflict detection result indicates that there is no conflict candidate dummy graphic;

[0022] an initial dummy graphic determination module, configured to, in a case where the graphic conflict detection result indicates that there is no conflict candidate dummy graphic, determine the candidate dummy graphic in the to-be-processed mask layout as an initial dummy graphic corresponding to the isolated cut graphic.

[0023] In some exemplary embodiments, the candidate dummy graphic adjustment module, when adjusting the conflict candidate dummy graphic, is specifically configured to compress the conflict candidate dummy graphic along a direction in which a spacing between the conflict candidate dummy graphic and an adjacent cut graphic in the to-be-processed mask layout is enlarged, based on the adjacent cut graphic.

[0024] In some exemplary embodiments, the candidate dummy graphic adding module comprises:

[0025] a first determination module, configured to determine a target cut graphic in the cut mask layout, and a projection graphic of the target cut graphic in the to-be-processed mask layout;

[0026] a second determination module, configured to determine the projection graphic of the target cut graphic as a candidate dummy graphic corresponding to the target cut graphic.

[0027] In some exemplary embodiments, the significant influence range corresponding to the isolated cut graphic comprises a circular region with a center of the isolated cut graphic as a center and a preset length as a radius.

[0028] In some exemplary embodiments, the detection result prediction module comprises:

[0029] an etching bias prediction module, configured to predict an etching bias of the isolated cut graphic based on graphic information of the isolated cut graphic in the to-be-processed mask layout to which the initial dummy graphic is added;

[0030] a simulation result determination module, configured to determine a simulation post-development result of the isolated cut graphic based on the etching bias of the isolated cut graphic and a target critical dimension.

[0031] In some example embodiments, the iteration module is configured to adjust size and / or position information of the initial dummy pattern when performing the adjusting of the initial dummy pattern.

[0032] In some example embodiments, the plurality of mask patterns are obtained based on a split target chip layout, the cutting pattern in the mask pattern corresponds to a cutting region in a mandrel mask pattern, the mandrel mask pattern is obtained based on the split target chip layout, and the mandrel mask pattern includes a mandrel pattern for defining a mandrel structure formed in a sacrificial layer.

[0033] In some example embodiments, the target chip layout is used to define a pattern of a zeroth metal layer.

[0034] In some example embodiments, the apparatus further includes:

[0035] a correction module configured to correct the target cutting mask layout using an optical proximity effect to obtain a corrected target cutting mask layout, wherein the corrected target cutting mask layout is used to manufacture a cutting mask.

[0036] In another aspect, an electronic device is provided, which includes a processor and a memory, the memory having stored therein at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement the mask layout processing method of any of the above aspects.

[0037] In another aspect, a computer-readable storage medium is provided, the computer-readable storage medium having stored therein at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by a processor to implement the mask layout processing method of any of the above aspects.

[0038] The embodiment of the application obtains a plurality of mask layouts, the plurality of mask layouts cut a mask layout and a to-be-processed mask layout, each cut mask layout includes a cut pattern, and the to-be-processed mask layout includes an isolated cut pattern. Then, based on the cut pattern in each cut mask layout, an initial pseudo pattern corresponding to the isolated cut pattern is added in the to-be-processed mask layout, the simulation developing result is predicted according to the pattern information of the isolated cut pattern in the to-be-processed mask layout to which the initial pseudo pattern is added, and in the case that the simulation developing result does not meet a preset condition, the initial pseudo pattern is adjusted, and the pattern information is updated based on the adjusted initial pseudo pattern to perform iteration until the simulation developing result meets the preset condition to obtain a target cut mask layout corresponding to the to-be-processed mask layout. Thus, a small pseudo pattern with higher size freedom and assisted in situ is realized, the pattern density of the cut mask layout can be effectively balanced, the local pattern density is increased, the problem that the etching deviation of the isolated cut pattern is too small to meet the process manufacturing requirement is avoided, and the process environment stability under an advanced node is improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] Figure 1 is an example of forming a zeroth metal layer (referred to as M0) by using a photolithography etching cutting (LE+cut) technology.

[0041] Figure 2 is a schematic diagram of splitting a typical M0 cutting layer into three cutting mask layouts;

[0042] Figure 3 is a schematic diagram of the relationship between etching deviation and pattern density provided by the embodiment of the present application;

[0043] Figure 4 is a schematic diagram of etching deviation of a pattern dense area and a pattern isolated area provided by the embodiment of the present application;

[0044] Figure 5 is a schematic diagram of the distribution of cut patterns on a single cutting mask layout after splitting provided by the embodiment of the present application;

[0045] Figure 6 is a schematic diagram of adding a pseudo pattern with a fixed size in batches in a layout in the prior art;

[0046] Figure 7 is a flowchart of a mask layout processing method provided by the embodiment of the present application;

[0047] Figure 8 is a flowchart of another mask layout processing method provided by an embodiment of the present application;

[0048] Figure 9 is a schematic diagram of adding a candidate pseudo pattern corresponding to a target cutting pattern in a to-be-processed mask layout based on the target cutting pattern in the cutting mask layout provided by an embodiment of the present application;

[0049] Figure 10 is a schematic diagram of adjusting a conflict candidate pseudo pattern provided by an embodiment of the present application;

[0050] Figure 11 is a schematic diagram of a single-side etching deviation of a certain pattern in an SEM image provided by an embodiment of the present application;

[0051] Figure 12 is a schematic diagram of a target ADI result of an isolated cutting pattern in the mask layout provided by an embodiment of the present application; Figure 10

[0052] Figure 13 is a schematic diagram of iteratively performing steps S705 to S709 provided by an embodiment of the present application;

[0053] Figure 14 is a structural block diagram of a mask layout processing device provided by an embodiment of the present application;

[0054] Figure 15 is a structural block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0056] ​It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the present application described herein are, for example, capable of efficient use, orderly understanding, and accurate transitions among others. It is to be understood that the terms "comprising", "including", and "having" when used in this specification, specify the presence of stated features, steps or components but do not preclude the presence or addition of one or more other features, steps, components, or groups thereof. In addition, it should be understood that embodiments of the present application can include hardware, software, firmware, or combinations thereof, use of a computer, or use of software, in connection with the foregoing disclosure, including any combinations of tasks or steps predominantly associated with computers or software.

[0057] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0058] In addition, in the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program having a predetermined function and working together with other relevant parts to achieve a predetermined target, and can be implemented in whole or in part by using software, hardware (such as a processing circuit or a memory), or a combination thereof. Similarly, one processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an integral module or unit that includes the functions of the module or unit.

[0059] As the critical dimension (CD) of semiconductor devices continues to shrink, pattern density is becoming far beyond the limits of a single exposure. Therefore, multi-patterning (MP) technology and lithography+cut technology have been introduced to ensure that the pattern CD and pitch on a single mask layout meet the process manufacturing capabilities. For example, to form the zeroth metal layer (hereinafter referred to as M0), please refer to... Figure 1 and Figure 2 ,in Figure 1 The image shows an example of forming the zeroth metal layer M0 using photolithography etching (LE+cut) technology; Figure 2 The image shows a typical M0 cutting layer split into 3 cutting mask layouts. Different gray values ​​represent different cutting mask layouts, and cutting patterns with the same gray value are located on the same cutting mask layout.

[0060] Furthermore, as node technology becomes increasingly advanced, the critical dimensions and spacing of the patterns are also decreasing, leading to a more pronounced impact of uneven etching load, such as... Figure 3 As shown, patterns in dense areas (hereinafter referred to as dense patterns) often have a large etching bias, while patterns in isolated areas (hereinafter referred to as isolated patterns) often have a smaller etching bias. As the critical dimensions gradually decrease, the impact of this uneven etching bias caused by inconsistent pattern distribution density on the overall process stability becomes more and more apparent.

[0061] Etching deviation can typically be characterized by the difference between the critical dimensions obtained from After-Develop Inspection (ADI) and After-Etch Inspection (AEI). For example... Figure 4 The diagram shows the etching deviation between densely packed and isolated areas of the pattern.

[0062] In the process of realizing this invention, the inventors discovered that when using multi-patterning technology and photolithography etching cutting technology for layout splitting, the cut patterns on the split single-cut mask layout have typical characteristics of uneven pattern density distribution, such as... Figure 5 As shown in the cut mask pattern on the right, the etching deviation of isolated areas in the cut mask pattern is extremely small, and there is... Figure 4 The calculated theoretical ADI (After-Develop Inspection) value shown in the isolated region of the graphic is less than the minimum CD of the lithography process, which leads to the inability to meet the manufacturing requirements.

[0063] One approach in related technologies is to enlarge isolated patterns to meet basic process requirements; however, this method is prone to bridging problems caused by excessively large patterns. Another approach, which improves pattern density differences by adding dummy patterns to the mask layout, typically involves adding fixed-size dummy patterns in batches. Therefore, this method can only add dummy patterns to the edge regions of the chip pattern to help balance the pattern density on the layout, such as... Figure 6 As shown in the figure. The cut patterns in the cut mask layout are usually located in complex pattern areas inside the chip pattern. Therefore, the surrounding environment of isolated cut patterns in the cut mask layout is complex. It is impossible to solve the problem of the etching deviation of isolated cut patterns being too small or even below the limit of photolithography process by adding pseudo patterns of fixed size in batches. Moreover, such weaknesses are also difficult to solve by traditional optical proximity correction (OPC) technology.

[0064] In view of this, embodiments of this application provide a mask pattern processing method. This method acquires multiple mask patterns, which are then used to cut a mask pattern and a mask pattern to be processed. Each cut mask pattern includes a cut pattern, and the mask pattern to be processed includes isolated cut patterns. Based on the cut patterns in each cut mask pattern, an initial pseudo-pattern corresponding to the isolated cut pattern is added to the mask pattern to be processed. The simulation ADI result is predicted based on the pattern information of the isolated cut pattern in the mask pattern to be processed with the added initial pseudo-pattern. If the simulation ADI result does not meet preset conditions, the initial pseudo-pattern is adjusted, and the pattern information is updated based on the adjusted initial pseudo-pattern for iteration until the simulation ADI result meets the preset conditions to obtain the target cut mask pattern corresponding to the mask pattern to be processed. This achieves in-situ addition of auxiliary, smaller pseudo-patterns with higher dimensional freedom, effectively balancing the pattern density of the cut mask pattern, increasing local pattern density, avoiding the problem that the etching deviation of isolated cut patterns is too small to meet process manufacturing requirements, and improving the stability of the process environment under advanced nodes.

[0065] The following is combined Figures 7 to 13 The technical solutions of the embodiments of this application will be described in detail.

[0066] Please see Figure 7As shown in the flowchart of the mask layout processing method provided by the embodiments of the present application, the method can be applied to the mask layout processing device of the embodiments of the present application, the mask layout processing device can be configured in an electronic device, the electronic device can be an electronic device including a processor and a memory, wherein the memory stores at least one instruction or at least one program, the at least one instruction or the at least one program is loaded and executed by the processor to implement the mask layout processing method of any one of the above aspects.

[0067] It should be noted that the present specification provides method operation steps as described in the embodiments or flowcharts, but more or fewer operation steps can be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one of the many execution orders, and does not represent the only execution order. In actual system or product execution, the method order shown in the embodiments or the drawings can be executed in sequence or in parallel (for example, in a parallel processor or multi-thread processing environment). Specifically as Figure 7 As shown, the method can include:

[0068] In step S701, a plurality of mask layouts are obtained, the plurality of mask layouts including cutting mask layouts and a to-be-processed mask layout.

[0069] Each cutting mask layout includes a cutting pattern, and the to-be-processed mask layout includes an isolated cutting pattern. Specifically, the plurality of mask layouts can be a plurality of cutting mask layouts obtained based on a split target chip layout, each cutting mask layout includes a cutting pattern for defining a cutting position, and the to-be-processed mask layout includes an isolated cutting pattern.

[0070] The target chip layout is used to define a chip pattern. For example, the chip pattern can be a pattern of a zeroth metal layer (M0).

[0071] Specifically, the target chip layout can be split into a plurality of single mask layouts by a multiple patterning technology, which can include a mandrel mask layout and a plurality of cutting mask layouts. The mandrel mask layout includes a mandrel pattern for defining a mandrel structure formed on a sacrificial layer, and the mandrel mask layout includes a to-be-cut region corresponding to the cutting pattern in the cutting mask layout, so that the structure corresponding to the to-be-cut region in the mandrel structure can be cut off by using the cutting pattern in subsequent processes.

[0072] Specifically, the to-be-processed mask layout can be a mask layout containing isolated cut patterns selected from a plurality of mask layouts. It can be understood that only one mask layout in the plurality of mask layouts can contain isolated cut patterns, that is, only one to-be-processed mask layout exists, or two or more mask layouts can contain isolated cut patterns, that is, two or more to-be-processed mask layouts exist at this time. In this case, the mask layout processing of the present application embodiment can be performed on each to-be-processed mask layout to obtain a target cut mask layout corresponding to each to-be-processed mask layout.

[0073] It should be noted that the isolated cut pattern in the embodiment of the present application refers to a cut pattern meeting the condition that the CD is less than 45 nm or the area is less than 2000 nm 2 , and the space with other patterns around is greater than 120 nm. For each cut mask layout in the plurality of cut mask layouts obtained based on the split target chip layout, the electronic device can search for isolated cut patterns in the cut mask layout. If isolated cut patterns are found, it is determined that the cut mask layout is a to-be-processed mask layout. On the contrary, if no isolated cut patterns are found, the cut mask layout is not a to-be-processed mask layout of the embodiment of the present application.

[0074] It can be understood that one or more isolated cut patterns can exist in the to-be-processed mask layout. The embodiment of the present application can perform adaptive and individualized local pattern density improvement on each isolated cut pattern in the to-be-processed mask layout, so that a target cut mask layout corresponding to the to-be-processed mask layout can be obtained after processing each isolated cut pattern in the to-be-processed mask layout.

[0075] In step S703, based on the cut patterns in the cut mask layout, initial pseudo patterns corresponding to the isolated cut patterns are added in the to-be-processed mask layout.

[0076] Specifically, based on the cut patterns of each cut mask layout in the plurality of mask layouts, initial pseudo patterns corresponding to the isolated cut patterns are added in the to-be-processed mask layout. It can be understood that each cut mask layout in the plurality of mask layouts is a mask layout other than the to-be-processed mask layout in the plurality of mask layouts, that is, when the embodiment of the present application adds initial pseudo patterns corresponding to isolated cut patterns in the to-be-processed mask layout, the addition of initial pseudo patterns is based on the cut patterns in the mask layout other than the to-be-processed mask layout in the plurality of mask layouts.

[0077] Specifically, the initial pseudo-graphics added to the mask layout to be processed correspond to the positions of the cut patterns. That is, initial pseudo-graphics can be added at the positions corresponding to each cut pattern. The feature information (such as key dimensions, spacing, etc.) of the initial pseudo-graphics at different positions can be different. After adding the initial pseudo-graphics, the mask layout to be processed conforms to mask manufacturing constraints and lithography constraints. Among them, mask manufacturing constraints can also be called mask manufacturing rules. For example, mask manufacturing constraints may include the minimum spacing, minimum width, minimum interval, etc. of the patterns on the mask, which can be implemented through mask rule check (MRC) in specific implementations. Lithography constraints may include a mask CD of not less than 45nm, a mask pattern spacing of not less than 45nm, etc.

[0078] In some exemplary embodiments, in order to improve the efficiency of mask pattern processing, such as Figure 8 As shown, step S703, when implemented, may include the following steps S801 to S809:

[0079] In step S801, based on the target cutting pattern in the cutting mask layout, candidate pseudo-patterns corresponding to the target cutting pattern are added to the mask layout to be processed.

[0080] The target cutting pattern is the cutting pattern in each cutting mask layout that falls within the significant influence range corresponding to the isolated cutting pattern.

[0081] As mentioned above Figure 5 For example, multiple mask layouts are obtained by splitting them into three cut mask layouts. Assume the mask layout to be processed is a cut mask layout. Figure 2 So, based on the cutting mask Figure 1 and cutting mask Figure 3 The cutting pattern is added to the mask pattern to be processed, and the initial pseudo-pattern is then added to the mask pattern to obtain the target cutting pattern. Figure 1 and cutting mask Figure 3 The cut pattern that falls within the significant influence range corresponding to the isolated cut pattern.

[0082] For example, the significant influence range corresponding to an isolated cut pattern may include a circular region with the center of the isolated cut pattern as the center and a preset length as the radius. The preset length can be set based on practical experience; for example, the preset length may be approximately 150 nm.

[0083] Specifically, the candidate dummy pattern can be a pattern with the same position and size as the corresponding target cut pattern. For example, adding a candidate dummy pattern corresponding to a target cut pattern in a to-be-processed mask layout can include determining the target cut pattern in each cut mask layout, projecting the target cut pattern in the to-be-processed mask layout, and determining the projected target cut pattern as the candidate dummy pattern corresponding to the target cut pattern.

[0084] Referring to Figure 9 , which shows a schematic diagram of adding a candidate dummy pattern corresponding to a target cut pattern in a to-be-processed mask layout based on the target cut pattern in a cut mask layout. As Figure 9 shown, the dashed circular region is the significant influence range of the isolated cut pattern, and the cut patterns in each cut mask layout that fall within the dashed circular region are target cut patterns. By forming a projected pattern with the same size as the target cut pattern at the position of the target cut pattern as a candidate dummy pattern, a basis is provided for subsequent formation of a final auxiliary dummy pattern.

[0085] The above embodiment, by projecting the target cut pattern in each cut mask layout that falls within the significant influence range of the isolated cut pattern in the to-be-processed mask layout as a candidate dummy pattern, not only improves the overall mask layout processing efficiency, but also provides a basis for subsequent in-situ formation of an auxiliary dummy pattern.

[0086] In step S803, the to-be-processed mask layout with the added candidate dummy pattern is subjected to conflict detection based on mask manufacturing constraints and / or lithography constraints, to add an initial dummy pattern to the to-be-processed mask layout based on the candidate dummy pattern.

[0087] In the embodiments of the present application, in order to ensure the safety of subsequent mask manufacturing, after adding the candidate dummy pattern, it is further necessary to confirm whether the candidate dummy pattern conflicts with the isolated cut pattern itself and the existing cut patterns on the to-be-processed mask layout, which violates the mask manufacturing constraints and / or lithography constraints.

[0088] Specifically, continuing to refer to Figure 8 , the above step S803 can include, when implemented:

[0089] In step S805, the to-be-processed mask layout with the added candidate dummy pattern is subjected to pattern conflict detection based on mask manufacturing constraints and / or lithography constraints, to obtain a pattern conflict detection result.

[0090] The pattern conflict detection result is used to indicate whether there is a conflict candidate dummy pattern that conflicts. Specifically, if the pattern conflict detection result indicates that there is a conflict candidate dummy pattern, the following step S807 can be performed; otherwise, if the pattern conflict detection result indicates that there is no conflict dummy pattern, the following step S809 can be performed.

[0091] In step S807, in a case where the graphic conflict detection result indicates that there is a conflict candidate dummy graphic, the conflict candidate dummy graphic is adjusted, and based on the adjusted conflict candidate dummy graphic, the foregoing step S805 is returned to be executed until the graphic conflict detection result indicates that there is no conflict candidate dummy graphic, the following step S809 can be executed.

[0092] Exemplarily, the adjustment of the conflict candidate dummy graphic can include: based on an adjacent cutting graphic of the conflict candidate dummy graphic in the to-be-processed mask layout, compressing the conflict candidate dummy graphic along a direction of expanding a space between the conflict candidate dummy graphic and the adjacent cutting graphic. As shown in the following figure, by compressing the candidate dummy graphic, the candidate dummy graphic located in the conflict space can be removed, and thus the conflict is finally avoided to make the current to-be-processed mask layout conform to the mask manufacturing constraint and / or the lithography constraint. Figure 10

[0093] In step S809, in a case where the graphic conflict detection result indicates that there is no conflict candidate dummy graphic, the candidate dummy graphic in the to-be-processed mask layout is taken as an initial dummy graphic corresponding to the isolated cutting graphic.

[0094] It can be understood that the initial dummy graphic corresponding to the isolated cutting graphic at this time can include the adjusted candidate dummy graphic.

[0095] The graphic conflict detection on the to-be-processed mask layout after adding the candidate dummy graphic and the adjustment of the candidate dummy graphic based on the graphic conflict detection result in the foregoing embodiments can ensure that the auxiliary dummy graphic finally added around the isolated cutting graphic conforms to the mask manufacturing constraint and / or the lithography constraint.

[0096] In step S705, according to the graphic information of the isolated cutting graphic in the to-be-processed mask layout to which the initial dummy graphic is added, a simulation developing result of the isolated cutting graphic is predicted.

[0097] The graphic information of the isolated cutting graphic in the to-be-processed mask layout can include a size of the isolated cutting graphic itself and a space between the isolated cutting graphic and the surrounding graphics.

[0098] ​Specifically, the etch bias can be predicted in combination with a preset etch bias model, and then the simulated development result can be calculated based on the predicted etch bias. It should be noted that the simulated development result refers to the simulated post-development ADI result, which can also be referred to as a simulated ADI result. The etch bias model is established by collecting a large number of ADI results of test patterns and corresponding AEI results, simulating the etching particle behavior on the wafer surface, and thus can be used to predict the etching bias of a new pattern in a specific environment. The following is an example of an etch bias model:

[0099] Etch Bias = C0 + C1*K1 + C2*K2 + C3*K1 2 + C4*K2 2 + C5*K1*K2

[0100] Wherein, C0-C5 are coefficients, which can be understood as weights; K1-K2 represent Gaussian kernel functions, which are used to describe different etching particle behaviors.

[0101] Based on this, step S705 can include, based on the pattern information of the isolated cut pattern in the mask layout to which the initial dummy pattern is added, predicting the etch bias of the isolated cut pattern; and based on the etch bias of the isolated cut pattern and the target critical dimension, determining the simulated development result of the isolated cut pattern.

[0102] Wherein, the target critical dimension is the target AEI result, which should be equal to the design size of the isolated cut pattern in numerical value, and then the simulated ADI result can be the sum of the target AEI result and the etching bias.

[0103] In some exemplary embodiments, in order to improve the accuracy of the predicted simulated ADI result and improve the accuracy of the finally added auxiliary dummy pattern, the above-mentioned etch bias model of the embodiments of the present application can predict the one-side etching bias, and then the simulated ADI result can be calculated on both sides respectively. As Figure 11 The following is a schematic diagram of the one-side etching bias of a pattern in a SEM image, wherein the left pattern represents the SEM image of the AEI of the layout, and the right side schematically shows the etching bias bias1 and bias2 of a pattern at different one-side edges in the SEM image. AEI sem represents the SEM image of the AEI of the pattern, which can be understood as the target AEI; ADI sem represents the SEM image of the ADI of the pattern, which can be understood as the simulated ADI.

[0104] In step S707, it is determined whether the simulated development result meets the preset condition.

[0105] The preset condition can be that a difference between the target development result and the simulation development result is less than or equal to a preset difference threshold, which can be set based on actual experience, for example, can be zero, and thus when the simulation development result is consistent with the target development result, it is considered that the preset condition is met, and otherwise, when the simulation development result is inconsistent with the target development result, it is considered that the preset condition is not met.

[0106] The target development result, that is, the target ADI result, can be a CD value or a length-width value or an area value. In specific implementation, the value of the target ADI result can be set based on the aforementioned etching compensation model, and the target ADI result is used to ensure that lithography can accurately expose the required real pattern size, and etching can make the pattern size meet the TGT requirement. For example, the target ADI result can be set to about 45x70 nm. Figure 12 FIG. 3 shows a schematic diagram of a target ADI result of an isolated cut pattern. Figure 10 FIG. 4 shows a schematic diagram of a target ADI result of an isolated cut pattern.

[0107] Specifically, if the result of the judgment is that the difference between the target development result and the simulation development result is greater than the preset difference threshold, it is determined that the simulation development result does not meet the preset condition, and the following step S709 can be performed; otherwise, if the result of the judgment is that the difference between the target development result and the simulation development result is less than or equal to the preset difference threshold, it is determined that the simulation development result meets the preset condition, and the processing of the to-be-processed mask pattern can be ended to obtain a target cut mask pattern corresponding to the to-be-processed mask pattern.

[0108] In step S709, the initial dummy pattern in the to-be-processed mask pattern is adjusted, and the pattern information in the aforementioned step S705 is updated based on the adjusted initial dummy pattern, so that steps S705 to S709 are iteratively performed until the simulation development result meets the preset condition, and a target cut mask pattern corresponding to the to-be-processed mask pattern is obtained. In the embodiment of the present application, the initial dummy pattern adjusted by the above-mentioned adjustment in the target cut mask pattern can be referred to as an auxiliary dummy pattern, and the added auxiliary dummy pattern can make the corresponding isolated cut pattern reach the target ADI result.

[0109] FIG. 5 shows a schematic diagram of an auxiliary dummy pattern. Figure 13 FIG. 6 shows a schematic diagram of iterative execution of steps S705 to S709, and through multiple rounds of iteration, the finally added auxiliary dummy pattern can help the isolated cut pattern to reach the target ADI result.

[0110] For example, adjusting the initial dummy pattern can be adjusting the size and / or position information of the initial dummy pattern.

[0111] In some example embodiments, after obtaining the target cutting mask layout corresponding to the mask layout to be processed, the method can further include: correcting the target cutting mask layout by using an optical proximity effect to obtain a corrected target cutting mask layout; and using the corrected target cutting mask layout to manufacture a cutting mask.

[0112] The technical solution of the embodiments of the present application considers that the multiple patterning cutting layers are often realized by multiple LE processes, and multiple cutting mask layouts are finally presented on a hard mask, and then subsequent processes are performed. Since the cutting layer is an auxiliary layer of the core shaft structure of the sacrificial layer, after the process production by the multiple exposure technology, only the stopping etching layer of the core shaft structure of the sacrificial layer exists, and the multiple processes of the cutting layer itself do not substantially affect the core shaft structure. Therefore, the unique feature of the multiple patterning cutting layer can be used to generate a process capability of the auxiliary pattern similar to the cutting layer pattern itself, thereby realizing the in-situ addition of the small auxiliary pseudo-pattern with higher size freedom, effectively balancing the pattern density of the cutting mask layout, increasing the local pattern density, avoiding the problem that the etching deviation of the isolated cutting pattern is too small to meet the process manufacturing requirements, and improving the process environment stability at the advanced node.

[0113] Corresponding to the mask layout processing method provided in the above several embodiments, the embodiments of the present application also provide a mask layout processing device. Since the mask layout processing device provided by the embodiments of the present application corresponds to the mask layout processing method provided by the above several embodiments, the implementation modes of the foregoing mask layout processing method are also applicable to the mask layout processing device provided by the embodiments of the present application, which will not be described in detail in the embodiments.

[0114] Please refer to Figure 14 which is a structural schematic diagram of a mask layout processing device provided by the embodiments of the present application. The device has the function of realizing the mask layout processing method in the above method embodiments. The function can be realized by hardware, or the corresponding software can be executed by hardware. As Figure 14 shown, the mask layout processing device 1400 can include:

[0115] A to-be-processed layout acquisition module 1410 is configured to acquire a plurality of mask layouts, wherein the plurality of mask layouts include cutting mask layouts and a mask layout to be processed, each of the cutting mask layouts includes a cutting pattern, and the mask layout to be processed includes an isolated cutting pattern.

[0116] An initial pseudo-pattern adding module 1420 is configured to add an initial pseudo-pattern corresponding to the isolated cutting pattern in the mask layout to be processed based on the cutting pattern in the cutting mask layout.

[0117] The detection result prediction module 1430 is configured to predict a simulation developing result of the isolated cutting pattern according to pattern information of the isolated cutting pattern in the to-be-processed mask layout to which the initial dummy pattern is added.

[0118] The iteration module 1440 is configured to adjust the initial dummy pattern in a case where the simulation developing result does not satisfy a preset condition, and update the pattern information based on the adjusted initial dummy pattern until the simulation developing result satisfies the preset condition, so as to obtain a target cutting mask layout corresponding to the to-be-processed mask layout.

[0119] In some example embodiments, the initial dummy pattern adding module 1420 comprises:

[0120] The candidate dummy pattern adding module is configured to add a candidate dummy pattern corresponding to a target cutting pattern in the to-be-processed mask layout based on the target cutting pattern in the cutting mask layout, the target cutting pattern being a cutting pattern falling within a significant influence range corresponding to the isolated cutting pattern.

[0121] The conflict detection module is configured to perform conflict detection on the to-be-processed mask layout to which the candidate dummy pattern is added based on mask manufacturing constraints and / or photolithography constraints, so as to add an initial dummy pattern in the to-be-processed mask layout according to the candidate dummy pattern.

[0122] In some example embodiments, the conflict detection module comprises:

[0123] The pattern conflict detection module is configured to perform pattern conflict detection on the to-be-processed mask layout to which the candidate dummy pattern is added based on mask manufacturing constraints and / or photolithography constraints, so as to obtain a pattern conflict detection result.

[0124] The candidate dummy pattern adjustment module is configured to adjust a conflict candidate dummy pattern in a case where the pattern conflict detection result indicates that there is a conflict candidate dummy pattern, and perform the pattern conflict detection based on the adjusted conflict candidate dummy pattern until the pattern conflict detection result indicates that there is no conflict candidate dummy pattern.

[0125] The initial dummy pattern determination module is configured to determine the candidate dummy pattern in the to-be-processed mask layout as an initial dummy pattern corresponding to the isolated cutting pattern in a case where the pattern conflict detection result indicates that there is no conflict candidate dummy pattern.

[0126] In some exemplary embodiments, the candidate pseudo-pattern adjusting module is specifically configured to, when adjusting the conflict candidate pseudo-pattern, compress the abnormal candidate pseudo-pattern along a direction in which a spacing between the conflict candidate pseudo-pattern and an adjacent cutting pattern in the to-be-processed mask layout is enlarged, based on the adjacent cutting pattern of the conflict candidate pseudo-pattern in the to-be-processed mask layout.

[0127] In some exemplary embodiments, the candidate pseudo-pattern adding module comprises:

[0128] The first determining module is configured to determine the projection pattern of the target cutting pattern in the to-be-processed mask layout.

[0129] The second determining module is configured to determine the projection pattern of the target cutting pattern as the candidate pseudo-pattern corresponding to the target cutting pattern.

[0130] In some exemplary embodiments, the significant influence range corresponding to the isolated cutting pattern comprises a circular region with a center of the isolated cutting pattern as a center and a preset length as a radius.

[0131] In some exemplary embodiments, the detection result predicting module 1430 comprises:

[0132] The etching deviation predicting module is configured to predict an etching deviation of the isolated cutting pattern based on pattern information of the isolated cutting pattern in the to-be-processed mask layout to which the initial pseudo-pattern is added.

[0133] The simulation result determining module is configured to determine a simulation post-development result of the isolated cutting pattern based on the etching deviation of the isolated cutting pattern and a target critical dimension.

[0134] In some exemplary embodiments, the iteration module 1440 is specifically configured to adjust size and / or position information of the initial pseudo-pattern when performing the adjustment on the initial pseudo-pattern.

[0135] In some exemplary embodiments, the plurality of mask layouts are obtained based on a split target chip layout, the cutting patterns in the mask layouts correspond to to-be-cut regions in a mandrel mask layout, the mandrel mask layout is obtained based on the split target chip layout, and the mandrel mask layout comprises mandrel patterns used to define a mandrel structure formed in a sacrificial layer.

[0136] In some exemplary embodiments, the target chip layout is used to define a pattern of a zeroth metal layer.

[0137] In some exemplary embodiments, the apparatus 1400 further comprises:

[0138] The correction module is configured to correct the target cutting mask layout by using an optical proximity effect to obtain a corrected target cutting mask layout, wherein the corrected target cutting mask layout is used to manufacture a cutting mask.

[0139] It should be noted that the apparatus provided in the above embodiments is only used as an example to divide the above functional modules to achieve the functions thereof, and in actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above-described functions. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be described here.

[0140] The electronic device provided in the embodiments of the present application includes a processor and a memory, and the memory stores at least one instruction or at least one program, which is loaded and executed by the processor to implement any one of the mask layout processing methods provided in the above method embodiments.

[0141] The memory can be used to store software programs and modules, and the processor can execute various functional applications and data processing by running the software programs and modules stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, application programs required by functions, etc.; and the data storage area can store data created according to the use of the device, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory device. Accordingly, the memory can also include a memory controller to provide access of the processor to the memory.

[0142] Figure 15 is a hardware structure block diagram of an electronic device provided in the embodiments of the present application to run a mask layout processing method, as Figure 15 shown, the internal structure of the electronic device can include but is not limited to a processor, a network interface and a memory. Among them, the processor, the network interface and the memory in the electronic device can be connected through a bus or other means, in the embodiment of the present application Figure 15 is taken as an example to connect through a bus.

[0143] The processor (or CPU (Central Processing Unit)) is the computing core and control core of the electronic device. The network interface can optionally include a standard wired interface, a wireless interface (such as WI-FI, a mobile communication interface, etc.). The memory is a memory device in the electronic device, used to store programs and data. It can be understood that the memory here can be a high-speed RAM memory device, or a non-volatile memory, for example, at least one disk storage device; optionally, it can also be at least one storage device located away from the aforementioned processor. The memory provides a storage space that stores the operating system of the electronic device, which can include but is not limited to: a Windows system (an operating system), a Linux (an operating system), an Android (a mobile operating system) system, an IOS (a mobile operating system) system, etc., and the present application is not limited thereto; and in the storage space, one or more instructions suitable for being loaded and executed by the processor are also stored, and these instructions can be one or more computer programs (including program codes). In the embodiment of the present application, the processor loads and executes one or more instructions stored in the memory to implement any one of the mask layout processing methods provided by the above method embodiments.

[0144] The embodiment of the present application also provides a computer readable storage medium, which can be arranged in an electronic device to save at least one instruction or at least one program related to a mask layout processing method, and the at least one instruction or the at least one program is loaded and executed by the processor to implement any one of the mask layout processing methods provided by the above method embodiments.

[0145] Optionally, in the present embodiment, the above-mentioned storage medium can include but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0146] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A mask layout processing method, characterized by, include: Multiple mask layouts are obtained, including cut mask layouts and mask layouts to be processed. Each cut mask layout includes a cut pattern, and each mask layout to be processed includes an isolated cut pattern. Based on the cutting pattern in the cutting mask layout, an initial pseudo-pattern corresponding to the isolated cutting pattern is added to the mask layout to be processed; Based on the graphic information of the isolated cut graphic in the mask layout to be processed with the initial pseudo graphic added, the simulation development result of the isolated cut graphic is predicted. If the simulation development result does not meet the preset conditions, the initial pseudo-graphic is adjusted, and the graphic information is updated based on the adjusted initial pseudo-graphic until the simulation development result meets the preset conditions, thereby obtaining the target cutting mask pattern corresponding to the mask pattern to be processed.

2. The method of claim 1, wherein, The step of adding an initial pseudo-graphic corresponding to the isolated cut pattern to the mask layout to be processed based on the cut pattern in the cut mask layout includes: Based on the target cutting pattern in the cutting mask layout, a candidate pseudo-pattern corresponding to the target cutting pattern is added to the mask layout to be processed. The target cutting pattern is a cutting pattern that falls within the significant influence range corresponding to the isolated cutting pattern. Based on mask manufacturing constraints and / or photolithography constraints, conflict detection is performed on the mask layout to be processed with the candidate pseudo-patterns added, so as to add an initial pseudo-pattern to the mask layout to be processed according to the candidate pseudo-patterns.

3. The method of claim 2, wherein, The method of performing conflict detection on the mask layout to be processed with the candidate pseudo-graphics added, based on mask manufacturing constraints and / or photolithography constraints, to add an initial pseudo-graphic to the mask layout to be processed according to the candidate pseudo-graphics, includes: Based on mask manufacturing constraints and / or photolithography constraints, the pattern of the mask to be processed with the candidate pseudo-patterns added is subjected to pattern conflict detection to obtain pattern conflict detection results. If the graphic conflict detection result indicates the existence of a conflict candidate pseudo-graphic, the conflict candidate pseudo-graphic is adjusted, and the graphic conflict detection is performed based on the adjusted conflict candidate pseudo-graphic until the graphic conflict detection result indicates that there is no conflict candidate pseudo-graphic. If the graphic conflict detection result indicates that there are no conflict candidate pseudo-graphics, the candidate pseudo-graphics in the mask layout to be processed are used as the initial pseudo-graphics corresponding to the isolated cut graphic.

4. The method of claim 3, wherein, The adjustment of the conflict candidate pseudo-graphics includes: Based on the adjacent cut patterns of the conflict candidate pseudo-graphics in the mask layout to be processed, the conflict candidate pseudo-graphics are compressed along the direction of increasing the interval between the conflict candidate pseudo-graphics and the adjacent cut patterns.

5. The method of claim 2, wherein, The step of adding candidate pseudo-graphics corresponding to the target cut pattern in the cut mask layout, based on the target cut pattern in the cut mask layout, includes: Determine the target cutting pattern in the cutting mask layout and its projection pattern in the mask layout to be processed; The projected image of the target cut image is determined as a candidate pseudo-image corresponding to the target cut image.

6. The method of claim 2, wherein, The significant influence range corresponding to the isolated cut pattern includes a circular area with the center of the isolated cut pattern as the center and a preset length as the radius.

7. The method of claim 1, wherein, The step of predicting the simulation development result of the isolated cut pattern based on the pattern information in the mask layout to be processed with the initial pseudo-pattern added includes: Based on the graphic information of the isolated cut pattern in the mask layout to be processed with the initial pseudo pattern added, the etching deviation of the isolated cut pattern is predicted. Based on the etching deviation and target critical dimensions of the isolated cut pattern, the simulation development result of the isolated cut pattern is determined.

8. The method according to claim 1, characterized in that, The adjustment of the initial pseudo-graphic includes: adjusting the size and / or position information of the initial pseudo-graphic.

9. The method according to claim 1, characterized in that, The plurality of mask layouts are obtained based on the split target chip layout. The cutting patterns in the mask layouts correspond to the areas to be cut in the mandrel mask layout. The mandrel mask layout is obtained based on the split target chip layout. The mandrel mask layout includes a mandrel pattern for defining the mandrel structure formed on the sacrificial layer.

10. The method according to claim 9, characterized in that, The target chip layout is used to define the pattern of the zeroth metal layer.

11. The method according to any one of claims 1 to 10, characterized in that, After obtaining the target cutting mask layout corresponding to the mask layout to be processed, the method further includes: The target cutting mask pattern is modified using the optical proximity effect to obtain a modified target cutting mask pattern; wherein, the modified target cutting mask pattern is used to fabricate the cutting mask.

12. A mask layout processing apparatus, characterized in that, include: The unprocessed layout acquisition module is used to acquire multiple mask layouts, the multiple mask layouts including cut mask layouts and unprocessed mask layouts, each cut mask layout including cut patterns, and the unprocessed mask layout including isolated cut patterns; An initial pseudo-graphics adding module is used to add an initial pseudo-graphics corresponding to the isolated cut pattern in the cut mask layout based on the cut pattern in the cut mask layout; The detection result prediction module is used to predict the simulation development result of the isolated cut pattern based on the graphic information of the isolated cut pattern in the mask layout to be processed with the initial pseudo pattern added. An iterative module is used to adjust the initial pseudo-graphics when the simulation development result does not meet the preset conditions, and update the graphic information based on the adjusted initial pseudo-graphics until the simulation development result meets the preset conditions, thereby obtaining the target cutting mask pattern corresponding to the mask pattern to be processed.

13. An electronic device, characterized in that, The method includes a processor and a memory, wherein the memory stores at least one instruction or at least one program, and the at least one instruction or the at least one program is loaded and executed by the processor to implement the mask layout processing method as described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one instruction or at least one program, which is loaded and executed by a processor to implement the mask layout processing method as described in any one of claims 1 to 11.

Images