Frequency-voltage conversion circuit and integrated circuit using same
By using a frequency divider circuit to generate a switching control signal with a phase difference through a simple logic combination, the robustness problem caused by inverter chain delay is solved, achieving high-precision and stable frequency-voltage conversion.
Patent Information
- Application Number
- CN202510965287.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-11
- Publication Date
- 2025-11-25
AI Technical Summary
Existing frequency-to-voltage conversion circuits have poor robustness and are greatly affected by process, voltage, and temperature fluctuations because the generation of control signals depends on the delay of the inverter chain.
By reusing the clock input signal that represents the frequency information before the frequency divider circuit, and using simple combinational logic to generate two-phase switching control signals with a phase difference, the use of inverters is avoided, thereby reducing the impact of process, voltage and temperature on circuit stability.
It achieves high-precision and stable frequency-to-voltage conversion, improves the robustness of the circuit, and reduces the impact of process, voltage, and temperature fluctuations.
Smart Images
Figure CN121012489A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and more specifically, to a frequency-to-voltage conversion circuit and an integrated circuit using the same. Background Technology
[0002] A frequency-to-voltage converter (FVC) is an electronic circuit whose core function is to linearly convert a periodic frequency signal (such as a square wave or sine wave) into a corresponding DC voltage output. This is typically achieved through integration or charge balancing techniques, such as using the charging and discharging process of a capacitor to accumulate charge, thereby generating a DC output voltage related to the input frequency signal.
[0003] Existing frequency-to-voltage conversion circuits have poor robustness because the generation of control signals depends on the delay of the inverter chain to generate two non-overlapping signals. This delay fluctuates with process, voltage, and temperature (PVT). Summary of the Invention
[0004] In view of this, the present invention provides a frequency-to-voltage conversion circuit with high accuracy and high stability.
[0005] In a first aspect, the present invention provides a frequency-to-voltage conversion circuit, characterized in that it comprises:
[0006] A phase module is used to generate a frequency division signal based on a clock input signal representing frequency information, and to generate multiple switching control signals for a conversion module based on the frequency division signal and the clock input signal, wherein the frequency of the clock input signal is N times that of the frequency division signal, where N is a positive integer and N≠1;
[0007] The conversion module is controlled by the plurality of switch control signals to convert the frequency division signal into an output voltage related to the frequency of the clock input signal.
[0008] Preferably, the phase module generates two switching control signals with different phase delays relative to the frequency division signal and the same period as the frequency division signal, based on the frequency division signal and the clock input signal.
[0009] Preferably, the phase module generates a switch control signal with two effective level state intervals that do not overlap, based on the frequency division signal and the clock input signal.
[0010] Preferably, the phase module generates a first switch control signal in an effective level state during a phase in which both the frequency division signal and the clock input signal are at a low level within one cycle of the frequency division signal, and generates a first switch control signal in an ineffective level state during the remaining phases.
[0011] Preferably, the phase module generates a signal with the same phase as the frequency division signal as a second switch control signal.
[0012] Preferably, the phase module outputs the frequency division signal as a second switch control signal.
[0013] Preferably, within one cycle of the frequency division signal, the phase module generates a third switch control signal with an effective level state during the phase when both the inverted signal of the frequency division signal and the clock input signal are at a high level, and generates the third switch control signal with an invalid level state during the other phases.
[0014] Preferably, the phase module includes:
[0015] A frequency divider circuit is used to receive the clock input signal and divide the clock input signal according to a predetermined frequency division ratio to obtain the frequency-divided signal.
[0016] The first logic circuit includes an OR gate, wherein the input terminals of the OR gate receive the clock input signal and the frequency division signal respectively, and output a first switch control signal;
[0017] The second logic circuit includes an AND gate, the input terminals of which receive the clock input signal and the inverted signal of the frequency division signal, respectively, and output a third switch control signal.
[0018] Preferably, the frequency divider circuit is configured as a D flip-flop, wherein the clock input terminal of the D flip-flop receives the clock input signal, the data input terminal is shorted to the inverting output terminal, and the frequency divider signal is generated at the inverting output terminal.
[0019] Preferably, the conversion module includes:
[0020] The first and second switches are connected in series.
[0021] The first capacitor is connected in parallel with the second switch;
[0022] A third switch connected between the common node of the second switch and the first capacitor and the output terminal; and,
[0023] A second capacitor connected to the output terminal.
[0024] Preferably, the conversion circuit further includes:
[0025] A constant current source, which outputs the first current;
[0026] A current mirror receives the first current and generates the first current at one power terminal of the second switch in a mirror-replica manner.
[0027] Preferably, the first switch is controlled by the first switch control signal, the second switch is controlled by the frequency division signal, and the third switch is controlled by the third switch control signal.
[0028] Preferably, when operating in the first state, the first switch is turned on, and the first capacitor is charged by the power supply voltage; when operating in the second state, the second switch is turned on, and the first capacitor is discharged through the second switch, with the discharge current being consistent with the first current; when operating in the third state, the third switch is turned on, and the first capacitor and the second capacitor perform charge distribution, with the voltage on the second capacitor serving as the output voltage.
[0029] Preferably, the second switch and the third switch are turned on in the order of the second switch first and then the third switch during the period when the first switch is turned off.
[0030] Preferably, within one cycle of the frequency division signal, the first switch, the second switch, and the third switch are turned on sequentially once.
[0031] In a second aspect, an integrated circuit is provided, characterized in that it comprises:
[0032] The frequency-to-voltage conversion circuit described above.
[0033] The present invention aims to provide a frequency-to-voltage conversion circuit that combines a clock input signal representing frequency information prior to a frequency divider circuit with the frequency divider signal and uses simple combinational logic to generate two-phase switching control signals with a phase difference, thereby avoiding the influence of process, voltage or temperature fluctuations on circuit stability. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0035] Figure 1 This is a partial schematic diagram of the control signal generation circuit in a comparative frequency-to-voltage conversion circuit.
[0036] Figure 2This is a schematic diagram of a frequency-to-voltage conversion circuit according to an embodiment of the present invention;
[0037] Figure 3 This is a schematic diagram of the phase module according to an embodiment of the present invention;
[0038] Figure 4 This is a waveform diagram of the phase module in an embodiment of the present invention.
[0039] Figure 5 This is a schematic diagram of the conversion module according to an embodiment of the present invention. Detailed Implementation
[0040] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0041] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0042] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0043] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."
[0044] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0045] Figure 1 This is a partial schematic diagram of the control signal generation circuit in a proportional frequency-to-voltage conversion circuit. (Example:) Figure 1As shown, in the control signal generation circuit of this comparative amplifier, two non-overlapping signals are generated based on the frequency division signal Fin and two delay times τ1 and τ2. and The delay times τ1 and τ2 are achieved through a delay link composed of inverters. However, the delay accuracy of the inverters fluctuates with process, voltage, and temperature (PVT), which makes the frequency-to-voltage conversion circuit less stable.
[0046] Based on this, the frequency-to-voltage conversion circuit of the present invention does not require delay through an inverter to generate two-phase switching control signals with a phase difference, thereby avoiding the influence of process, voltage or PVT on the circuit. The present invention achieves the same function through simple combinational logic by multiplexing the clock input signal representing frequency information before the frequency divider circuit. Since it is not affected by the performance of the inverter, the frequency-to-voltage conversion circuit of the present invention has high conversion accuracy.
[0047] Figure 2 This is a frequency-to-voltage conversion circuit according to an embodiment of the present invention. For example... Figure 2 As shown, the frequency-to-voltage conversion circuit includes a phase module 21 and a conversion module 22.
[0048] Specifically, phase module 21 generates a frequency-divided signal Fin based on the clock input signal clkin, which represents frequency information, and generates multiple switching control signals Fin, ph1, and ph2 for conversion module 22 based on the frequency-divided signal Fin and the clock input signal clkin. Phase module 21 divides the clock input signal clkin according to a predetermined division ratio, for example, the frequency of the frequency-divided signal Fin is 1 / 2, 1 / 4, or other values of the clock input signal clkin.
[0049] It should be noted that, in one embodiment, the phase module 21 can generate a signal with the same phase as the frequency division signal Fin as the second switch control signal Fin1; in another embodiment, the phase module 21 can also directly output the frequency division signal Fin as the second switch control signal Fin1.
[0050] Preferably, the switch control signals ph1 and ph2 have a phase difference. In one embodiment, the phase module 21 generates two signals with different phase delays relative to the frequency divider signal Fin and the clock input signal clkin, which are respectively used as switch control signals ph1 and ph2; and the switch control signals ph1 and ph2 have the same period as the frequency divider signal Fin, and the effective level intervals of the three signals Fin, ph1, and ph2 do not overlap. In another embodiment, the phase module 21 generates two signals with non-overlapping effective level state intervals based on the frequency divider signal Fin and the clock input signal clkin, which are respectively used as switch control signals ph1 and ph2. In this embodiment of the invention, for distinction, the switch control signal ph2 is designated as the first switch control signal ph2, and the switch control signal ph1 is designated as the third switch control signal ph1.
[0051] Preferably, the phase module 21 generates a first switch control signal ph2 in an effective level state during the period when both the frequency divider signal Fin and the clock input signal clkin are at a low level, and generates a first switch control signal ph2 in an ineffective level state during the remaining periods.
[0052] Meanwhile, within the cycle of a frequency divider signal Fin, the phase module 21 generates a third switch control signal ph1 with an effective level state when both the inverted signal of the frequency divider signal Fin and the clock input signal clkin are at a high level, and generates a third switch control signal ph1 with an invalid level state in other stages.
[0053] The conversion module 22 is controlled by the plurality of switch control signals Fin, ph1 and ph2 to periodically charge and discharge the capacitor, so as to convert the frequency division signal Fin into an output voltage, and then generate an output voltage Vout.
[0054] Therefore, the frequency-to-voltage conversion circuit of this invention uses the clock input signal representing frequency information before the frequency divider circuit and combines it with the frequency divider signal through simple combinational logic to generate two-phase switching control signals with a phase difference, thereby avoiding the influence of process, voltage or temperature fluctuations on circuit stability.
[0055] Figure 3 The circuit structure of a preferred phase module 21 is illustrated. Figure 4 This is a waveform diagram of the phase module 21. Figure 3 As shown, the phase module 21 includes a frequency divider circuit 211, a first logic circuit 212, and a second logic circuit 213.
[0056] Frequency divider circuit 211 receives the clock input signal clkin and divides it according to a predetermined division ratio to obtain the divided signal Fin. Specifically, the divided signal Fin is in phase with the clock input signal clkin, only its frequency is a predetermined multiple of clkin, such as... Figure 4 As shown, this embodiment uses the example of dividing the clock input signal clkin by two to obtain the divided signal Fin.
[0057] In this embodiment of the invention, the frequency divider circuit 211 is implemented using a D flip-flop. Preferably, the clock input signal clkin is connected to the clock input terminal CK of the D flip-flop, and the data input terminal D and the inverting output terminal Qb of the D flip-flop are shorted, so that the frequency divider signal Fin is output at the inverting output terminal Qb of the D flip-flop. (Continue to refer to...) Figure 3 and Figure 4 Within each cycle of the frequency divider signal Fin, when the rising edge of the first clock input signal clkin arrives, the frequency divider signal Fin is 0. Therefore, the data input terminal D of the D flip-flop is 0, the output terminal Q is 0, and the inverting output terminal Qb is 1. Thus, after the rising edge of the first clock input signal clkin, the frequency divider signal Fin remains at 1. When the rising edge of the second clock input signal clkin arrives, the frequency divider signal Fin is 1. Therefore, the data input terminal D is 1, the output terminal Q is 1, and the inverting output terminal Qb is 0. This process repeats, thus dividing the clock input signal clkin by two to obtain the frequency divider signal Fin. Here, 1 represents a high-level signal, and 0 represents a low-level signal.
[0058] The first logic circuit 212 is used to generate a first switch control signal ph2 in an effective level state during the period when both the frequency divider signal Fin and the clock input signal clkin are at a low level, and to generate a first switch control signal ph2 in an ineffective level state during the other periods. In this embodiment of the invention, the first logic circuit 212 includes an OR gate. Specifically, the two input terminals of the OR gate receive the clock input signal clkin and the frequency divider signal Fin, respectively, and the output terminal outputs the first switch control signal ph2.
[0059] The second logic circuit 213 is used to generate a third switch control signal ph1 with an effective level when both the inverted signal of the frequency divider signal Fin and the clock input signal clkin are at a high level, and to generate a third switch control signal ph1 with an invalid level during other stages. In this embodiment of the invention, the first logic circuit 212 includes an AND gate. Specifically, the two input terminals of the AND gate receive the clock input signal clkin and the inverted signal Fin_n of the frequency divider signal Fin, respectively, and the output terminal outputs the third switch control signal ph1. The frequency divider signal Fin is passed through an NOT gate to obtain its inverted signal Fin_n.
[0060] It should be noted that in this embodiment of the invention, the effective level states of the first switch control signal ph2 and the third switch control signal ph1 are opposite. The effective level state of the third switch control signal ph1 is 1, and the effective level state of the first switch control signal ph2 is 0. In this embodiment, the level state when the corresponding switch in the conversion module 22 is turned on is marked as the effective level. Since the second switch Q2 and the third switch Q3 are N-type metal-oxide-semiconductor transistors, the effective level states of their corresponding control signal frequency division signal Fin and the third switch control signal ph1 are 1, respectively; the first switch Q1 is a P-type metal-oxide-semiconductor transistor, so the effective level state of its corresponding first switch control signal ph2 is 0. Therefore, from Figure 4 As can be seen, within each period of the frequency division signal Fin, the effective level states of the first switch control signal ph2 and the third switch control signal ph1 have a phase difference and do not overlap. In other embodiments, the first switch control signal ph2 can also be inverted and used as the first switch control signal ph2. ， This causes the first switch control signal ph2 to... ， The effective level state is 1, and this invention does not limit this.
[0061] It should be understood that the phase module described above is only one type of circuit structure for generating the switch control signal described above, and other circuit structures that are suitable for generating the switch control signal described above are all within the protection scope of the embodiments of the present invention.
[0062] Figure 5 The circuit structure of a preferred conversion module 22 is illustrated. For example... Figure 5 As shown, the conversion module 22 includes: a first switch Q1 and a second switch Q2 connected in series and coupled in series between the power supply voltage Vdd and the reference ground; a first capacitor C1 coupled in parallel with the second switch Q2; a third switch Q3 connected between the common node of the second switch Q2 and the first capacitor C1 and the output terminal; and a second capacitor C2 connected between the output terminal and the reference ground. The end of the first switch Q1 not connected to the second switch Q2 is connected to the power supply voltage Vdd. One end of the first capacitor C1 is connected to the common node of the first switch Q1, the second switch Q2, and the third switch Q3, and the other end is connected to ground potential.
[0063] It should be noted that the switches in the embodiments of the present invention employ metal-oxide-semiconductor transistors (MOSFETs). It should be understood that other electrically controlled switching devices, such as bipolar transistors (BJTs) or insulated-gate bipolar transistors (IGBTs), can also be used as the switches Q of the present invention.
[0064] Specifically, in this embodiment of the invention, the first switch Q1 is a P-type metal-oxide-semiconductor transistor, and the second switch Q2 and the third switch Q3 are N-type metal-oxide-semiconductor transistors.
[0065] Furthermore, the conversion circuit 22 also includes a constant current source and a current mirror. Specifically, the constant current source outputs a first current Idc, and the first current Idc is a fixed current. The current mirror receives the first current Idc and generates a first current Idc at one power terminal of the second switch Q2 in a mirror-replica manner. Specifically, the current mirror includes transistors M1 and M2 connected in a common-source, common-gate configuration. Transistor M2 receives the first current Idc output by the constant current source, transistor M1 is connected in series with the second switch Q2, and the common gate of transistors M1 and M2 is connected to the common node of transistor M2 and the output terminal of the constant current source.
[0066] When the conversion module 22 is working, the first switch Q1 is controlled by the first switch control signal ph2, the second switch Q2 is controlled by the frequency division signal Fin, and the third switch Q3 is controlled by the third switch control signal ph1. Within one cycle of the frequency division signal Fin, the first switch Q1, the second switch Q2, and the third switch Q3 are turned on sequentially once to complete one charge and discharge cycle of the first capacitor C1 and to share the charge on the first capacitor C1 with the charge on the second capacitor C2. After several cycles, the voltage on the second capacitor C2 is stabilized at a value related to the frequency of the input clock signal.
[0067] Preferably, the second switch Q2 and the third switch Q3 are turned on in the following order during the period when the first switch Q1 is off: the second switch Q2 is turned on first, followed by the third switch Q3. When the first switch Q1 is turned on, the voltage on the first capacitor C1 is reset to the supply voltage Vdd; when the second switch Q2 is turned on, the first capacitor C1 discharges with a first current Idc; when the third switch Q3 is turned on, the charge on the first capacitor C1 is shared with the charge on the second capacitor C2.
[0068] Combination Figure 4 The waveform diagram shown below illustrates the working process of the conversion module:
[0069] (1) t2-t3 stage: During this stage, the first switch control signal ph2 is at an effective level and is in a low level state, which makes the first switch Q1 turn on and all other switches turn off, resetting node Vdisch to the supply voltage Vdd;
[0070] (2) t3-t4 stage: During this stage, the frequency divider signal Fin is at an effective level, which is a high level state, causing the second switch Q2 to conduct and all other switches to be turned off. The node Vdisch will discharge. The size ratio of transistors M1 and M2 in the current mirror is 1:1, and transistor M1 replicates the current on M2 proportionally, causing the first capacitor C1 to discharge with the first current Idc. The discharge time is the duration of the effective level of the frequency divider signal Fin. Because in this embodiment, the frequency of the frequency divider signal is 1 / 2 of the frequency of the clock input signal clkin, the duration of the effective level of the clock frequency divider signal Fin is one period of the input signal clkin, which is denoted as Tin, where Tin = 1 / fin, and fin is the frequency of the clock input signal clkin. Therefore, after the discharge stage ends, the voltage value of the Vdisch node is Vdd - Idc * Tin / C1;
[0071] (3) t4 - t1 stage of the next cycle: The third switch control signal ph1 is at an effective level, which is a high level state, so that the third switch Q3 is turned on and all other switches are turned off. The charge on the first capacitor C1 is shared with the charge on the second capacitor C2. After several cycles, the voltage on the second capacitor C2 will stabilize at Vdd-Idc*Tin / C1. Therefore, the voltage on the second capacitor C2 is the output voltage Vout=Vdd-Idc / (fin*C1).
[0072] As can be seen from the above analysis, the frequency-to-voltage conversion circuit of this embodiment of the invention will eventually obtain an output voltage Vout = Vdd - Idc / (fin * C1). This voltage is positively correlated with the frequency fin of the clock input signal clkin. When the frequency fin decreases, the output voltage Vout decreases accordingly, and when the frequency fin increases, the output voltage Vout will also increase.
[0073] Therefore, the frequency-to-voltage conversion circuit of this invention reuses the clock input signal representing the frequency information before the frequency divider circuit, and uses simple combinational logic to generate a two-phase switching control signal with a phase difference, thereby avoiding the influence of process, voltage or temperature fluctuations on circuit stability. The conversion circuit operates under the control of the switching control signal, converting the frequency of the clock input signal into an output voltage that is positively correlated with it.
[0074] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.
Claims
1. A frequency-to-voltage conversion circuit, characterized in that, include: A phase module is used to generate a frequency division signal based on a clock input signal representing frequency information, and to generate multiple switching control signals for a conversion module based on the frequency division signal and the clock input signal, wherein the frequency of the clock input signal is N times that of the frequency division signal, where N is a positive integer and N≠1; The conversion module is controlled by the plurality of switch control signals to convert the frequency division signal into an output voltage related to the frequency of the clock input signal.
2. The frequency-to-voltage conversion circuit according to claim 1, characterized in that, The phase module generates two switch control signals with different phase delays relative to the frequency divider signal and the same period as the frequency divider signal, based on the frequency divider signal and the clock input signal.
3. The frequency-to-voltage conversion circuit according to claim 2, characterized in that, The phase module generates two effective level state intervals that do not overlap based on the frequency division signal and the clock input signal.
4. The frequency-to-voltage conversion circuit according to claim 1, characterized in that, The phase module generates a first switch control signal in an effective level state during a period when both the frequency division signal and the clock input signal are at a low level, and generates a first switch control signal in an ineffective level state during the remaining periods.
5. The frequency-to-voltage conversion circuit according to claim 1, characterized in that, The phase module generates a signal with the same phase as the frequency division signal as a second switch control signal.
6. The frequency-to-voltage conversion circuit according to claim 1, characterized in that, The phase module outputs the frequency division signal as a second switch control signal.
7. The frequency-to-voltage conversion circuit according to claim 1, characterized in that, During one cycle of the frequency division signal, the phase module generates a third switch control signal with an effective level state when both the inverted signal of the frequency division signal and the clock input signal are at a high level, and generates the third switch control signal with an invalid level state during the other stages.
8. The frequency-to-voltage conversion circuit according to claim 1, characterized in that, The phase module includes: A frequency divider circuit is used to receive the clock input signal and divide the clock input signal according to a predetermined frequency division ratio to obtain the frequency-divided signal. The first logic circuit includes an OR gate, wherein the input terminals of the OR gate receive the clock input signal and the frequency division signal respectively, and output a first switch control signal; The second logic circuit includes an AND gate, the input terminals of which receive the clock input signal and the inverted signal of the frequency division signal, respectively, and output a third switch control signal.
9. The frequency-to-voltage conversion circuit according to claim 8, characterized in that, The frequency divider circuit is configured as a D flip-flop, the clock input terminal of the D flip-flop receives the clock input signal, the data input terminal is shorted to the inverting output terminal, and the frequency divider signal is generated at the inverting output terminal.
10. The frequency-to-voltage conversion circuit according to claim 8, characterized in that, The conversion module includes: The first and second switches are connected in series. The first capacitor is connected in parallel with the second switch; A third switch connected between the common node of the second switch and the first capacitor and the output terminal; and, A second capacitor connected to the output terminal.
11. The frequency-to-voltage conversion circuit according to claim 10, characterized in that, The conversion circuit further includes: A constant current source, which outputs the first current; A current mirror receives the first current and generates the first current at one power terminal of the second switch in a mirror-replica manner.
12. The frequency-to-voltage conversion circuit according to claim 10, characterized in that, The first switch is controlled by the first switch control signal, the second switch is controlled by the frequency division signal, and the third switch is controlled by the third switch control signal.
13. The frequency-to-voltage conversion circuit according to claim 11, characterized in that, When operating in the first state, the first switch is turned on, and the first capacitor is charged by the power supply voltage; when operating in the second state, the second switch is turned on, and the first capacitor is discharged through the second switch, and the discharge current is consistent with the first current. When operating in the third state, the third switch is turned on, the first capacitor and the second capacitor perform charge distribution, and the voltage on the second capacitor is used as the output voltage.
14. The frequency-to-voltage conversion circuit according to claim 10, characterized in that, The second switch and the third switch are turned on in the order of the second switch first and then the third switch during the period when the first switch is turned off.
15. The frequency-to-voltage conversion circuit according to claim 10, characterized in that, Within one cycle of the frequency division signal, the first switch, the second switch, and the third switch are turned on once in sequence.
16. An integrated circuit, characterized in that, include: The frequency-to-voltage conversion circuit according to any one of claims 1-15.