Power MOSFET wide SOA structure preparation technology and chip

Abstract

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) wide SOA (Silicon On Architecture) structure preparation process and a chip, a well region is arranged among a plurality of first grooves, a first injection region is arranged in the well region, and a plurality of second injection regions are correspondingly arranged below a part of the well region, so that an MOSFET device with a wider safe working region can be realized; moreover, a proper threshold voltage value is obtained, the overcurrent capability of the SOA can be improved by nearly 2-3 times, and the thermal stability is synchronously reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application belong to the technical field of semiconductor technology, and particularly relate to a power MOSFET wide SOA structure preparation process and a chip. BACKGROUND

[0002] Power MOSFET has the advantages of small volume, fast switching speed, and low power consumption, and is widely used in communication, industrial automation, transportation, and consumer electronics fields. With the continuous development of modern communication industry, electronic systems are often required to have hot plug function, and the key to the realization of hot plug technology is that the safe operating area (SOA) of the power MOSFET is wide enough. However, as the power MOSFET continuously pursues low on-resistance (Ron,sp), the chip area is continuously reduced, and the SOA will inevitably be continuously reduced. Therefore, it is of great significance to design a MOSFET device with a wider safe operating area. SUMMARY

[0003] In order to solve or alleviate the problems in the prior art, in a first aspect, embodiments of the present application provide a power MOSFET wide SOA structure preparation process, comprising:

[0004] etching a plurality of first grooves and second grooves in an epitaxial layer, the epitaxial layer being arranged on a substrate;

[0005] arranging source poly-silicon, first dielectric layer and gate poly-silicon in the first grooves and the second grooves from top to bottom in sequence, respectively;

[0006] forming a well region in the epitaxial layer in the region where the first grooves and the second grooves are located;

[0007] forming a first implantation region in the well region in the epitaxial layer in the region where the first grooves are located;

[0008] forming a second implantation region below the well region in the region where the first grooves are located;

[0009] forming a second dielectric layer on the surface of the epitaxial layer;

[0010] arranging a source contact hole and a gate contact hole in the second dielectric layer, the source contact hole extending to the well region in the region where the first grooves are located through the second dielectric layer and the first implantation region in sequence so as to lead out the source, and the gate contact hole extending to the gate poly-silicon in the second grooves so as to lead out the gate;

[0011] depositing metal in the source contact hole and the gate contact hole, and forming a source metal layer and a gate metal layer arranged at intervals on the surface of the second dielectric layer;

[0012] A drain metal layer is provided on the side of the substrate away from the epitaxial layer to lead out the drain.

[0013] In a second aspect, the MOSFET chip is prepared by the process of any one of the first aspect, and the structure comprises: a MOSFET body;

[0014] The MOSFET body comprises a plurality of first trenches and second trenches arranged at intervals, and the upper surface of the MOSFET body corresponding to the first trenches is provided with a second dielectric layer, a source lead-out area, and the upper surface of the MOSFET body corresponding to the second trenches is provided with a second dielectric layer and a gate lead-out area.

[0015] The source lead-out area comprises a source metal layer and a source contact hole.

[0016] The gate lead-out area comprises a gate metal layer and a gate contact hole.

[0017] The source metal layer and the gate metal layer are arranged at intervals.

[0018] A well region is arranged between the plurality of first trenches, and a first implantation region is arranged in the well region, and a plurality of second implantation regions are arranged below part of the well region.

[0019] The source contact hole extends through the second dielectric layer, the first implantation region, and the well region in the area of the first trench to lead out the source, and the gate contact hole extends through the second dielectric layer and reaches the gate polysilicon in the second trench to lead out the gate.

[0020] The source metal layer is arranged above the second dielectric layer and is in conductive connection with the metal in the source contact hole, and the gate metal layer is arranged above the second dielectric layer and is in conductive connection with the metal in the gate contact hole.

[0021] Compared with the prior art, by arranging a well region between the plurality of first trenches, arranging a first implantation region in the well region, and arranging a plurality of second implantation regions below part of the well region, a MOSFET device with a wider safe operating area can be realized, appropriate threshold voltage values can be obtained, the overcurrent capacity of SOA can be improved by nearly 2-3 times, and the thermal stability can be simultaneously reduced. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0023] Figure 1 is a structural diagram corresponding to steps S1 and S2 provided by the embodiment of the application;

[0024] Figure 2 is a structural diagram corresponding to step S3 provided by the embodiment of the application;

[0025] Figure 3 is a structural diagram corresponding to step S4 provided by the embodiment of the application;

[0026] Figure 4 is a structural diagram corresponding to step S5 provided by the embodiment of the application;

[0027] Figure 5 is a structural diagram corresponding to steps S6 and S7 provided by the embodiment of the application;

[0028] Figure 6 is a structural diagram corresponding to step S8 provided by the embodiment of the application;

[0029] Figure 7 is a structural diagram corresponding to step S9 provided by the embodiment of the application;

[0030] Figure 8 is a comparison diagram of transfer characteristics of a sample of a narrow SOA and a sample of a wide SOA provided by the embodiment of the application;

[0031] Figure 9 is a comparison diagram of DVDS data of a sample of a narrow SOA and a sample of a wide SOA provided by the embodiment of the application.

[0032] Figure 10 is a comparison diagram of DVDS data of a sample of a narrow SOA and a sample of a wide SOA provided by the embodiment of the application. DETAILED DESCRIPTION

[0033] In the following well-known elements of the art will be described with reference to the accompanying drawings and illustrations, in a clear and complete manner, in order to have a better understanding of the present application. Obviously, the described embodiments are only a part of the present application, and not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present application.

[0034] In a first aspect, the embodiments of the present application provide a power MOSFET wide SOA structure preparation process, comprising:

[0035] Step S1, etching a plurality of first grooves 3 and second grooves 4 in an epitaxial layer 2, wherein the epitaxial layer 2 is arranged on a substrate 1;

[0036] Step S2, sequentially arranging a gate polysilicon 6, a first dielectric layer 7 and a source polysilicon 5 from top to bottom in the first grooves 3 and the second grooves 4, respectively;

[0037] It should be noted that, Figure 1 The structure diagram corresponding to steps S1 and S2 is shown, and steps S1 and S2 are both process preparations well known to those skilled in the art, which will not be described here. Since the present application is a power MOSFET chip, the gate polysilicon 6, the first dielectric layer 7 and the source polysilicon 5 are sequentially deposited from top to bottom in the first grooves 3 and the second grooves 4.

[0038] Step S3, forming a well region 8 in the epitaxial layer 2 in the region where the first grooves 3 and the second grooves 4 are located;

[0039] It should be noted that, as Figure 2 In order to prepare the PN junction of the source region, it is necessary to first form a well region 8 in the epitaxial layer 2 in the region where the first grooves 3 and the second grooves 4 are located, wherein the well region 8 is formed by ion implantation, which is a well-known method to those skilled in the art, which will not be described here. In the embodiments of the present application, the implantation energy of the well region 8 is 120-160 Kev, and the implantation dose is 3e12-6e12.

[0040] Step S4, forming a first implantation region 9 in the well region 8 in the epitaxial layer 2 in the region where the first grooves 3 are located;

[0041] It should be noted that, as Figure 3 As shown in the figure, this step only forms a first implantation region 9 in the well region 8 in the epitaxial layer 2 in the region where the first grooves 3 are located, which is mainly to form the PN junction of the source. In the embodiments of the present application, the implantation energy of the first implantation region 9 is 50-70 Kev, and the implantation dose is 3e15-6e15.

[0042] Step S5, forming a second implantation region 10 below part of the well region 8 in the region where the first grooves 3 are located;

[0043] It should be noted that, as Figure 4As shown, for the MOSFET device with wider safe operating area of the gate, by forming the second implantation region 10 under the well region 8 in the area where the first trench 3 is located, the appropriate threshold voltage can be obtained, while the over-current capacity of the SOA can be improved by nearly 2-3 times, and the thermal stability can be reduced simultaneously. In the embodiment of the present application, the implantation energy of the second implantation region 10 is 90-110 Kev, and the implantation dose is 8e12-3e13.

[0044] Preferably, the second implantation region 10 is not arranged under the source contact hole 12 adjacent to the gate lead-out area.

[0045] Step S6, forming a second dielectric layer 11 on the surface of the epitaxial layer 2;

[0046] Step S7, arranging a source contact hole 12 and a gate contact hole 13 in the second dielectric layer 11, the source contact hole 12 extends to the well region 8 in the area where the first trench 3 is located through the second dielectric layer 11 and the first implantation region 9 in sequence so as to lead out the source, and the gate contact hole 13 extends to the gate polysilicon in the second trench 4 through the second dielectric layer 11 so as to lead out the gate;

[0047] It should be noted that, as Figure 5 shown, the second dielectric layer 11 is mainly arranged to play an insulating role, in addition, the source and the gate can be led out by arranging the source contact hole 12 and the gate contact hole 13.

[0048] Step S8, depositing metal in the source contact hole 12 and the gate contact hole 13, and forming a source metal layer 14 and a gate metal layer 15 arranged at intervals on the surface of the second dielectric layer 11;

[0049] It should be noted that, as Figure 6 shown, the source metal layer 14 and the gate metal layer 15 need to be separated.

[0050] Step S9, arranging a drain metal layer 16 on the side of the substrate 1 away from the epitaxial layer 2 so as to lead out the drain.

[0051] It should be noted that, as Figure 7 shown, the metal is arranged on the lower surface of the epitaxial layer 2 so as to form a metal drain.

[0052] The second aspect, as Figure 7 shown, the MOSFET chip provided by the embodiment of the present application is prepared by the process of any one of the first aspect, and the structure comprises: a MOSFET body;

[0053] The MOSFET body includes a plurality of spaced first trenches 3 and second trenches 4. The upper surface of the MOSFET body corresponding to the first trench 3 is provided with a second dielectric layer 11 and a source lead-out region. The upper surface of the MOSFET body corresponding to the second trench 4 is provided with a second dielectric layer 11 and a gate lead-out region.

[0054] The source lead-out region includes a source metal layer 14 and a source contact hole 12;

[0055] The gate lead-out region includes a gate metal layer 15 and a gate contact hole 13;

[0056] The source metal layer 14 and the gate metal layer 15 are spaced apart.

[0057] A well region 8 is provided between multiple first trenches 3, and a first injection region 9 is provided in the well region 8. Multiple second injection regions 10 are correspondingly provided below some of the well regions 8.

[0058] The source contact hole 12 passes through the second dielectric layer 11 and the first injection region 9 in sequence, extending to the well region 8 in the area where the first trench 3 is located, so as to bring out the source. The gate contact hole 13 passes through the second dielectric layer 11 and extends to the gate polysilicon in the second trench 4 so as to bring out the gate.

[0059] The source metal layer 14 is disposed above the second dielectric layer 11 and is electrically connected to the metal in the source contact hole 12, and the gate metal layer 15 is disposed above the second dielectric layer 11 and is electrically connected to the metal in the gate contact hole 13.

[0060] like Figure 8 As shown, Figure 8 By comparing the actual test transfer characteristic curves of non-bandwidth SOA samples and wide SOA samples, the difference between traditional and optimized processes can be seen. By optimizing the design and process to reduce the positive temperature coefficient of Id (saturation region), the Id current will decrease with temperature change, thereby reducing thermal instability and improving SOA capability.

[0061] like Figure 9 As shown, Figure 9 A comparison of actual DVDS test data for wide SOA and non-wide SOA samples shows that the wide SOA sample exhibits better overall convergence and thermal stability. DVDS is a test to detect the ability of a device to dissipate internal heat (junction temperature TJ).

[0062] like Figure 10 As shown, Figure 10 To compare the SOA diagrams of wide SOA samples and non-wide SOA samples, under the same pulse width test conditions, the wide SOA sample has a wider safe operating area than the non-wide SOA sample.

[0063] Compared with the prior art, the application can realize the MOSFET device with a wider safe working area, obtain a proper threshold voltage value, improve the overcurrent capacity of SOA by nearly 2-3 times, and simultaneously reduce the thermal stability by setting the trap region between the plurality of first grooves 3, setting the first injection region in the trap region, and correspondingly setting the plurality of second injection regions below part of the trap region.

[0064] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, and not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A process for fabricating a power MOSFET wide SOA structure, comprising: Comprising: etching a plurality of first and second trenches in an epitaxial layer, the epitaxial layer being disposed on a substrate; sequentially disposing a source polysilicon, a first dielectric layer and a gate polysilicon in the first and second trenches from top to bottom respectively; forming a well region in the epitaxial layer in the region where the first and second trenches are located; forming a first implantation region in the well region in the region where the first trench is located; forming a second implantation region below part of the well region in the region where the first trench is located; forming a second dielectric layer on the surface of the epitaxial layer; disposing a source contact hole and a gate contact hole in the second dielectric layer, the source contact hole sequentially extending through the second dielectric layer, the first implantation region to the well region in the region where the first trench is located so as to lead out the source, the gate contact hole extending through the second dielectric layer and extending to the gate polysilicon in the second trench so as to lead out the gate; depositing metal in the source contact hole and the gate contact hole and forming a source metal layer and a gate metal layer arranged at intervals on the surface of the second dielectric layer; disposing a drain metal layer on the side of the substrate away from the epitaxial layer so as to lead out the drain.

2. The process for fabricating a power MOSFET wide SOA structure of claim 1, wherein, No second implantation region is disposed below the source contact hole adjacent to the gate lead-out region.

3. The process for fabricating a power MOSFET wide SOA structure of claim 1, wherein, The implantation energy of the first implantation region is 50-70 Kev and the implantation dose is 3e15-6e15.

4. The process for fabricating a power MOSFET wide SOA structure of claim 1, wherein, The implantation energy of the second implantation region is 90-110 Kev and the implantation dose is 8e12-3e13.

5. The process for fabricating a power MOSFET wide SOA structure of claim 1, wherein, The implantation energy of the well region is 120-160 Kev and the implantation dose is 3e12-6e12.

6. A power MOSFET chip characterized by, Prepared by the process of any one of claims 1 to 5, the structure comprising: a MOSFET body; The MOSFET body comprises a plurality of first and second trenches arranged at intervals, and the upper surface of the MOSFET body corresponding to the first trench is provided with a second dielectric layer, a source lead-out region, and the upper surface of the MOSFET body corresponding to the second trench is provided with a second dielectric layer, a gate lead-out region; The source lead-out region comprises a source metal layer and a source contact hole; The gate lead-out region comprises a gate metal layer and a gate contact hole; The source metal layer and the gate metal layer are arranged at intervals; A well region is disposed between a plurality of the first trenches, and a first implantation region is disposed in the well region, and a plurality of second implantation regions are correspondingly disposed below part of the well region; The source contact hole sequentially extends through the second dielectric layer, the first implantation region to the well region in the region where the first trench is located so as to lead out the source, and the gate contact hole extends through the second dielectric layer and extends to the gate polysilicon in the second trench so as to lead out the gate; The source metal layer is disposed above the second dielectric layer and is in conductive connection with the metal in the source contact hole, and the gate metal layer is disposed above the second dielectric layer and is in conductive connection with the metal in the gate contact hole.

7. A power MOSFET chip as defined in claim 6, wherein, A plurality of the second implantation regions are arranged adjacent to each other.

8. A power MOSFET chip as defined in claim 6, wherein, No second implantation region is disposed below the source contact hole adjacent to the gate lead-out region.

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