Distributed multi-site data synchronous acquisition method and system based on white rabbit technology

Abstract

The invention provides a distributed multi-site data synchronous acquisition method and system based on a white rabbit technology, and relates to the field of radar data acquisition, and the method comprises the steps: carrying out the data interaction between a WR switch and a WR node through an optical fiber based on the white rabbit WR technology, so as to enable the WR node to output two paths of coherent 10MHz signals and PPS signals; the PPS signal is sent to a data acquisition board card as a reference clock, and the 10MHz signal is sent to a clock power division circuit to divide a first path of target signal and a second path of target signal; the first path of target signal is sent to the FPGA as a system operation clock, and the second path of target signal is sent to the clock generation chip circuit to generate an ADC sampling clock and a system reference clock. According to the invention, time and frequency distribution is carried out by using a white rabbit technology, instructions are synchronously acquired through PPS, distributed multi-site data synthesis is realized, the target detection capability and the detection distance are increased, and the method is convenient to realize, high in reliability and excellent in performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radar data collection, in particular to a distributed multi-site data synchronous collection method and system based on White Rabbit technology. BACKGROUND

[0002] White Rabbit (WR) clock synchronization technology is a distributed synchronization time service technology developed by combining synchronous Ethernet (Sync-E), precision timing protocol (IEEE1588v2) and digital phase measurement technology, which can realize sub-nanosecond precision clock distribution among thousands of kilometers of multiple nodes. This technology is compatible with standard Ethernet protocol, does not occupy additional network bandwidth, is directly integrated with the data link, has a simple structure and low cost. This method can be effectively applied to long-distance multi-node high-precision time service occasions, and is also widely used in distributed network measurement and control, time unification system, industrial automation control, distributed base station and remote radio system, power grid synchronization, adaptive array antenna, distributed multi-base radar, indoor positioning and other occasions.

[0003] Due to the multi-angle and multi-path detection mode of the distributed radar, compared with the traditional single-station radar, it has spatial diversity gain and detection performance advantage, that is, it only needs smaller transmitting power under the same detection range, has low interception characteristics, or has larger detection range under the same transmitting power. Multi-angle detection can obtain target high-scattering coefficient echo with a larger probability, corresponding to better observation of small target performance.

[0004] Although the distributed radar has many advantages, due to the distribution of multiple sites at different locations, there are many technical difficulties in engineering. Compared with the single-base radar, the time, space and phase synchronization between each unit radar is the first technical difficulty of the distributed full-phase radar. Since the distributed full-phase radar requires that the signals of each unit radar need to meet the time and phase correlation, the synchronization accuracy of time and phase is very high. At present, the time and frequency synchronization method is generally transmitted by optical fiber. Affected by environmental factors, the transmission distance is short, the time accuracy is generally in nanoseconds, the detection target capability is weak, and the detection distance is low. SUMMARY

[0005] In view of the deficiencies of the prior art, the present application provides a distributed multi-site data synchronous collection method and system based on White Rabbit technology, which solves the problems of short transmission distance, low time accuracy, weak detection target capability and the like faced by the current distributed radar during data collection.

[0006] To achieve the above purpose, the present application realizes the following technical solutions:

[0007] In a first aspect, the embodiments of the present application provide a distributed multi-site data synchronous acquisition method based on white rabbit technology, which comprises the following steps: acquiring a GPS / reference clock source, a WR switch, a plurality of WR nodes, an optical fiber line, and a plurality of data acquisition board cards; based on the white rabbit WR technology, data interaction is performed between the WR switch and the WR nodes through the optical fiber, so that the WR nodes output two-way phase-related 10MHz signals and PPS signals; the PPS signals output by the WR nodes are sent to the data acquisition board cards as reference clocks, and the 10MHz signals output by the WR nodes are sent to the clock power division circuit of the data acquisition board cards to divide out a first target signal and a second target signal; the first target signal is sent to the FPGA on the data acquisition board card as a system running clock, and the second target signal is sent to the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and phase correlation; based on the data acquisition board card, an external control command is received through a data interface, data acquisition is started, data of a plurality of data acquisition board cards is fused and processed, and the data is output through the data interface.

[0008] According to the first aspect of the embodiments of the present application, the GPS / reference clock source is used to provide a UTC time code and two-way clock signals: the two-way clock signals include 10MHz signals and PPS signals; the WR switch adopts high-precision distributed timing technology based on optical fiber Ethernet technology, and can perform sub-nanosecond precision time synchronization between ten thousand nodes in a spatial distance of less than 10km, so as to be applied to long-distance multi-node high-precision timing occasions.

[0009] According to the first aspect of the embodiments of the present application, the WR switch synchronizes with the upper clock as a slave clock, and synchronizes with the lower clock as a master clock to complete the cross-border synchronization of the clock; wherein the clock synchronization process based on the WR switch includes frequency synchronization and time synchronization representing absolute time information.

[0010] According to the first aspect of the embodiments of the present application, the 10MHz signals and PPS signals output by each WR node are respectively the same in frequency and fixed in phase with the 10MHz signals and PPS signals input by the WR switch; the number of data acquisition board cards is the same as the number of WR nodes, and the data acquisition board card comprises a clock power division circuit, an FPGA, a clock generation chip circuit, an ADC, and a data interface circuit.

[0011] According to the first aspect of the embodiment of the present application, the clock power division circuit is used for dividing the input clock to generate multiple clocks, the output clock of the clock power division circuit is the same as the input signal in frequency and phase, and has low time delay and low clock jitter characteristics; the clock generation chip circuit is used for generating an ADC sampling clock and a system reference clock, the system reference clock is used as a reference clock of the ADC and the FPGA to realize synchronization of ADC data acquisition and FPGA reception; the clock generation chip circuit configures the working mode and the output frequency through a configuration interface to realize multiple sampling clocks and working modes; the ADC is a wideband analog-to-digital converter based on the JESD204B protocol to directly sample the input high-frequency signal; the FPGA is a main control chip of the data acquisition board card, realizes system data acquisition and reception control through programming, configures the ADC and the clock generation chip circuit, and realizes command reception, synchronization and data packaging output.

[0012] According to the first aspect of the embodiment of the present application, the foregoing data acquisition board card receives an external control command through a data interface, starts data acquisition, and fuses and outputs the data of multiple data acquisition board cards through the data interface, which can specifically include: sending the system reference clock into the FPGA as a reference, and sending the PPS signal as a time reference; when the acquisition control command is received, the acquisition of multiple data acquisition board cards is started when the next pulse of the PPS signal arrives, so as to ensure that multiple data acquisition board cards perform data acquisition at the same time.

[0013] According to the first aspect of the embodiment of the present application, the data interface realizes a communication rate greater than 10 Gb / s through an optical fiber, the data collected based on the data interface is transmitted to a system host computer based on a communication protocol through the optical fiber, and data reception and processing are realized; the WR node and the data acquisition board card are located at different site positions, the distribution distance between some of the site positions is greater than 10 km, multiple site positions can perform synchronous acquisition and reception of a target signal on the target signal, and fusion processing of multi-site data is performed.

[0014] The second aspect, the embodiment of the present application provides a distributed multi-site data synchronous acquisition system based on white rabbit technology, the distributed multi-site data synchronous acquisition system based on white rabbit technology includes an acquisition module, a data interaction module, a first feeding module, a second feeding module and an acquisition module.

[0015] Specifically, the acquisition module is configured to acquire a GPS / reference clock source, a WR switch, a plurality of WR nodes, a fiber line, and a plurality of data acquisition board cards; the data interaction module is configured to interact data between the WR switch and the WR nodes through the fiber based on the white rabbit WR technology, so that the WR nodes output two-phase 10MHz signals and PPS signals; the first feeding module is configured to feed the PPS signals output by the WR nodes into the data acquisition board cards as reference clocks, and feed the 10MHz signals output by the WR nodes into a clock power division circuit of the data acquisition board cards to divide out a first target signal and a second target signal; the second feeding module is configured to feed the first target signal into an FPGA on the data acquisition board card as a system running clock, and feed the second target signal into a clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and in phase; and the acquisition module is configured to receive external control commands through a data interface based on the data acquisition board cards, start data acquisition, fuse the data of the plurality of data acquisition board cards, and output the fused data through the data interface.

[0016] In a third aspect, an electronic device is provided, which includes a processor, a memory, and a program stored in the memory and capable of running on the processor, and the program, when executed by the processor, implements the white rabbit technology-based distributed multi-site data synchronous acquisition method of the first aspect.

[0017] In a fourth aspect, a computer readable storage medium is provided, which stores a program or instructions, and the program or instructions, when executed by a processor, implement the white rabbit technology-based distributed multi-site data synchronous acquisition method of the first aspect.

[0018] The present application provides a white rabbit technology-based distributed multi-site data synchronous acquisition method and system. Compared with the prior art, the present application has the following beneficial effects:

[0019] The present application uses a wired communication method, and comprehensively uses a white rabbit technology, a synchronous Ethernet, a precise timing protocol, and a digital phase measurement technology, so that time and frequency can be distributed among multiple sites in a technical manner, sub-nanosecond time synchronization can be achieved, and better stability and reliability are achieved. The frequencies of the working clocks of the data acquisition board cards of the multiple sites are the same, and the phases are fixed. Through FPGA software design, the data acquisition of the multiple sites at the same target time can be achieved, and data synthesis of the target signal can be achieved. The present application distributes time and frequency by using the white rabbit technology, and achieves distributed multi-site data synthesis through a PPS synchronous acquisition instruction, so that the detection capability and the detection distance of a detection target are increased, and the present application is convenient, reliable, and superior in performance. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings belong to the protection scope of the present application.

[0021] Figure 1 is a flowchart of a distributed multi-site data synchronous acquisition method based on white rabbit technology provided by the embodiments of the present application;

[0022] Figure 2 is a structural schematic diagram of a distributed multi-site data synchronous acquisition system based on white rabbit technology provided by the embodiments of the present application;

[0023] Figure 3 is an exemplary block diagram of a distributed multi-site data synchronous acquisition system based on white rabbit technology provided by the embodiments of the present application;

[0024] Figure 4 is an architecture diagram of a digital acquisition board card provided by the embodiments of the present application;

[0025] Figure 5 is a clock power division circuit diagram provided by the embodiments of the present application;

[0026] Figure 6 is a clock generation chip circuit diagram provided by the embodiments of the present application;

[0027] Figure 7 is an ADC circuit diagram provided by the embodiments of the present application;

[0028] Figure 8 is an optical fiber transceiver circuit diagram provided by the embodiments of the present application;

[0029] Figure 9 is a structural schematic diagram of an electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0030] In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application are described clearly and completely. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0031] It is to be noted that, in this document, the terms such as first and second, etc., are used merely to distinguish one entity or action from another, and do not necessarily require or imply any such actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... " does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0032] The embodiment of the present application provides a distributed multi-station data synchronization acquisition method and system based on a white rabbit technology, and solves the problems of short transmission distance, low time precision and weak target detection capability of a current distributed radar during data acquisition.

[0033] The technical solution in the embodiment of the present application is used for solving the above technical problem, and the general idea is as follows:

[0034] White rabbit (WR) clock synchronization technology is a distributed synchronization time service technology developed by combining synchronous Ethernet (Sync-E), precision timing protocol (IEEE1588v2) and digital phase measurement technology, and can realize sub-nanosecond precision clock distribution in a range of thousands of meters. The technology is compatible with standard Ethernet protocol, does not occupy additional network bandwidth, is directly integrated with a data link, has a simple structure and low cost. The method can be effectively applied to long-distance multi-node high-precision time service occasions, and is also widely applied to distributed network measurement and control, time unification systems, industrial automation control, distributed base stations and remote radio frequency systems, power grid synchronization, adaptive array antennas, distributed multi-base radar, indoor positioning and various occasions.

[0035] Due to the multi-angle and multi-path detection mode of the distributed radar, compared with the traditional single-station radar, the distributed radar has spatial diversity gain and detection performance advantages, that is, only needs smaller transmitting power under the same detection range, has low interception characteristics, or has a larger detection range under the same transmitting power. Multi-angle detection can obtain target high-scattering coefficient echoes with a larger probability, and corresponds to better observation of small target performance.

[0036] The distributed radar has the following advantages: (1) The distributed radar can more effectively receive electromagnetic scattering information of a target, improve sensitivity of the system, and thus can realize detection of a target at a farther distance. (2) The distributed radar can receive electromagnetic scattering information of a target that cannot be received by a single radar, and thus has more advantages in detecting a stealth target. (3) If a transmit-receive separation system structure is used, the receiver of the distributed radar is in a passive state, and electronic warfare means cannot determine the position of the receiver, and thus the survivability of the radar is effectively improved. (4) The distributed radar has high reliability, and even if a part of the transmitters and receivers of the radar system is damaged, the entire radar system will not be completely paralyzed. (5) Because the spatial distance of each radar unit is far apart, the distributed radar has a very long baseline, and thus the positioning accuracy of the target can be effectively improved. (6) The distributed radar can receive scattering information of the target at different angles, and thus helps to improve the target recognition capability of the radar system.

[0037] Although the distributed radar has many advantages, because multiple stations are distributed at different positions, there are many technical difficulties in engineering. Compared with a single radar, the most difficult technical problem of the distributed full-phase radar is synchronization of time, space and phase among the radar units. Because the distributed full-phase radar requires that the signals of each radar unit meet the phase correlation of time and phase, the synchronization accuracy of time and phase is very high. According to the transmission mode of the signal, the existing synchronization method can be divided into two categories: radio signal method and wired communication method. The current synchronization method using optical fiber to transmit time frequency is affected by environmental factors, the transmission distance is short, the time accuracy is generally in nanoseconds, the target detection capability is weak, and the detection distance is low.

[0038] In order to better understand the above technical solutions, the above technical solutions will be described in detail in combination with the drawings of the specification and the specific embodiments.

[0039] First, a distributed multi-station data synchronous acquisition method based on a white rabbit technology provided by the embodiments of the present application will be introduced.

[0040] A flowchart of the distributed multi-station data synchronous acquisition method based on the white rabbit technology provided by the embodiments of the present application is shown as shown in the figure, and the method can include the following steps S110-S150. Figure 1

[0041] S110, acquiring a GPS / reference clock source, a WR switch, a plurality of WR nodes, an optical fiber line, and a plurality of data acquisition board cards;

[0042] ​S120, based on the white rabbit WR technology, data interaction between the WR switch and the WR node is carried out through the optical fiber, so that the WR node outputs two-way 10MHz signals and PPS signals in phase;

[0043] S130, the PPS signal output by the WR node is sent to the data acquisition board card as a reference clock, and the 10MHz signal output by the WR node is sent to the clock power division circuit of the data acquisition board card to divide the first target signal and the second target signal;

[0044] S140, the first target signal is sent to the FPGA on the data acquisition board card as a system running clock, and the second target signal is sent to the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and in phase;

[0045] S150, based on the data acquisition board card, an external control command is received through a data interface, data acquisition is started, data of multiple data acquisition board cards is fused and output through the data interface.

[0046] The above is a specific implementation of a distributed multi-site data synchronous acquisition method based on white rabbit technology provided by the embodiment of the application. It can be understood that the application uses a wired communication method, and based on the white rabbit technology, the time, frequency and phase of multiple sites can be accurately synchronized within a range of 10km. The white rabbit technology integrates synchronous Ethernet, precise timing protocol and digital phase measurement technology, and can technically distribute time and frequency among multiple sites, achieve sub-nanosecond time synchronization, have better stability and reliability, and can be further upgraded on this basis to obtain higher time synchronization reference.

[0047] Further, the frequencies of the data acquisition board cards of the multiple sites are the same, and the phases are fixed. Through FPGA software design, data acquisition of the same target at the same time by multiple sites can be realized, and data synthesis of the target signal can be realized. The clock frequencies between sites are accurately synchronized with the main node clock frequency (±10 -11 long-term accuracy), a large-range, multi-node clock distribution and synchronization mechanism is realized, the time synchronization accuracy can reach sub-nanosecond level, and the synchronous acquisition of multiple sites to the same target signal can be well realized, and multi-site data fusion is realized.

[0048] Based on this, the application uses the white rabbit technology to distribute time and frequency, realizes distributed multi-site data synthesis through PPS synchronous acquisition instructions, increases the detection target capability and detection distance, is convenient, has high reliability and superior performance.

[0049] In some embodiments, the GPS / reference clock source is used to provide a UTC time code and two-way clock signals: the two-way clock signals include a 10MHz signal and a PPS signal; the WR switch adopts a high-precision distributed time service technology based on fiber-optic Ethernet technology, and is capable of sub-nanosecond precision time synchronization among ten thousand nodes at a spatial distance of less than 10 km, to be applied to long-distance multi-node high-precision time service occasions.

[0050] In the embodiments of the present application, it can be understood that, based on the WR technology, the GPS / reference clock source, the WR switch, the WR node, the fiber link, and the data acquisition board card, the multi-site data synchronization acquisition and data fusion are realized by sending a synchronization acquisition instruction to each site. The GPS / reference clock source includes a Beidou GPS, a high-stability atomic clock, or a high-stability quartz crystal oscillator, outputs a high-stability clock signal, and outputs a time code and two-way clock signals (a 10MHz signal and a PPS signal) to the WR switch through a fiber, as the main time and frequency reference of the whole system.

[0051] In some embodiments, the WR switch synchronizes with the upper clock as a slave clock, and synchronizes with the lower clock as a master clock to complete the cross-border synchronization of the clock; wherein the clock synchronization process based on the WR switch includes frequency synchronization and time synchronization representing absolute time information.

[0052] In the embodiments of the present application, it can be understood that the WR switch is added with WR function support on the basis of a common switch, and provides QoS support, link redundancy, and fast switching and other characteristics, to meet the high real-time requirements of the clock and control system. The WR switch has multiple SFP fiber ports, which can be configured as uplink ports or downlink ports at will, and synchronizes with the lower WR slave node or switch through a fiber link.

[0053] In some embodiments, the 10MHz signal and the PPS signal output by each WR node are respectively the same in frequency and fixed in phase with the 10MHz signal and the PPS signal input by the WR switch.

[0054] In the embodiments of the present application, it can be understood that the WR node has two SFP fiber ports, can receive data of the upper WR switch, phase-locks the received clock, and can also communicate with other WR nodes through the SFP, to perform frequency and time synchronization. The WR node outputs two-way clock signals: 10MHz and PPS, and the 10MHz and PPS signals between multiple WR nodes are the same in frequency and phase, and are time-synchronized with the system 10MHz and PPS.

[0055] In some embodiments, the number of data acquisition board cards is the same as the number of WR nodes, and the data acquisition board card comprises a clock distribution circuit, an FPGA, a clock generation chip circuit, an ADC, and a data interface circuit.

[0056] The clock distribution circuit is used for distributing the input clock to generate multiple clocks, and the output clock of the clock distribution circuit is the same as the input signal in frequency and phase, and has low latency and low clock jitter characteristics.

[0057] The clock generation chip circuit is used for generating an ADC sampling clock and a system reference clock, and the system reference clock is used as a reference clock of the ADC and the FPGA to realize synchronization of ADC data acquisition and FPGA reception; the clock generation chip circuit configures the working mode and the output frequency through a configuration interface to realize multiple sampling clocks and working modes.

[0058] The ADC is a wideband analog-to-digital converter based on the JESD204B protocol to directly sample the input high-frequency signal.

[0059] The FPGA is a main control chip of the data acquisition board card, and realizes system data acquisition and reception control through programming, configures the ADC and the clock generation chip circuit, and realizes command reception, synchronization, and data packaging output.

[0060] In the embodiments of the present application, it can be understood that the data acquisition board card comprises an ADC, an FPGA, a clock distribution chip, a 100MHz high-stability crystal oscillator clock, a clock generation circuit, a power supply circuit, an SFP optical fiber interface, etc. The power supply circuit generates multiple voltages and is connected to each device and circuit on the data acquisition board card; the clock distribution circuit distributes the input 10MHz signal to generate two 10MHz signals, one of which is connected to the FPGA and the other of which is connected to the clock generation chip; the clock generation chip comprises two phase-locked loops (PLLs), the 100MHz high-stability crystal oscillator is connected to the clock input end of the clock generation chip, the first-stage PLL of the clock generation chip performs phase locking on the input 10MHz signal and the 100MHz high-stability clock, the second-stage PLL generates a 2.4GHz clock through frequency multiplication and phase locking, and then generates multiple ADC sampling clocks and system reference clocks through a frequency division circuit, the ADC sampling clock is connected to the sampling clock pin of the ADC chip, and the system reference clock is connected to the FPGA and the ADC; the data output end of the ADC is connected to the FPGA, the collected data is sent to the FPGA for data decoding through the JESD204B interface protocol. After the FPGA processes the ADC signal, the FPGA receives the synchronous acquisition instruction of the remote computer through the SFP optical fiber interface, sends the data of multiple data acquisition board cards to the remote host computer respectively, and the host computer performs data fusion processing, so as to realize the fusion processing function of multiple stations on the same target signal.

[0061] In one example, the foregoing data acquisition board card receives external control commands through the data interface, starts data acquisition, fuses the data of multiple data acquisition board cards, and outputs through the data interface, that is, the foregoing S150 can specifically include the following steps:

[0062] S210, sending the system reference clock into the FPGA as a reference, and taking the PPS signal as a time reference;

[0063] S220, when receiving the acquisition control command, starting the acquisition of multiple data acquisition board cards at the next pulse of the PPS signal to ensure that multiple data acquisition board cards perform data acquisition at the same time.

[0064] In one example, the data interface realizes a communication rate greater than 10 Gb / s through an optical fiber, and the data acquired based on the data interface is transmitted to the system host computer based on a communication protocol through the optical fiber to realize data receiving and processing.

[0065] The WR node and the data acquisition board card are located at different site locations, and the distribution distance between some sites is greater than 10 km. Multiple sites can perform synchronous acquisition and reception of target signals on the same target signal and perform fusion processing of multi-site data.

[0066] In some embodiments, the present application provides a distributed multi-site data synchronous acquisition system 300 based on white rabbit technology, as shown in Figure 2 The distributed multi-site data synchronous acquisition system 300 based on white rabbit technology can include the following modules:

[0067] The acquisition module 310 is configured to acquire a GPS / reference clock source, a WR switch, multiple WR nodes, an optical fiber line, and multiple data acquisition board cards.

[0068] The data interaction module 320 is configured to interact data between the WR switch and the WR node based on white rabbit WR technology through the optical fiber, so that the WR node outputs two-way 10 MHz signals and PPS signals.

[0069] The first feeding module 330 is configured to feed the PPS signal output by the WR node into the data acquisition board card as a reference clock, and feed the 10 MHz signal output by the WR node into the clock power division circuit of the data acquisition board card to divide out a first target signal and a second target signal.

[0070] The second feeding module 340 is configured to feed the first target signal into the FPGA on the data acquisition board card as a system running clock, and feed the second target signal into the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and phase.

[0071] The acquisition module 350 is configured to receive external control commands through a data interface based on a data acquisition board card, start data acquisition, fuse data of a plurality of data acquisition board cards, and output the fused data through the data interface.

[0072] According to an embodiment of the present application, any of the modules of the acquisition module 310, the data interaction module 320, the first feeding module 330, the second feeding module 340, and the acquisition module 350 can be combined in one module, or any of the modules can be split into a plurality of modules. Alternatively, at least part of the functions of one or more of the modules can be combined with at least part of the functions of other modules, and implemented in one module.

[0073] Figure 2 Each module in the system has the function of implementing each step in the foregoing distributed multi-site data synchronization acquisition method based on the white rabbit technology, and can achieve the corresponding technical effects. For brevity, the foregoing will not be described again.

[0074] It should be further noted that please refer to Figure 3 , there are n WR nodes, and there are n data acquisition board cards. The present application includes two parts, system clock generation and distribution, and data acquisition.

[0075] Clock generation and distribution are mainly based on the white rabbit technology, and 10MHz, PPS, and time code of the GPS / reference clock source are distributed to a plurality of white rabbit nodes through the white rabbit switch. Each white rabbit node corresponds to a data acquisition board card. Since the white rabbit technology can realize distribution of time and frequency among a plurality of sites, the data acquisition board cards of each site can obtain frequency and time synchronized 10MHz and PPS signals as the basic clock of the acquisition board card.

[0076] The method technically ensures that a plurality of distributed sites can realize synchronous acquisition and data fusion. In the present application, the WR technology is adopted, and with the mature commercial COTS components, the WR-based application or modification can be very conveniently and quickly realized.

[0077] Exemplarily, the WR node has a plurality of implementation forms: a board mode, a sub-board mode, and an IP core mode, which can be selected according to specific needs. The WR switch and the WR node are both realized based on the WR technology, are connected to each other through a fiber link, realize time and frequency synchronization of the WR switch and the WR node through data interaction.

[0078] The working process of the system is as follows: after the WR switch receives the reference clock (10MHz, PPS and time code) signal, the information is sent to the WR node through the optical fiber, so that the local clock of the WR node is synchronized to the clock frequency of the WR switch, and two clock signals (10MHz and PPS) output by the WR node enter the data acquisition board card, as shown in the figure. Figure 4 The data acquisition board card divides the 10MHz signal into two parts, one of which enters the FPGA, and the other enters the clock generation chip circuit, and is phase-locked with the 100M clock on the board, and the sampling clock and the system reference clock required by the ADC are generated after frequency multiplication, phase locking and frequency division in the chip, and the input RF signal is sent to the FPGA after AD conversion under the action of the sampling clock. Since the ADC sampling clock and the system reference clock are both phase-locked with the input 10MHz signal, the sampling clock and the reference clock of each site are also phase-locked signals, and the synchronous acquisition command is output through the optical fiber interface under the action of the PPS, so that the synchronous acquisition of multiple sites to the same RF signal can be realized, the data synthesis can be carried out, and the distributed multi-site data acquisition and fusion can be realized.

[0079] The application will be further described below. Figures 5-8 As shown in the figure, Figure 5 The 10MHz signal sent by the WR node is connected to XS1, then coupled to the CLK0 pin of the clock power division chip D10 through the capacitor C424, and two 10MHz differential signals of the same frequency and phase are divided after D10: CLK10M_A_P / N and CLK10M_B_P / N. Capacitors C348-C356, C639-C640, C662-C667, C674-C675 provide filtering and decoupling for the power supply.

[0080] As shown in the figure, Figure 6 One of the 10MHz clocks divided by D10 enters the REF_A port, the REF_SEL port is a selection port, which can select whether the input reference clock of the clock generation circuit is REF_A or REF_B, the VCXO_IN port is connected to the 100MHz high-stability clock, the 10MHz signal sent by REF_A is phase-locked with the 100MHz high-stability clock through PLL1, and then sent to PLL2 for frequency multiplication and phase locking, and then a 2.4GHz clock is output. After two-stage phase-locked loop, frequency division, time delay adjustment and driving are carried out through the clock distribution module, and then the output is obtained. The clock generation chip circuit has multiple outputs, and the generated signals include the ADC sampling clock CLK_P / N and the reference clock SYSREF_P / N. The SYSREF_REQ signal is used for phase synchronization of the multiple output signals of the clock generation chip circuit. After the PPS signal of the WR node enters the FPGA, it is synchronized with the synchronous acquisition command and then output, so that the data acquisition board cards of multiple sites can be synchronized and acquired.

[0081] As shown in Figure 7 The RF signal enters XS1, is coupled by capacitor C17, is sent to the balun T5, is converted from an analog single-ended signal to a differential signal, is sent to the filter composed of capacitors C18, C19, C20, resistors R41, R42, R43, R44, R45, R46 for filtering, and then is sent to the analog differential input end 5 and 6 of D3 for analog-to-digital conversion under the action of the sampling clock CLK_P / N. The SYSREF_P / N pin of the ADC is used for data reference synchronization with the FPGA.

[0082] Figure 6 The reference clock SYSREF clock generated by the clock generation chip is sent to the FPGA and the ADC, the multi-channel AD data sent by the ADC is synchronized through the reference clock, and the data is processed after being sent to the FPGA. The FPGA configures the working mode of the FPGA through the SPI interface (SDIO, SCLK, CSB) of the ADC chip. Another RF signal is converted from a single-ended signal to a differential signal after passing through XS2 and then enters the ADC for sampling processing, and the sampling processing process is the same as the above principle.

[0083] The two RF signals of the same acquisition board card are collected by the ADC, and since the sampling clock is the same and the reference clock SYSREF is the same, the digital signals collected by the two channels are completely the same in time and phase for the same ADC. For different acquisition board cards of multiple sites, the sampling clock and the reference signal frequency and phase are also the same, so the digital signals of the multiple acquisition board cards can be synthesized to realize beam synthesis of the digital signals.

[0084] As shown in Figure 8 D11 is a fiber transceiver module, one end of which is connected to the GTX high-speed port of the FPGA, and the other end of which is connected to the remote host computer through an optical fiber. The fiber transceiver module adopts multi-channel transceiving, and the module adopts a single-mode working mode, which can meet the requirement of transmitting a longer distance. The FPGA receives the synchronous acquisition control command through the fiber module, and controls the sampling time of the ADC after being related to the PPS pulse, so as to obtain multi-channel AD data. After data processing in the FPGA, the data is sent out through the fiber transceiver module. The data of multiple sites is sent to the remote host computer through the optical fiber, and then is subjected to data fusion processing, so as to realize distributed site data acquisition and processing.

[0085] In some embodiments, the present application provides an electronic device, a structural schematic diagram of which is shown in Figure 9 .

[0086] The electronic device can include a processor 410 and a memory 420 storing computer program instructions.

[0087] In particular, the processor 410 can include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to perform one or more of the embodiments of the present application.

[0088] The memory 420 can include mass storage for data or instructions. As an example and not by way of limitation, the memory 420 can include a hard disk drive (HDD), a floppy disk drive, flash memory, an optical disc (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a tape drive, a USB drive, or a combination of two or more of these. Where appropriate, the memory 420 can include removable or non-removable (or fixed) media, where appropriate. Where appropriate, the memory 420 can be internal or external to the integrated gateway disaster recovery device. In particular embodiments, the memory 420 is non-volatile, solid-state memory.

[0089] The memory 420 can include read-only memory (ROM), random-access memory (RAM), a disc storage medium, an optical storage medium, a flash memory device, or electrical, optical, or other physically tangible storage device. Accordingly, in general, the memory 420 includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software that, when executed (e.g., by the one or more processors), is operable to perform the operations described above as being performed by any of the embodiments of the white rabbit technology-based distributed multi-site data synchronization acquisition method.

[0090] The processor 410 implements the white rabbit technology-based distributed multi-site data synchronization acquisition method of any of the embodiments described above by reading and executing computer program instructions stored in the memory 420.

[0091] In one example, the electronic device can further include a communication interface 430 and a bus 400. As shown, the processor 410, the memory 420, and the communication interface 430 are connected by the bus 400 and complete communication with each other. Figure 9

[0092] The communication interface 430 is mainly used to realize the communication between the modules, devices, units and / or equipment in the embodiments of the present application.

[0093] ​Bus 400 includes a hardware, software, or both that couples components of the online data traffic metering device to each other. As an example and not by way of limitation, the bus can include an accelerated graphics port (AGP) or other graphics bus, an enhanced industry standard architecture (EISA) bus, a front-side bus (FSB), a HyperTransport (HT) interconnect, an industry standard architecture (ISA) bus, an InfiniBand (IB) interconnect, a low pin count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a serial advanced technology attachment (SATA) bus, a video electronics standards board (VLB) bus, or another suitable bus or a combination of two or more of these. Where suitable, bus 400 can include one or more buses. Although this application describes and shows a particular bus, this application contemplates any suitable bus or interconnect.

[0094] In addition, in combination with the above-mentioned embodiment of the distributed multi-site data synchronization acquisition method based on the white rabbit technology, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium has computer program instructions stored thereon; the computer program instructions are executed by a processor to implement any one of the above-mentioned embodiments of the distributed multi-site data synchronization acquisition method based on the white rabbit technology.

[0095] It needs to be clear that the present application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above-mentioned embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after understanding the spirit of the present application.

[0096] The functional blocks shown in the above structural block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, etc. When implemented in software, the elements of the present application are program or code segments used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. The "machine-readable medium" can include any medium capable of storing or transmitting information. Examples of the machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segments can be downloaded via a computer network such as the Internet, an intranet, etc.

[0097] It is also noted that the examples mentioned in this application describe some methods or systems based on a series of steps or devices. However, the application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the examples, or in an order different from the examples, or several steps can be performed simultaneously.

[0098] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other processing device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other processing device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer program instructions can also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other processing device to operate in a particular manner, such that the computer readable medium having instructions stored therein comprises an article of manufacture including a computer program of instructions which implement the function / act specified in the flowchart and / or block diagram block or blocks.

[0099] The above examples are only used to illustrate the technical solutions of the present application, and not to limit it; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A distributed multi-site data synchronization and acquisition method based on White Rabbit technology, characterized in that, include: Acquire GPS / reference clock source, WR switch, multiple WR nodes, fiber optic lines, and multiple data acquisition boards; Based on the White Rabbit WR technology, data interaction is performed between the WR switch and the WR node via optical fiber, so that the WR node outputs two coherent 10MHz signals and PPS signals. The PPS signal output by the WR node is sent to the data acquisition board as a reference clock, and the 10MHz signal output by the WR node is sent to the clock power divider circuit of the data acquisition board to separate the first target signal and the second target signal. The first target signal is sent to the FPGA on the data acquisition board as the system operating clock, and the second target signal is sent to the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and phase. Based on the data acquisition board, external control commands are received through the data interface to start data acquisition, and data from multiple data acquisition boards are fused and processed and output through the data interface.

2. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The GPS / reference clock source is used to provide UTC timecode and two clock signals: the two clock signals include a 10MHz signal and a PPS signal; The WR switch adopts high-precision distributed time synchronization technology based on fiber optic Ethernet technology, and can perform sub-nanosecond time synchronization between tens of thousands of nodes in a spatial distance of less than 10km, so as to be applied to long-distance multi-node high-precision time synchronization occasions.

3. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The WR switch synchronizes with the upper-level clock as a slave clock and with the lower-level clock as a master clock to complete cross-domain clock synchronization. The clock synchronization process based on the WR switch includes frequency synchronization and time synchronization, which represents absolute time information.

4. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The 10MHz signal and PPS signal output by each WR node have the same frequency and fixed phase as the 10MHz signal and PPS signal input by the WR switch, respectively. The number of data acquisition boards is the same as the number of WR nodes. The data acquisition boards include a clock power divider circuit, an FPGA, a clock generation chip circuit, an ADC, and a data interface circuit.

5. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 4, characterized in that, The clock power divider circuit is used to distribute the input clock and generate multiple clocks. The output clock of the clock power divider circuit is the same as the input signal in frequency and phase, and has low latency and low clock jitter characteristics. The clock generation chip circuit is used to generate the ADC sampling clock and the system reference clock. The system reference clock serves as the reference clock for the ADC and the FPGA to achieve synchronization of ADC data acquisition and FPGA reception. The clock generation chip circuit can be configured with its operating mode and output frequency through a configuration interface to achieve multiple sampling clocks and operating modes. The ADC uses a wideband analog-to-digital converter based on the JESD204B protocol to directly sample the input high-frequency signal. The FPGA is the main control chip of the data acquisition board. It is programmed to realize the system data acquisition and reception control, configure the ADC and the clock generation chip circuit, and realize command reception, synchronization and data packet output.

6. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The process, based on the data acquisition board, receives external control commands through a data interface, initiates data acquisition, fuses data from multiple data acquisition boards, and outputs the data through the data interface, including: The system reference clock is fed into the FPGA as a reference, and the PPS signal is used as a time reference. Upon receiving the acquisition control command, when the next pulse of the PPS signal arrives, the acquisition of multiple data acquisition boards is initiated to ensure that the multiple data acquisition boards acquire data at the same time.

7. The distributed multi-site data synchronization acquisition method based on White Rabbit technology as described in claim 1, characterized in that, The data interface achieves a communication rate greater than 10Gb / s through optical fiber. Data collected based on the data interface is transmitted to the system host computer through optical fiber based on the communication protocol to realize data reception and processing. The WR node and the data acquisition board are located at different sites, and some of the sites are more than 10km apart. Multiple sites can synchronously acquire and receive the same target signal and perform multi-site data fusion processing.

8. A distributed multi-site data synchronization and acquisition system based on White Rabbit technology, characterized in that, include: The acquisition module is used to acquire GPS / reference clock sources, WR switches, multiple WR nodes, fiber optic lines, and multiple data acquisition boards; The data interaction module is used to perform data interaction between the WR switch and the WR node through optical fiber based on the White Rabbit WR technology, so that the WR node outputs two coherent 10MHz signals and PPS signals; The first input module is used to input the PPS signal output by the WR node into the data acquisition board as a reference clock, and to input the 10MHz signal output by the WR node into the clock power divider circuit of the data acquisition board to separate the first target signal and the second target signal. The second input module is used to input the first target signal into the FPGA on the data acquisition board as the system operating clock, and to input the second target signal into the clock generation chip circuit to generate an ADC sampling clock and a system reference clock with the same frequency and phase. The acquisition module is used to receive external control commands through a data interface based on the data acquisition board, start data acquisition, fuse data from multiple data acquisition boards, and output the data through the data interface.

9. An electronic device, characterized in that, include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the distributed multi-site data synchronization acquisition method based on the White Rabbit technology as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program or instructions that, when executed by a processor, implement the distributed multi-site data synchronization acquisition method based on the White Rabbit technology as described in any one of claims 1 to 7.

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