Memory testing methods and electronic devices

Abstract

This application discloses a memory testing method and electronic device, relating to the field of memory testing technology. The method includes: dynamically configuring the testing environment based on the serial presence detection parameters of the memory under test, ensuring precise matching of testing criteria with memory specifications, significantly improving the accuracy and relevance of the test; simultaneously, by comparing power supply parameters and serial presence detection parameters in real time, dynamic adjustment of the protection threshold is achieved, which avoids accidental interruptions, ensures test continuity, and can respond promptly to real anomalies, effectively improving testing efficiency and reducing the risk of memory damage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory testing, and in particular to a memory testing method and an electronic device. BACKGROUND

[0002] In the related art, memory testing usually needs to monitor the signal waveform of the memory during operation with the help of an oscilloscope or other external devices, and by analyzing the amplitude, frequency, phase and other characteristics of the signal, it is determined whether there is an abnormality in the memory data transmission, clock synchronization and the like, but it is difficult to analyze in depth in the face of complex faults such as data transmission abnormalities, internal defects of memory chips and the like; in addition, in order to protect the electrical performance of the memory, the memory testing fixture is equipped with an overvoltage and overcurrent protection circuit, but the overvoltage and overcurrent protection circuit is mostly set with a fixed threshold value, which cannot match the complex and diverse working voltage and current range of different memories, and the fixed threshold value either leads to misjudgment, frequently cutting off normal power supply and interfering with the testing process, or is slow to react when a real abnormality occurs, and cannot protect the memory in time, increasing the risk of memory damage. SUMMARY

[0003] The present application provides a memory testing method and an electronic device to at least solve the problem of insufficient diagnostic depth and rigid protection strategy in the face of complex faults in the related art, which leads to the problem that the testing efficiency and protection reliability are difficult to balance.

[0004] The present application provides a memory testing method, which comprises: collecting a serial presence detect parameter of a memory to be tested; sending an initialization instruction to the memory to be tested and receiving response information of the memory to be tested, and in the case that it is determined that the initialization of the memory to be tested is successful according to the response information, testing the memory to be tested based on the serial presence detect parameter to obtain a test result; and in the process of testing the memory to be tested, collecting an actual power supply parameter of the memory to be tested based on a preset time interval, and performing a corresponding protection operation based on the actual power supply parameter and the serial presence detect parameter.

[0005] The present application also provides an electronic device, which comprises: a memory, a processor and a memory testing program stored in the memory and executable on the processor, and when the processor executes the memory testing program, the memory testing method described above is realized.

[0006] The memory testing method of the present application dynamically configures the test environment according to the serial presence detect parameter of the memory to be tested, so that the test criterion is accurately matched with the memory specification, which significantly improves the accuracy and pertinence of the test; at the same time, the dynamic adjustment of the protection threshold value is realized by real-time comparison of the power supply parameter and the serial presence detect parameter, which not only avoids false interruption and ensures the continuity of the test, but also responds in time when a real abnormality occurs, effectively improving the testing efficiency and reducing the risk of memory damage. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below only illustrate some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0008] Figure 1 The flow chart of the memory testing method according to some embodiments of the present application;

[0009] Figure 2 The structural schematic diagram of the memory testing system according to some embodiments of the present application;

[0010] Figure 3 The structural schematic diagram of the mechanical adapting unit according to some embodiments of the present application;

[0011] Figure 4 The flow chart of the memory testing method according to some other embodiments of the present application;

[0012] Figure 5 The block schematic diagram of the electronic device according to some embodiments of the present application. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the protection scope of the present application.

[0014] It should be noted that, in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover the non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are applicable to distinguish similar objects, and are not used to describe a specific order or sequence.

[0015] In order to make the skilled in the art better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0016] In combination with the specific application environment architecture or specific hardware architecture on which the memory testing method is executed, the specific application environment architecture or specific hardware architecture is described here.

[0017] Embodiments of the present application provide a memory testing method. The method is described in detail in combination with an execution flow of the memory testing method.

[0018] Figure 1 FIG. 1 is a flowchart of a memory testing method according to some embodiments of the present application. Referring to FIG. 1, the memory testing method according to some embodiments of the present application can include the following steps: Figure 1

[0019] S110, serial presence detection parameters of the memory to be tested are collected.

[0020] Specifically, after the memory to be tested is installed into a memory testing fixture, the memory testing fixture reads JEDEC standard information in an SPD (Serial Presence Detect) chip of the memory to be tested through an SPI (Serial Peripheral Interface) or an I2C (Inter-Integrated Circuit) communication interface integrated on the memory testing fixture, i.e., reads serial presence detection parameters, which include the type, capacity, reference power supply parameters (e.g., reference power supply voltage and reference power supply current), reference amplitude parameters and reference timing parameters of memory data signals, address signals and clock signals of the memory to be tested.

[0021] S120, an initialization instruction is sent to the memory to be tested, and response information of the memory to be tested is received. In a case where it is determined according to the response information that the memory to be tested is initialized successfully, the memory to be tested is tested based on the serial presence detection parameters to obtain a test result.

[0022] ​Specifically, after the serial presence detect parameters of the memory to be tested are collected, the memory test fixture sends an initialization instruction, such as an MRS (Mode Register Set) or EMRS (Extended Mode Register Set) instruction of DDR5 (Double Data Rate 5 Synchronous Dynamic Random-Access Memory), to the memory to be tested, and receives response information of the memory to be tested. Then, the response information is matched with an expected value, and in the case that the response information is consistent with the expected value, it is determined that the memory to be tested is successfully initialized. Then, the memory test fixture sends a test instruction to the memory to be tested, the memory to be tested performs a corresponding test operation based on the test instruction to obtain corresponding test data, and returns the test data to the memory test fixture. The memory test fixture matches the test data with the serial presence detect parameters to obtain a test result.

[0023] In the process of testing the memory to be tested, actual power supply parameters of the memory to be tested are collected based on a preset time interval, and a corresponding protection operation is performed based on the actual power supply parameters and the serial presence detect parameters. The preset time interval can be determined according to actual conditions, for example, the preset time interval can be 1 minute, which is not limited here.

[0024] Specifically, in the process of testing the memory to be tested, the memory test fixture collects actual power supply parameters of the memory to be tested every preset time interval, compares the actual power supply parameters with the serial presence detect parameters, determines whether a protection operation needs to be performed according to the comparison result, and performs a specific protection operation in the case that it is determined that the protection operation needs to be performed. For example, if it is determined according to the comparison result that the actual power supply parameters are relatively large, it is determined that the protection operation needs to be performed, such as stopping power supply to the memory to be tested.

[0025] The memory test method of the present application dynamically configures the test environment according to the serial presence detect parameters of the memory to be tested, so that the test criterion is accurately matched with the memory specification, which significantly improves the accuracy and pertinence of the test. At the same time, by comparing the power supply parameters with the serial presence detect parameters in real time, the protection threshold is dynamically adjusted, which not only avoids false interruption and ensures the continuity of the test, but also responds in time when there is a real exception, effectively improves the test efficiency and reduces the risk of memory damage.

[0026] In some embodiments, the serial presence detection parameters include a reference supply voltage and a reference supply current of the memory to be tested, the actual supply parameters include an actual supply voltage and an actual supply current, and the corresponding protection operation is performed based on the actual supply parameters and the serial presence detection parameters, including: determining a voltage protection threshold based on a product of the reference supply voltage and a preset protection coefficient; determining a current protection threshold based on a product of the reference supply current and the preset protection coefficient; and performing the corresponding protection operation according to the voltage protection threshold, the current protection threshold, the actual supply voltage and the actual supply current. The preset protection coefficient can be calibrated according to actual conditions, for example, the preset protection coefficient can be 0.95, which is not limited here.

[0027] Specifically, after the memory to be tested is installed into the memory test fixture, the memory test fixture collects the serial presence detection parameters of the memory to be tested through the communication interface, the serial presence detection parameters of the memory to be tested including a reference supply voltage of the memory to be tested and a reference supply current of the memory to be tested, wherein the reference supply voltage is used to represent the maximum supply voltage that the memory to be tested can withstand, and the reference supply current is used to represent the maximum supply current that the memory to be tested can withstand; then, a voltage protection threshold is determined based on a product of the reference supply voltage and a preset protection coefficient, and a current protection threshold is determined based on a product of the reference supply current and the preset protection coefficient, thereby realizing individual customization of the protection threshold; finally, during the testing of the memory to be tested by the memory test fixture, the actual supply voltage and the actual supply current are collected every preset time interval, and it is determined whether the protection operation needs to be performed according to the voltage protection threshold, the current protection threshold, the actual supply voltage and the actual supply current, for example, the actual supply voltage is compared with the voltage protection threshold, and at the same time, the actual supply current is compared with the current protection threshold, if the difference between the voltage protection threshold and the actual supply voltage is large, and the difference between the current protection threshold and the actual supply current is also large, it is determined that the protection operation does not need to be performed; if the difference between the current protection threshold and the actual supply current is large, but the difference between the voltage protection threshold and the actual supply voltage is small, it is determined that the protection operation needs to be performed, for example, the memory test fixture issues an alarm prompt; if the actual supply current exceeds the current protection threshold or the actual supply voltage exceeds the voltage protection threshold, it is determined that the protection operation needs to be performed, for example, the memory test fixture directly powers off.

[0028] In some embodiments, the corresponding protection operation is performed according to the voltage protection threshold, the current protection threshold, the actual supply voltage and the actual supply current, including: in a case that the actual supply current is less than or equal to the current protection threshold, and the actual supply voltage is greater than or equal to the product of the voltage protection threshold and a preset percentage and less than the voltage protection threshold, it is determined that the protection operation is to issue a power supply protection warning action; in a case that the actual supply current is greater than the current protection threshold or the actual supply voltage is greater than or equal to the voltage protection threshold, it is determined that the protection operation is to cut off the power supply circuit of the memory to be tested. The preset percentage can be calibrated according to the actual situation, for example, the preset percentage can be 90%, which is not limited here.

[0029] For example, assuming that the current protection threshold is 2A, the voltage protection threshold is 1.21V, the product of the voltage protection threshold and the preset percentage is 1.089V, if it is detected that the actual supply voltage is 1V and the actual supply current is 1.6A, it indicates that the actual supply voltage is less than the product of the voltage protection threshold and the preset percentage, and the actual supply current is less than the current protection threshold, so it is determined that no protection operation is needed, and the green display light of the memory test fixture is on; if it is detected that the actual supply voltage is 1.1V and the actual supply current is 1.6A, it indicates that the actual supply current is less than the current protection threshold, and the actual supply voltage is greater than or equal to the product of the voltage protection threshold and the preset percentage and less than the voltage protection threshold, so it is determined that the protection operation is to issue a power supply protection warning action, for example, the yellow display light of the memory test fixture is on; if it is detected that the actual supply current is 2.1A, it indicates that the actual supply current is greater than or equal to the current protection threshold, or if it is detected that the actual supply voltage is 1.22V, it indicates that the actual supply voltage is greater than or equal to the voltage protection threshold, so it is determined that the protection operation is to cut off the power supply circuit of the memory to be tested, for example, an NMOS (N-type Metal-Oxide-Semiconductor) tube is used as a main switching device (on-resistance <10mΩ), and a high-speed gate driver (response time <50ns) is used, when an abnormality is detected, the memory power supply can be cut off within 1μs, which is much faster than a traditional relay (millisecond level), and the red display light of the memory test fixture is on, which needs to be manually reset.

[0030] The present application compares the actual supply parameters with the dynamic threshold in real time, provides a buffer intervention opportunity for the system when the parameters are close to the threshold, cuts off the power supply immediately when the parameters exceed the safety limit, and ensures the timeliness of protection. In this way, the continuity of the test can be ensured, and the safety and reliability of the memory test process can be significantly improved.

[0031] In some embodiments, the serial presence detection parameters include reference amplitude parameters and reference timing parameters of memory data signals, address signals and clock signals of the memory to be tested, and the test result includes a signal integrity state. The testing of the memory to be tested based on the serial presence detection parameters to obtain the test result includes: sending a preset data test sequence to the memory to be tested at multiple test frequencies to collect actual amplitude parameters and actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested; and determining the signal integrity state of the memory to be tested according to the reference amplitude parameters and the reference timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested and the actual amplitude parameters and the actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested.

[0032] Specifically, after the memory to be tested is installed to the memory test fixture, the memory test fixture collects the serial presence detection parameters of the memory to be tested through a communication interface. The serial presence detection parameters of the memory to be tested include reference amplitude parameters and reference timing parameters of memory data signals, address signals and clock signals of the memory to be tested. Then, the memory test fixture sends a test instruction to the memory to be tested, for example, sends a preset data test sequence to the memory to be tested at a test frequency (for example, 3200 MHz), and then captures the memory data signals, the address signals and the clock signals of the memory to be tested. The actual amplitude parameters and the actual timing parameters are determined by analyzing the voltage trajectories of the signal waveforms. Specifically, the actual amplitude parameters are calculated by counting the voltage extreme values of the high level and the low level to obtain the signal swing. The actual timing parameters are measured based on the clock edge to measure the setup and hold times of the data signals before and after the transition, so as to quantify the actual state of the signal. After the actual amplitude parameters and the actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested are collected, the actual amplitude parameters and the actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested are compared with the reference amplitude parameters and the reference timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested. Specifically, the actual amplitude parameters of the memory data signals are compared with the reference amplitude parameters of the memory data signals, the actual timing parameters of the memory data signals are compared with the reference timing parameters of the memory data signals, the actual amplitude parameters of the address signals are compared with the reference amplitude parameters of the address signals, the actual timing parameters of the address signals are compared with the reference timing parameters of the address signals, the actual amplitude parameters of the clock signals are compared with the reference amplitude parameters of the clock signals, the actual timing parameters of the clock signals are compared with the reference timing parameters of the clock signals, and the signal integrity state of the memory to be tested is determined according to the comparison results.

[0033] After the current test frequency test is completed, the next test frequency (for example, 2666MHz) is switched to send a preset data test sequence to the to-be-tested memory to retest the signal integrity state of the to-be-tested memory under the next test frequency.

[0034] In some embodiments, the signal integrity state of the to-be-tested memory is determined according to the reference amplitude parameters and the reference timing parameters of the memory data signal, the address signal and the clock signal of the to-be-tested memory and the actual amplitude parameters and the actual timing parameters of the memory data signal, the address signal and the clock signal of the to-be-tested memory, including: determining the amplitude deviation values of the memory data signal, the amplitude deviation values of the address signal and the amplitude deviation values of the clock signal of the to-be-tested memory based on the differences between the actual amplitude parameters and the corresponding reference amplitude parameters of the memory data signal, the address signal and the clock signal of the to-be-tested memory; determining the timing deviation values of the memory data signal, the timing deviation values of the address signal and the timing deviation values of the clock signal of the to-be-tested memory based on the differences between the actual timing parameters and the corresponding reference timing parameters of the memory data signal, the address signal and the clock signal of the to-be-tested memory; determining the signal integrity state of the to-be-tested memory as an abnormal state in a case that at least one of the absolute values of the amplitude deviation values of the memory data signal, the absolute values of the amplitude deviation values of the address signal and the absolute values of the amplitude deviation values of the clock signal and the absolute values of the timing deviation values of the memory data signal, the absolute values of the timing deviation values of the address signal and the absolute values of the timing deviation values of the clock signal of the to-be-tested memory is greater than a corresponding preset tolerance threshold.

[0035] For example, the amplitude deviation values between the actual amplitude parameters of the memory data signal and the reference amplitude parameters of the memory data signal, the amplitude deviation values between the actual amplitude parameters of the address signal and the reference amplitude parameters of the address signal and the amplitude deviation values between the actual amplitude parameters of the clock signal and the reference amplitude parameters of the clock signal are calculated; the timing deviation values between the actual timing parameters of the memory data signal and the reference timing parameters of the memory data signal, the timing deviation values between the actual timing parameters of the address signal and the reference timing parameters of the address signal and the timing deviation values between the actual timing parameters of the clock signal and the reference timing parameters of the clock signal are calculated; the absolute values of the above-mentioned amplitude deviation values are compared with the corresponding preset tolerance thresholds, the absolute values of the above-mentioned timing deviation values are compared with the corresponding preset tolerance thresholds, and if one or more of the absolute values of the above-mentioned amplitude deviation values and the absolute values of the above-mentioned timing deviation values is greater than the corresponding preset tolerance threshold, the signal integrity state of the to-be-tested memory is an abnormal state; if the absolute values of the above-mentioned amplitude deviation values and the absolute values of the above-mentioned timing deviation values are all less than or equal to the corresponding preset tolerance thresholds, the signal integrity state of the to-be-tested memory is a normal state. The preset tolerance threshold can be calibrated according to the actual situation, which is not limited here.

[0036] The application realizes accurate evaluation of the signal integrity state by testing the actual parameters of the memory signal at multiple frequencies and quantitatively comparing with the reference standard in the serial presence detection parameter. In this way, by calculating the deviation value of the amplitude and timing, and automatically judging based on the preset tolerance, the signal degradation caused by physical link or high-frequency interference can be effectively detected, so as to comprehensively evaluate the electrical performance and stability of the memory under high load and different working frequencies.

[0037] In some embodiments, the test result includes a test power consumption stability state, and the method further includes: sending a continuous refresh operation instruction to the to-be-tested memory, and collecting the test power consumption of the to-be-tested memory in the process of executing the continuous refresh operation instruction by the to-be-tested memory; in the case that the test power consumption is greater than a preset test power consumption threshold, determining that the test power consumption stability state is an abnormal state. The preset test power consumption threshold can be calibrated according to actual conditions, which is not specifically limited here.

[0038] Specifically, the memory test fixture sends a test instruction to the to-be-tested memory, for example, sends a continuous refresh operation instruction to the to-be-tested memory, collects the current and voltage in the memory power supply loop in the process of executing the continuous refresh operation instruction by the to-be-tested memory, and determines the test power consumption of the to-be-tested memory based on the product of the current and voltage; then, the test power consumption of the to-be-tested memory is compared with the preset test power consumption threshold, if the test power consumption is greater than the preset test power consumption threshold, it is determined that the test power consumption stability state of the to-be-tested memory is an abnormal state; if the test power consumption is less than or equal to the preset test power consumption threshold, it is determined that the test power consumption stability state of the to-be-tested memory is a normal state.

[0039] The application can effectively identify abnormal test power consumption phenomena caused by internal leakage current increase or circuit failure by monitoring the dynamic test power consumption of the memory when it executes the continuous refresh operation, so as to accurately judge the test power consumption stability state of the memory, and provide a direct basis for detecting potential defects and preventing reliability risks caused by overheating or overconsumption.

[0040] In some embodiments, the test result includes a bad block of the to-be-tested memory, including: writing corresponding reference data to the access address of the to-be-tested memory, and accessing the access address of the to-be-tested memory one by one to read corresponding target data; matching the reference data and the target data, and determining the bad block of the to-be-tested memory according to the matching result.

[0041] Specifically, the memory test fixture sends a test instruction to the memory to be tested, for example, writes corresponding reference data to the access address of the memory to be tested, and accesses the access address of the memory to be tested one by one to read corresponding target data, and through bit-by-bit matching of the read target data and the originally written reference data, if any target data is found to be inconsistent with the reference data, the storage unit or storage block where the bit is located is determined to be a bad block, thereby accurately identifying the physical defect area in the memory.

[0042] The application realizes accurate positioning of the physical defects of the storage unit by writing preset reference data to the memory address and comparing the read data bit by bit. In this way, unreliable storage bits are directly exposed through data consistency verification, which can effectively identify the bad block area in the memory, providing a direct basis for memory quality and reliability evaluation.

[0043] In some embodiments, the response information includes response time and return code, and the initialization success of the memory to be tested is determined according to the response information, including: in the case that the response time is less than or equal to a preset response time threshold and the return code is a preset return code, it is determined that the initialization of the memory to be tested is successful. Wherein, the preset response time threshold can be calibrated according to the actual situation, for example, the preset response time threshold can be 1s, which is not limited here.

[0044] Specifically, after collecting the serial presence detection parameters of the memory to be tested, the memory test fixture will send an initialization instruction to the memory to be tested, and receive the response information of the memory to be tested, the response information including response time and return code, if the response time is less than or equal to a preset response time threshold and the return code is a preset return code (indicating initialization success), it is determined that the initialization of the memory to be tested is successful; if the response time is greater than the preset response time threshold, or the return code is not the preset return code, or the response time is greater than the preset response time threshold and the return code is not the preset return code, it is determined that the initialization of the memory to be tested fails.

[0045] In this way, the reliability of initialization success is ensured in two dimensions of timing and state, effectively avoiding test process errors caused by single condition misjudgment, and improving the accuracy of initialization state detection and the confidence level of test results.

[0046] In some embodiments, the serial presence detection parameters of the memory to be tested are collected, including: obtaining the gold finger physical parameters and configuration information of the memory to be tested; adjusting the spacing of the scalable slot assembly based on the gold finger physical parameters to adapt to the physical size of the memory to be tested; dynamically adjusting the conduction logic between the electrical contacts based on the configuration information of the memory to be tested to adapt to the pin definition of the memory to be tested; after completing the mechanical adaptation and electrical adaptation of the memory to be tested, and in response to a collection enable signal, reading the serial presence detection parameters of the memory to be tested.

[0047] Specifically, the memory test fixture usually adopts a fixed slot design, which can only adapt to a specific specification of memory. In the current era of frequent memory updates, the compatibility short board is obvious. For example, when transitioning from DDR3 (Double Data Rate 3 Synchronous Dynamic Random-Access Memory) memory to DDR4 (Double Data Rate 4 Synchronous Dynamic Random-Access Memory) memory, the memory test fixture cannot be compatible due to significant changes in the pin pitch, pin count, and electrical characteristics of the memory. Based on this, after the memory to be tested is installed into the memory test fixture, the memory test fixture will collect the physical parameters (such as length, pin pitch) of the memory to be tested through the built-in sensor, and obtain the configuration information (such as voltage type, pin definition) through the communication interface of the memory test fixture; then, the memory test fixture automatically adjusts the mechanical pitch of the scalable slot to ensure reliable physical contact, and dynamically configures the connection logic of the electrical contact to match different signal definitions; after completing the two adaptive matching, and in response to the collection enable signal, the serial presence detect parameters of the memory to be tested are read.

[0048] Alternatively, after the memory to be tested is installed into the memory test fixture, the memory test fixture will collect the physical parameters (such as length, pin pitch) of the memory to be tested through the built-in sensor, adjust the pitch of the scalable slot assembly based on the physical parameters of the memory to be tested, to adapt to the physical size of the memory to be tested, and after successful connection, read the serial presence detect parameters of the memory to be tested through the SPI / I2C communication interface, which includes the configuration information of the memory to be tested; then, based on the configuration information of the memory to be tested, the conduction logic between the electrical contacts is dynamically adjusted to adapt to the pin definition of the memory to be tested, and after completing the mechanical adaptation and electrical adaptation of the memory to be tested, initialization and subsequent testing are performed.

[0049] The present application automatically obtains the physical parameters and configuration information of the memory gold finger, realizes the mechanical self-adaptation of the test fixture slot pitch and the dynamic configuration of the electrical contact conduction logic, and effectively overcomes the compatibility bottleneck of the traditional fixed slot design when the memory specification iterates. In this way, a single test fixture can automatically adapt to different generations and different specifications of memory modules, safely and accurately read the serial presence detect parameters under the premise of ensuring the reliability of physical connection and the matching of electrical interface, and significantly improves the universality of testing and equipment utilization.

[0050] As a specific example, refer to Figure 2The memory test system 1 comprises an adjustable connection module 11, a test module 12, a protection module 13 and a display module 14.

[0051] The adjustable connection module 11 comprises a mechanical adaptation unit, an electrical adaptation unit and a parameter identification unit. The mechanical adaptation unit comprises a telescopic slot assembly, a displacement detection assembly (e.g. laser sensor 0, laser sensor 1, laser sensor 2 and laser sensor 3) and a motor driving assembly, as shown in the figure. The mechanical adaptation unit is configured to collect the physical parameters of the gold finger of the memory to be tested (e.g. to detect the width, pitch and thickness parameters of the gold finger) through the displacement detection assembly, and to control the motor driving assembly to adjust the pitch of the telescopic slot assembly (e.g. to adjust the range covering DDR3 to DDR5 and LPDDR series of memories) based on the physical parameters of the gold finger, so as to adapt to the physical size of the memory to be tested. Figure 3

[0052] The electrical adaptation unit comprises a spring probe array and a programmable switch matrix. The spring probe array forms an electrical contact with the gold finger of the memory to be tested (a single needle can withstand 0-5V voltage and a maximum of 3A current). The programmable switch matrix dynamically adjusts the conduction logic between the electrical contacts based on the configuration information of the memory to be tested, so as to adapt to the pin definition of the memory to be tested (e.g. 288 pins of DDR4 and 288 pins of DDR5 but different signal definitions).

[0053] The parameter identification unit (integrating SPI / I2C communication interface) is configured to receive the collection enable signal sent by the test module 12 after the mechanical adaptation unit completes the mechanical adaptation and electrical adaptation of the memory to be tested, and to read the JEDEC standard information in the SPD chip of the memory to be tested in response to the collection enable signal, i.e. to read the serial presence detect parameter, which includes the type, capacity, reference power supply parameter (e.g. reference power supply voltage and reference power supply current), reference amplitude parameter and reference timing parameter of the memory data signal, address signal and clock signal of the memory to be tested, and to transmit the serial presence detect parameter to the test module 12 and the protection module 13.

[0054] ​Exemplarily, the mechanical adaptation unit adopts a manually knob-adjustable telescopic slot assembly. The two side baffles can be driven to slide by the knob to adapt to the length difference of DDR3 (gold finger length 133.35 mm), DDR4 (gold finger length 133.35 mm) and DDR5 (gold finger length 139.7 mm). The adjustment range is 130-140 mm. The inner side of the baffle is attached with a wear-resistant rubber pad to ensure stable fixation after the to-be-tested memory is inserted. The electrical adaptation unit selects a 288-pin gold-plated pogo pin array with a pin pitch of 1 mm, covering the gold finger pin distribution of mainstream memories. The probe stroke is 0.5 mm, which ensures reliable contact with the gold finger. The contacts are connected to the test module 12 through a flat cable. The parameter identification unit integrates a simple I2C card reader. The basic information (memory type, working voltage) of the memory SPD chip is read to complete the identification within 200 ms, and the LED indicator (red / green) is used to prompt whether the identification is successful.

[0055] The core processor of the test module 12 can adopt an STM32F103C8T6 microprocessor with high-speed data processing capability, which can run the memory initialization detection, signal analysis and protection control algorithm in parallel. The test module 12 is configured to test the to-be-tested memory based on the serial presence detect parameters to obtain a test result, determine a fault signal of the to-be-tested memory according to the test result, for example, match the test data with a preset fault feature library (containing 100+ typical fault modes, such as VDD overvoltage, DQ signal open circuit, initialization timeout, etc.) to determine the fault signal of the to-be-tested memory, and send the fault signal to the state display module 14. Specifically, the test module 12 includes a basic test unit, a signal test unit, a stress test unit and an initialization unit. The initialization unit is configured to send an initialization instruction to the to-be-tested memory, receive response information of the to-be-tested memory, and determine whether the to-be-tested memory is initialized successfully according to the response information, and test the to-be-tested memory in the case of successful initialization. The basic test unit is configured to write corresponding reference data to the access address of the to-be-tested memory, and access the access address of the to-be-tested memory one by one to read corresponding target data, match the reference data with the target data, and determine the bad block of the to-be-tested memory according to the matching result. The signal test unit is configured to send a preset data test sequence to the to-be-tested memory at multiple test frequencies to collect the amplitude parameters and timing parameters of the data signal, address signal and clock signal of the to-be-tested memory, and determine the signal integrity state of the to-be-tested memory according to the amplitude parameters, timing parameters, reference amplitude parameters and reference timing parameters. The stress test unit is configured to send a continuous refresh operation instruction to the to-be-tested memory, and collect the test power consumption of the to-be-tested memory in the process of executing the continuous refresh operation instruction of the to-be-tested memory, and determine the test power consumption stability state according to the test power consumption.

[0056] The test module 12 is further configured to collect power supply parameters of the memory to be tested during the test, for example, by a 16-bit ADC (Analog-to-Digital Converter) chip (sampling rate 1 MSPS) to collect power supply voltage (precision ±1 mV) and power supply current (precision ±1 mA) in real time, monitor the key power supply pins of the memory such as VDD (Voltage Drain Drain), VDDIO (Voltage Drain Drain Input / Output), VPP (Voltage Peak-to-Peak), and transmit the power supply parameters to the protection module 13.

[0057] The protection module 13 is configured to receive the serial presence detection parameters and the power supply parameters of the memory to be tested, determine the protection threshold of the memory to be tested according to the serial presence detection parameters, and perform corresponding protection operations based on the power supply parameters and the protection threshold parameters; specifically, the protection module 13 includes a protection threshold determination unit, a warning unit and a cutting unit, wherein the protection threshold determination unit is configured to determine a voltage protection threshold based on the product of the reference power supply voltage and the preset protection coefficient, and determine a current protection threshold based on the product of the reference power supply current and the preset protection coefficient; the warning unit is configured to issue a power supply protection warning action in the case that the actual power supply current is less than or equal to the current protection threshold, the actual power supply voltage is greater than or equal to the product of the voltage protection threshold and the preset percentage and less than the voltage protection threshold; the cutting unit is configured to cut off the power supply loop of the memory to be tested in the case that the actual power supply current is greater than the current protection threshold or the actual power supply voltage is greater than or equal to the voltage protection threshold.

[0058] The display module 14 is configured to receive the fault signal and drive the corresponding display unit to perform the corresponding visual indication strategy according to the fault signal to visualize the fault type of the memory to be tested.

[0059] The power supply module (not shown) adopts a 12V DC power input, and outputs adjustable voltage (1.0-3.3V) through a DC-DC (Direct Current to Direct Current Converter) converter (such as LM2596), which is cooperatively controlled by the protected circuit and the controller.

[0060] The assembly steps of the memory test system 1 include:

[0061] Mechanical frame building: fix the telescopic slot assembly on the acrylic base, ensure that the center of the slot is parallel to the edge of the base, and install the knob on the side of the frame, which can smoothly adjust the distance between the baffles when rotating.

[0062] Electrical connection: connect the spring needle array to the GPIO (General-Purpose Input / Output) pin of the STM32 controller through the flat cable, the voltage detection circuit is connected to the ADC channel of the controller, and the current detection resistor is connected in series in the power supply circuit, and the output end is connected to another ADC channel of the controller.

[0063] Indicator light and protection circuit installation: fix the LED (Light-Emitting Diode) light plate on the front end panel of the base, and connect it to the IO port of the controller through the current limiting resistor; the relay output end of the overvoltage protection circuit is connected in series in the power supply circuit, and the control signal is connected to the interrupt pin of the controller.

[0064] Power module connection: use 12V DC power input, and output adjustable voltage (1.0-3.3V) through DC-DC converter (such as LM2596), which is cooperatively controlled by the protected circuit and the controller.

[0065] As a specific example, with reference to Figure 4 The memory test method of the embodiment of the application can further include the following steps:

[0066] S210, the memory to be tested is connected and the serial presence detect parameter is identified.

[0067] After the memory to be tested is inserted into the memory test fixture, the adjustable connection module 11 triggers mechanical adjustment through the displacement detection assembly, and the serial presence detect parameter is read synchronously.

[0068] For example, the operator adjusts the telescopic slot assembly to the corresponding length according to the type of the memory to be tested (such as DDR4) through the knob, inserts the memory gold finger into the spring needle array, and hears a "click" sound to indicate that it is installed in place. Press the specification identification button, and the I2C card reader reads the serial presence detect parameter. If the green indicator light flashes 3 times, it means that the identification is successful; if the red light is always on, the memory to be tested needs to be reinserted.

[0069] S220, adaptive power supply and initialization.

[0070] The power supply module of the memory test fixture determines the power supply voltage according to the serial presence detect parameter, and outputs the power supply voltage (such as 1.1V for DDR5) conforming to the memory specification through the digital-to-analog converter (DAC), and slowly increases the voltage to the power supply voltage based on a preset slope (for example, the preset slope can be 0.1V / ms to avoid impact); then, the test module 12 sends an initialization instruction sequence to the memory to be tested, monitors the memory response information, and if the initialization fails, records the failure code and feedbacks through the indicator light.

[0071] S230, performance test of the memory to be tested.

[0072] If the initialization is successful, the basic test, signal test and pressure test are performed. Meanwhile, during the test process, the actual power supply voltage and the actual power supply current are collected once per second. In the case that the actual power supply current is less than or equal to the current protection threshold value, and the actual power supply voltage is less than the product of the voltage protection threshold value and the preset percentage, the power supply is maintained, and the green light is always on. In the case that the actual power supply current is less than or equal to the current protection threshold value, and the actual power supply voltage is greater than or equal to the product of the voltage protection threshold value and the preset percentage and less than the voltage protection threshold value, a power supply protection warning action is sent, that is, the yellow light flashes, and the power supply is cut off if it is not restored for a preset time (5s). In the case that the actual power supply current is greater than the current protection threshold value or the actual power supply voltage is greater than or equal to the voltage protection threshold value, the power supply circuit of the memory to be tested is cut off, the red light is always on, the relay immediately cuts off the power supply, and manual reset is required.

[0073] S240, result output and summary.

[0074] After the test is completed, the test module 12 generates a report containing the memory model, test items and fault signals, and uploads it to the upper computer through a USB (Universal Serial Bus) or Ethernet interface. The display module 14 drives the corresponding display unit according to the fault signal to execute the corresponding visual indication strategy, so as to visualize the fault type of the memory to be tested.

[0075] In summary, the application realizes significant improvement in test platform compatibility and economy by integrating an adjustable mechanical structure and a general electrical interface. The core innovation lies in the use of a manually adjustable slot frame and a fully compatible spring needle array, which can be used for mainstream memory specifications and pin adaptive design to physically cover the contact distribution of different generations of memories, fundamentally solving the contact failure problem caused by differences in gold finger definitions, reducing the number of tool purchases and reducing equipment investment costs.

[0076] In terms of test process optimization, the integrated I2C protocol parser can automatically complete serial presence detect parameter reading and specification identification within a short time (e.g. 200ms), improving test preparation efficiency. Voltage and current synchronous monitoring can accurately distinguish between different abnormal states such as poor contact (warning) and hardware damage (failure), reducing the misjudgment rate. By implementing an initialization instruction response detection mechanism, implicit chip faults can be effectively identified, greatly improving fault coverage.

[0077] The protection system uses a programmable overvoltage protection module that supports manual setting of the protection threshold value according to the memory specification, ensuring the accuracy of overvoltage protection while completely avoiding false triggering. In combination with a fast cut-off circuit, power supply isolation can be completed before the short-circuit current reaches the preset current threshold, reducing the risk of chip burnout.

[0078] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software on a necessary general hardware platform, and of course can also be realized by hardware, but in many cases the former is a better embodiment.

[0079] Embodiments of the present application also provide an electronic device, which refers to Figure 5 , comprising a memory 310, a processor 320, and a memory test program stored in the memory 310 and executable on the processor 320, and when the processor 320 executes the memory test program, the memory test method described above is realized.

[0080] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0081] The above provides a detailed description of a memory test method and an electronic device. The principles and embodiments of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method and its core idea. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A memory testing method, characterized by, The method comprises: collecting a serial presence detect parameter of a memory to be tested; sending an initialization instruction to the memory to be tested and receiving response information of the memory to be tested, and in the case that it is determined that the memory to be tested is initialized successfully according to the response information, testing the memory to be tested based on the serial presence detect parameter to obtain a test result; in the process of testing the memory to be tested, collecting actual power supply parameters of the memory to be tested based on a preset time interval, and performing a corresponding protection operation based on the actual power supply parameters and the serial presence detect parameter.

2. The memory testing method of claim 1, wherein, The serial presence detect parameter comprises a reference power supply voltage and a reference power supply current of the memory to be tested, the actual power supply parameter comprises an actual power supply voltage and an actual power supply current, and performing a corresponding protection operation based on the actual power supply parameters and the serial presence detect parameter comprises: determining a voltage protection threshold based on a product of the reference power supply voltage and a preset protection coefficient; determining a current protection threshold based on a product of the reference power supply current and the preset protection coefficient; performing a corresponding protection operation according to the voltage protection threshold, the current protection threshold, the actual power supply voltage and the actual power supply current.

3. The memory testing method of claim 2, wherein, Performing a corresponding protection operation according to the voltage protection threshold, the current protection threshold, the actual power supply voltage and the actual power supply current comprises: in the case that the actual power supply current is less than or equal to the current protection threshold, the actual power supply voltage is greater than or equal to a product of the voltage protection threshold and a preset percentage and less than the voltage protection threshold, determining that the protection operation is to issue a power supply protection warning action; in the case that the actual power supply current is greater than the current protection threshold or the actual power supply voltage is greater than or equal to the voltage protection threshold, determining that the protection operation is to cut off a power supply loop of the memory to be tested.

4. The memory testing method of claim 1, wherein, The serial presence detect parameter comprises reference amplitude parameters and reference timing parameters of memory data signals, address signals and clock signals of the memory to be tested, and the test result comprises a signal integrity state, and testing the memory to be tested based on the serial presence detect parameter to obtain a test result comprises: sending a preset data test sequence to the memory to be tested at a plurality of test frequencies to collect actual amplitude parameters and actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested; determining the signal integrity state of the memory to be tested according to the reference amplitude parameters and the reference timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested and the actual amplitude parameters and the actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested.

5. The memory testing method of claim 4, wherein, Determining the signal integrity state of the memory to be tested according to the reference amplitude parameters and the reference timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested and the actual amplitude parameters and the actual timing parameters of the memory data signals, the address signals and the clock signals of the memory to be tested comprises: determining the amplitude deviation value of the memory data signal, the amplitude deviation value of the address signal and the amplitude deviation value of the clock signal of the to-be-tested memory based on the difference between the actual amplitude parameters of the memory data signal, the address signal and the clock signal of the to-be-tested memory and the corresponding reference amplitude parameters; determining the timing deviation value of the memory data signal, the timing deviation value of the address signal and the timing deviation value of the clock signal of the to-be-tested memory based on the difference between the actual timing parameters of the memory data signal, the address signal and the clock signal of the to-be-tested memory and the corresponding reference timing parameters; determining that the signal integrity state of the to-be-tested memory is an abnormal state in a case where at least one of the absolute value of the amplitude deviation value of the memory data signal, the absolute value of the amplitude deviation value of the address signal and the absolute value of the amplitude deviation value of the clock signal of the to-be-tested memory and the absolute value of the timing deviation value of the memory data signal, the absolute value of the timing deviation value of the address signal and the absolute value of the timing deviation value of the clock signal of the to-be-tested memory is greater than a corresponding preset tolerance threshold.

6. The memory testing method of claim 1, wherein, The test result includes a test power consumption stability state, and the method further includes: sending a continuous refresh operation instruction to the to-be-tested memory, and collecting test power consumption of the to-be-tested memory in a process in which the to-be-tested memory executes the continuous refresh operation instruction; determining that the test power consumption stability state is an abnormal state in a case where the test power consumption is greater than a preset test power consumption threshold.

7. The memory testing method of claim 1, wherein, The test result includes a bad block of the to-be-tested memory, and includes: writing corresponding reference data to an access address of the to-be-tested memory, and accessing the access address of the to-be-tested memory one by one to read corresponding target data; matching the reference data and the target data, and determining the bad block of the to-be-tested memory according to a matching result.

8. The memory testing method of claim 1, wherein, The response information includes a response time and a return code, and determining that the to-be-tested memory is initialized successfully according to the response information includes: determining that the to-be-tested memory is initialized successfully in a case where the response time is less than or equal to a preset response time threshold and the return code is a preset return code.

9. The memory testing method of claim 1, wherein, Collecting a serial presence detect parameter of the to-be-tested memory includes: obtaining a golden finger physical parameter and configuration information of the to-be-tested memory; adjusting a spacing of a scalable socket assembly based on the golden finger physical parameter to adapt to a physical size of the to-be-tested memory; dynamically adjusting a conduction logic between electrical contacts based on the configuration information of the to-be-tested memory to adapt to a pin definition of the to-be-tested memory; after completing mechanical adaptation and electrical adaptation of the to-be-tested memory, and in response to a collection enable signal, reading the serial presence detect parameter of the to-be-tested memory.

10. An electronic device, comprising: A memory, a processor and a memory test program stored on the memory and executable on the processor are included, and the processor implements the memory test method according to any one of claims 1-9 when executing the memory test program.

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