Circuit board and manufacturing method thereof

Abstract

The invention relates to the technical field of circuit boards, and discloses a circuit board and a manufacturing method thereof.The circuit board comprises a first connecting layer, a circuit layer and a second connecting layer, the circuit layer is located between the first connecting layer and the second connecting layer, the average grain size of the circuit layer is 50 nm to 80 nm, and the twin crystal density of the circuit layer is 50 nm to 80 nm. The circuit board and the manufacturing method thereof provided by the invention are used for solving the problems that the risk of a fatigue failure phenomenon is relatively high when the circuit board bears vibration, and the anti-vibration performance is relatively weak.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit boards, in particular to a circuit board and a manufacturing method thereof. BACKGROUND

[0002] With the development of science and technology, the application scenarios of circuit boards are becoming more and more extensive. In some application scenarios, the circuit board will be subjected to harsh vibration environment for a long time, which will increase the risk of fatigue failure of the circuit board due to vibration.

[0003] For example, in a new energy vehicle, the performance of the circuit board will affect the safety and reliability of the power battery pack of the vehicle, and thus affect the overall vehicle performance. When the vehicle is running, the circuit board of the battery pack will usually be subjected to harsh vibration environment. When the vehicle passes through a deceleration zone or an unpaved road, the instantaneous vibration acceleration can reach more than 30G, which greatly increases the fatigue failure phenomenon of the circuit board.

[0004] In related technologies, the risk of fatigue failure of the circuit board is relatively large when subjected to vibration, and the vibration resistance of the circuit board is relatively weak. SUMMARY

[0005] The present application provides a circuit board and a manufacturing method thereof, which are used to solve the problem that the risk of fatigue failure of the circuit board is relatively large when subjected to vibration, and the vibration resistance of the circuit board is relatively weak.

[0006] In a first aspect, an embodiment of the present application provides a circuit board, comprising a first connecting layer, a circuit layer and a second connecting layer, the circuit layer is located between the first connecting layer and the second connecting layer, the average grain size of the circuit layer is 50nm-80nm, and the twin crystal density of the circuit layer is .

[0007] In some embodiments, the grains of the circuit layer include first grains and second grains, the first grains are grains with a grain size less than 1μm, the number ratio of the first grains is greater than or equal to 90%, and the second grains are equiaxed crystals, the grain size uniformity of the second grains is less than or equal to 10%.

[0008] In some embodiments, the surface of the circuit layer close to the first connecting layer and / or the second connecting layer is provided with a plurality of protrusions, the average height of all the protrusions is 2μm-3μm, the width of the protrusions is 3μm-5μm, and the aspect ratio of the protrusions is 1-2.5.

[0009] In some embodiments, the first connecting layer comprises a substrate layer and a buffer layer arranged in a stack, the buffer layer is arranged between the substrate layer and the circuit layer, the buffer layer has a coefficient of thermal expansion of 10 ppm / °C to 20 ppm / °C, and a difference between the coefficient of thermal expansion of the buffer layer and the coefficient of thermal expansion of the circuit layer is less than or equal to 5 ppm / °C.

[0010] In some embodiments, a surface of the buffer layer in contact with the circuit layer is bonded by an interfacial adhesive, the surface of the buffer layer in contact with the circuit layer is subjected to a preloading treatment, and the preloading treatment comprises applying a pre-stretching strain of a preset proportion to the surface of the buffer layer in contact with the circuit layer and maintaining for a preset time period, the preset proportion is 5% to 10%, the pre-stretching strain is 5% to 10%, and the preset time period is 20 h to 28 h.

[0011] In some embodiments, one side of the circuit layer close to the buffer layer has a first stress concentration area, a normal projection of the first stress concentration area on a longitudinal section of the circuit layer is configured as a first arc shape, and a radius of curvature of the first arc shape is greater than or equal to 0.5 mm; one side of the buffer layer close to the circuit layer has a second stress concentration area matched with the first stress concentration area, and a normal projection of the second stress concentration area on a longitudinal section of the buffer layer is configured as a second arc shape matched with the first arc shape.

[0012] In some embodiments, the second connecting layer comprises a cover film layer, the cover film layer is attached to the circuit layer, the cover film layer comprises a TPU modified cover film, the TPU modified cover film comprises a PI cover film and a composite material, the composite material comprises a TPU elastomer and BN nanosheets, and a mass fraction of the TPU elastomer in the TPU modified cover film is 20 wt% to 30 wt%.

[0013] In some embodiments, the second connecting layer comprises an electromagnetic shielding film layer, the electromagnetic shielding film layer is located on a side of the cover film layer away from the circuit layer, a tensile strength of the electromagnetic shielding film layer is greater than or equal to 150 MPa, the electromagnetic shielding film layer comprises an insulating layer, a shielding layer and a conductive adhesive film layer arranged in a stack, and the conductive adhesive film layer is located between the cover film layer and the shielding layer.

[0014] In some embodiments, the circuit board comprises an edge protection layer, the edge protection layer is located at an edge portion of the circuit board, and the edge protection layer is located inside the first connecting layer, inside the second connecting layer, between the first connecting layer and the circuit layer, or between the second connecting layer and the circuit layer, the edge protection layer is an elastic sealant, and a thickness of the elastic sealant is 0.3 mm to 0.5 mm.

[0015] Secondly, embodiments of this application provide a method for manufacturing a circuit board, used to manufacture the circuit board as described in the first aspect, comprising: A substrate is provided, the substrate comprising a first interconnect layer and a circuit layer stacked thereon; A second connection layer is disposed on the side of the line layer opposite to the first connection layer.

[0016] The circuit board provided in this application has the following advantages: Since the circuit board includes a first interconnect layer, a circuit layer, and a second interconnect layer, with the circuit layer located between the first and second interconnect layers, and the average grain size of the circuit layer is 50nm~80nm, the twin density of the circuit layer is... Therefore, it not only increases the grain boundary area corresponding to the circuit layer, enhancing the hindering effect of grain boundaries on dislocation movement, but also, the fine grain structure corresponding to the circuit layer can better disperse stress concentration under cyclic loading, delaying crack initiation. Simultaneously, the twins corresponding to the circuit layer can increase grain boundary density, thereby increasing dislocation slip resistance during vibration and delaying microcrack initiation time, thus improving vibration resistance. The circuit board provided in this embodiment has a low risk of fatigue failure under vibration and exhibits strong vibration resistance.

[0017] The advantages of the circuit board manufacturing method provided in this application compared to the prior art can be found in the description of the advantages of the circuit board provided in this application compared to the prior art, which will not be repeated here. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the circuit board structure in one embodiment of this application; Figure 2 This is a flowchart of a method for manufacturing a circuit board in one embodiment of this application; Figure 3 This is a schematic diagram of the circuit board structure in another embodiment of this application; Figure 4 This is a schematic diagram of the circuit board structure in another embodiment of this application; Figure 5 This is a schematic diagram of the circuit board structure in another embodiment of this application.

[0020] The markings in the diagram mean: 10. Line layer; 11. Protrusion; 101. First stress concentration area; 20. Substrate layer; 30. Buffer layer; 301. Second stress concentration region; 40. Covering membrane layer; 50. Electromagnetic shielding film layer; 51. Insulating layer; 52. Shielding layer; 53. Conductive adhesive film layer; 60. Interface adhesive. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0025] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.

[0026] With the development of technology, the application scenarios of circuit boards are becoming more and more widespread. In some application scenarios, circuit boards will face harsh vibration environments for a long time, which will increase the risk of fatigue failure of circuit boards due to vibration.

[0027] For example, in new energy vehicles, the performance of circuit boards affects the safety and reliability of the vehicle's power battery pack, which in turn affects the overall vehicle performance. As a type of circuit board, FPC (Flexible Printed Circuit) has become a key component for signal transmission within the battery pack, including cell voltage acquisition, temperature monitoring, and equalization control, due to its lightweight, high integration, and bendability. A mainstream electric vehicle's battery pack often integrates 50 to 100 FPCs, connecting hundreds of cells to achieve complex electrical interconnections and data interaction. During vehicle operation, the battery pack's circuit boards typically face harsh vibration environments. According to the ISO 16750-3 standard, the battery pack must be able to withstand at least 20G acceleration, 10Hz–2000Hz wideband random vibration, and sinusoidal sweep vibration at specific frequencies. Furthermore, when the vehicle passes over speed bumps or unpaved roads, the instantaneous vibration acceleration can reach over 30G, significantly increasing the likelihood of circuit board fatigue failure.

[0028] In related technologies, when circuit boards are subjected to vibration, the dislocation slip resistance of the circuit layers is relatively low, which leads to a greater risk of fatigue failure and weaker vibration resistance.

[0029] In view of this, this application provides a circuit board and a method for manufacturing the same. The circuit board includes a first interconnect layer, a circuit layer, and a second interconnect layer, with the circuit layer located between the first and second interconnect layers. The average grain size of the circuit layer is 50 nm to 80 nm, and the twin density of the circuit layer is [missing information]. Therefore, it not only increases the grain boundary area corresponding to the circuit layer, enhancing the hindering effect of grain boundaries on dislocation movement, but also, the fine grain structure corresponding to the circuit layer can better disperse stress concentration under cyclic loading, delaying crack initiation. Simultaneously, the twins corresponding to the circuit layer can increase grain boundary density, thereby increasing dislocation slip resistance during vibration and delaying microcrack initiation time, thus improving vibration resistance. The circuit board provided in this embodiment has a low risk of fatigue failure under vibration and exhibits strong vibration resistance.

[0030] Please refer to Figure 1 and Figure 2In a first aspect, embodiments of this application provide a circuit board including a first interconnect layer, a circuit layer 10, and a second interconnect layer. The circuit layer 10 is located between the first interconnect layer and the second interconnect layer. The average grain size of the circuit layer 10 is 50nm~80nm, for example, the average grain size can be 55nm, 60nm, 65nm, 70nm, or 75nm, etc. The twin density of the circuit layer 10 is... For example, the twin density can be , , , , , or wait.

[0031] The circuit board manufacturing method provided in this embodiment includes: S100: A substrate is provided, the substrate including a first interconnect layer and a circuit layer 10 stacked together.

[0032] S200: A second connection layer is provided on the side of the line layer 10 that is away from the first connection layer.

[0033] Specifically, both the second connection layer and the first connection layer can be bonded together with the circuit layer 10.

[0034] The average grain size and twin density of the circuit layer 10 can be kept within the required range by controlling the pulse electroplating parameters and electroplating solution composition during fabrication, adding trace elements to the circuit layer 10, or performing heat treatment on the circuit layer 10. Specific parameters and steps can be adjusted according to the material adaptability of the circuit layer 10. The material of the circuit layer 10 can be copper, aluminum, or silver, etc.

[0035] The average grain size and twin density of the circuit layer 10 can be obtained by slicing. The average grain size can be calculated using X-ray diffractometer (XRD) combined with Scherrer's formula, or directly observed using transmission electron microscopy (TEM). The twin density can be analyzed by backscattered electron diffraction (EBSD) to count the number of twin boundaries per unit area.

[0036] In this embodiment, the average grain size of the circuit layer 10 is limited to 50nm~80nm, which is smaller than the average grain size of traditional circuit layers 10 (usually 300nm or more). Since smaller grain sizes result in larger grain boundary areas, the grain boundaries exert a greater resistance to dislocation movement. Furthermore, the fine grain structure can better disperse stress concentration under cyclic loading, delaying crack initiation and extending the service life of the circuit layer 10. This, in turn, enhances the strength and toughness of the circuit layer 10 material. For the circuit layer 10, this means it is less prone to fracture or damage when subjected to vibration or external impact, improving the reliability and durability of the circuit board. In addition, grain refinement can significantly improve the elongation and plasticity of the metal material, increasing the elongation of the circuit layer 10 to 12%~30%.

[0037] In this embodiment, twinning can increase grain boundary density, thereby increasing dislocation slip resistance during vibration and delaying microcrack initiation time, thus improving vibration resistance.

[0038] The circuit board provided in this embodiment includes a first interconnect layer, a circuit layer 10, and a second interconnect layer. The circuit layer 10 is located between the first interconnect layer and the second interconnect layer, and the average grain size of the circuit layer 10 is 50nm~80nm. The twin density of the circuit layer 10 is... Therefore, it not only increases the grain boundary area corresponding to the circuit layer 10, enhancing the hindering effect of grain boundaries on dislocation movement, but also, the fine grain structure corresponding to the circuit layer 10 can better disperse stress concentration under cyclic loading, delaying crack initiation. Simultaneously, the twins corresponding to the circuit layer 10 can increase grain boundary density, thereby increasing dislocation slip resistance during vibration and delaying microcrack initiation time, thus improving vibration resistance. The circuit board provided in this embodiment has a low risk of fatigue failure under vibration and exhibits strong vibration resistance.

[0039] For example, the material of circuit layer 10 is copper. When fabricating circuit layer 10 by electroplating, a double-pulse electroplating method (forward pulse plus reverse pulse) is used, with a forward pulse width of 10ms and a reverse pulse width of 1ms, and a frequency of [frequency missing]. The current density is High-frequency reverse pulses can suppress abnormal grain growth and refine grains to the nanoscale. Additionally, during electroplating, the plating solution is stirred at a high speed of 200 rpm to reduce concentration polarization and promote uniform nucleation, thereby reducing the grain size corresponding to circuit layer 10 to [a smaller size]. .

[0040] To ensure the twin density of circuit layer 10 is within the required range, the electroplating solution may include: copper sulfate at 25 g / L to 75 g / L, sulfuric acid at 75 g / L to 125 g / L, Cl⁻ at 25 ppm to 75 ppm, and 3-mercapto-1-propanesulfonic acid (MPS) at 10 ppm to 40 ppm. MPS adsorbs onto the copper crystal surface, forming high-density horizontal twin boundaries. Simultaneously, a polyether polyol inhibitor (5 ml / L to 15 ml / L) and a bis(sulfobutyl) disulfide promoter (5 ml / L to 10 ml / L) can be added to inhibit longitudinal grain growth and form a columnar nanotwin structure. Additionally, the electroplating solution may contain... Cr, through grain boundary segregation and pinning, inhibits grain growth, and the twin density can be controlled within a certain range. .

[0041] The elongation rate of the line layer 10 is 12% to 30%. For example, the elongation rate of the line layer 10 can be 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, or 29%.

[0042] This design allows the high elongation rate to withstand greater deformation without fracture when subjected to external tensile or bending forces, thus preventing the circuit layer 10 from breaking due to deformation and improving the overall structural stability and service life. Furthermore, the high elongation rate also allows the circuit layer 10 to maintain a certain degree of ductility after crack initiation, slowing down crack propagation and extending the fatigue life of the circuit layer 10.

[0043] Optionally, the coefficient of thermal expansion of the circuit layer 10 is 18ppm / ℃ to 22ppm / ℃. For example, the coefficient of thermal expansion can be 18.2ppm / ℃, 18.4ppm / ℃, 18.6ppm / ℃, 18.8ppm / ℃, 19ppm / ℃, 19.5ppm / ℃, 20ppm / ℃, 20.5ppm / ℃, 21ppm / ℃, 21.5ppm / ℃, etc.

[0044] This configuration can reduce the accumulation of thermal stress caused by temperature cycling (vibration is often accompanied by temperature changes) in the circuit layer 10, and avoid thermal-mechanical fatigue coupling failure.

[0045] In one example, the circuit layer 10 can be a copper foil layer, which can be obtained by alloying rolled copper foil. Here, the alloying can be used to adjust the coefficient of thermal expansion of the circuit layer 10.

[0046] Optionally, the grains of the circuit layer 10 include a first grain and a second grain. The first grain is a grain with a grain size of less than 1 μm. For example, the grain size can also be any one of 0.95 μm, 0.9 μm, 0.85 μm, 0.8 μm, 0.7 μm, 0.6 μm, or 0.5 μm, or less than or equal to any one of them. The number of first grains accounts for more than or equal to 90%. For example, the number percentage can be any one of 90.5%, 91%, 91.5%, 92%, 92.5%, 93%, 94%, 95%, 96%, 97%, 98%, or 99%, or more than or equal to any one of them. The second grain is an equiaxed grain. The grain size uniformity of the second grain is less than or equal to 10%. For example, the grain size uniformity can be any one of 9.5%, 9%, 8.5%, 8%, 7.5%, 7%, 6%, 5%, 4%, 3%, 2%, or 1%, or less than or equal to any one of them.

[0047] This configuration, with its uniform equiaxed grain distribution, ensures that the mechanical properties of the circuit layer 10 are consistent across all directions. It prevents stress concentration caused by excessively large local grains, allowing the uniform grain structure to distribute stress more evenly during vibration, reducing stress concentration areas and lowering the probability of crack formation. Furthermore, the isotropic nature of the equiaxed grains helps the circuit layer 10 maintain stable performance under vibration loads in different directions.

[0048] It should be noted that the uniformity of the grain size of the second grain is calculated as follows: [(maximum grain size of the second grain ~ minimum grain size of the second grain) / (maximum grain size of the second grain + minimum grain size of the second grain)] * 100%.

[0049] Optionally, the material of the circuit layer 10 includes magnesium, and the mass percentage of magnesium in the circuit layer 10 is 0.2wt% to 0.8wt%, for example, the mass percentage can be 0.25wt%, 0.3wt%, 0.35wt%, 0.4wt%, 0.45wt%, 0.5wt%, 0.55wt%, 0.6wt%, 0.65wt%, 0.7wt%, or 0.75wt%, etc.; and / or, the material of the circuit layer 10 includes titanium, and the mass percentage of titanium in the circuit layer 10 is 1.5wt% to 3wt%, for example, the mass percentage can be 1.6wt%, 1.7wt%, 1.8wt%, 1.9wt%, 2wt%, 2.1wt%, 2.2wt%, 2.3wt%, 2.4wt%, 2.5wt%, 2.6wt%, 2.7wt%, 2.8wt%, or 2.9wt%, etc.

[0050] By adopting the above scheme, magnesium, an alloying element, and / or a grain refiner can be used to increase the nucleation rate and inhibit grain growth by forming a large number of heterogeneous nucleation cores during solidification. This effectively refines the grain size of the circuit layer 10 and improves its vibration resistance.

[0051] Please refer to Figure 3 In some embodiments, the surface of the circuit layer 10 near the first interconnect layer and / or the second interconnect layer has a plurality of protrusions 11. The average height of all the protrusions 11 is 2μm to 3μm. For example, the average height of the protrusions 11 can be 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, 2.8μm, or 2.9μm, etc., and the width of the protrusions 11 is 3μm to 3μm. The width can be 5μm, for example, 3.2μm, 3.4μm, 3.6μm, 3.8μm, 4μm, 4.2μm, 4.4μm, 4.6μm or 4.8μm, etc., and the aspect ratio of the protrusion 11 is 1~2.5, for example, the aspect ratio can be 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, etc.

[0052] By adopting the above scheme, the surface of the circuit layer 10 with multiple protrusions 11 can be roughened. The surfaces of the first connecting layer and / or the second connecting member that are in contact with the roughened surface can be covalently bonded through Schiff base reaction, which can improve the bonding force and the interfacial fracture energy, thereby improving the vibration resistance of the circuit board.

[0053] In one example, the surfaces of the circuit layer 10 near the first and second connection layers can both be roughened as described above, so that the opposite sides of the circuit layer 10 achieve the above-mentioned effects with the first and second connection layers respectively.

[0054] Please refer to Figures 1 to 3In some embodiments, the first connection layer includes a substrate layer 20 and a buffer layer 30 stacked together. The buffer layer 30 is disposed between the substrate layer 20 and the circuit layer 10. The coefficient of thermal expansion of the buffer layer 30 is 10ppm / ℃ to 20ppm / ℃, for example, the coefficient of thermal expansion can be 11ppm / ℃, 12ppm / ℃, 13ppm / ℃, 14ppm / ℃, 15ppm / ℃, 16ppm / ℃, 17ppm / ℃, 18ppm / ℃, or 19ppm / ℃, etc. The difference in the coefficient of thermal expansion between the buffer layer 30 and the circuit layer 10 is less than or equal to 5ppm / ℃. For example, the difference in the coefficient of thermal expansion can be any one of 4.9, 4.8, 4.7, 4.6, 4.5, 4.4, 4.3, 4.2, 4.1, or 4, or less than or equal to any one of them. Alternatively, the difference in the coefficient of thermal expansion can also be any one of 3.5, 3, 2.5, 2, 1.5, or 1, or less than or equal to any one of them.

[0055] By adopting the above scheme, the buffer layer 30 can absorb and disperse the vibration energy from the outside, effectively delay the material fatigue process of the buffer layer 30, so that the circuit board can still maintain good structural integrity under thermal-vibration combined load, and can effectively reduce the thermal stress concentration in the buffer layer 30 and the circuit layer 10 under temperature cycling, greatly avoid fatigue failure caused by interlayer thermal stress, thereby improving the vibration resistance of the circuit board.

[0056] It should be noted that in practical applications, circuit boards often face complex operating conditions involving both mechanical vibration and temperature fluctuations (such as in automotive electronics and aerospace equipment). If the coefficient of thermal expansion of the buffer layer 30 is too high, it will generate significant deformation differences during thermal cycling, leading to localized stress concentration and accelerating fatigue damage under vibration conditions.

[0057] In one example, the buffer layer 30 includes a TPU film with a thickness of 1 μm to 2 μm, for example, the thickness can be 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm or 1.9 μm, etc. The Shore A hardness of the TPU film is 80 to 90, for example, the Shore A hardness can be 81, 82, 83, 84, 85, 86, 87, 88 or 89, etc. The elastic modulus of the TPU film is 0.3 GPa to 0.5 GPa, for example, the elastic modulus can be 0.32 GPa, 0.34 GPa, 0.36 GPa, 0.38 GPa, 0.4 GPa, 0.42 GPa, 0.44 GPa, 0.46 GPa or 0.48 GPa, etc.

[0058] By adopting the above scheme, the buffer layer 30 can maintain shape stability while absorbing energy, avoiding excessive deformation due to excessive softness or stress concentration due to excessive rigidity. Furthermore, the high elasticity of the buffer layer 30 can be used to absorb alternating stress during vibration, thereby reducing the peak value of interface stress.

[0059] It should be noted that TPU (Thermoplastic Polyurethane) material is renowned for its excellent elasticity and shock absorption capabilities. When used as part of the buffer layer 30, even a very thin TPU film (1μm~2μm) can effectively absorb and disperse vibration energy from the outside. This characteristic allows the TPU film to respond quickly to external impacts within a small deformation range, converting mechanical energy into heat energy through internal molecular chain movement, thereby reducing the energy transferred to the underlying structure (such as substrate layer 20 or circuit layer 10) and enhancing the overall vibration resistance of the circuit board. Furthermore, the thinner TPU film retains the high flexibility of the TPU material itself, allowing it to adapt well to the microscopic unevenness of other layer surfaces, ensuring close contact between layers. Under dynamic loads (such as vibration and bending), this flexibility allows the TPU film to undergo appropriate elastic deformation without permanent damage or failure, helping to maintain the overall structural stability and reliability of the circuit board.

[0060] Meanwhile, TPU films with a Shore A hardness of 80-90 are in the range of high hardness but still have good elasticity. They can provide a certain structural support without being too rigid and losing their buffering ability. Therefore, when the circuit board is subjected to vibration or impact, TPU films in this hardness range can absorb energy while maintaining shape stability, avoiding excessive deformation due to excessive softness or stress concentration due to excessive rigidity.

[0061] In addition, the elastic modulus of TPU film is 0.3GPa~0.5GPa, which can be used to absorb alternating stress during vibration and reduce the peak value of interfacial stress.

[0062] Please refer to Figure 3In some embodiments, the surfaces of the buffer layer 30 and the circuit layer 10 in contact are bonded together by an interface adhesive 60. The surfaces of the buffer layer 30 and the circuit layer 10 in contact have undergone a pre-loading treatment. The pre-loading treatment includes applying a preset proportion of pre-tensile strain to the surfaces of the buffer layer 30 and the circuit layer 10 in contact and maintaining it for a preset duration. The preset proportion is 5% to 10%, for example, the preset proportion can be 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, or 9.5%, etc. The pre-tensile strain is 5% to 10%, for example, the pre-tensile strain can be 5%, 6%, 7%, 7.5%, 8%, 9%, or 9.5%, etc. The preset duration is 20h to 28h, for example, the preset duration can be 21h, 22h, 23h, 24h, 25h, 26h, 27h, etc.

[0063] By adopting the above scheme, a more uniform stress field can be established in the adhesive layer before bonding and curing, resulting in a more balanced distribution of deformation and stress under dynamic loads. This helps to delay the initiation of microcracks and improve the durability of the circuit board under long-term vibration. Furthermore, pre-stretching the surface of the buffer layer 30 in contact with the circuit layer 10 by 5% to 10% activates the orientation of its internal polymer chains, enabling it to exhibit better dynamic response characteristics and resilience under subsequent loads. This allows the buffer layer 30 to more effectively disperse energy when encountering vibration or impact, reducing the impact force transmitted to the circuit layer 10 and protecting the circuit from damage.

[0064] It is understood that the protrusions 11 on the surface of the circuit layer 10 are bonded to the interface adhesive 60 to increase the bonding area between the circuit layer 10 and the interface adhesive 60, thereby improving the connection strength between the buffer layer 30 and the circuit layer 10. A preset duration of 20-28 hours ensures that the interface adhesive 60 completes sufficient cross-linking reaction and structural rearrangement under stress induction, thus significantly improving the interface bonding strength. Furthermore, during the manufacturing process, due to material differences or processing technology, certain residual stresses may exist between layers. This embodiment can also promote the gradual release or redistribution of these residual stresses, reducing the risk of structural failure due to stress abrupt changes during subsequent use, thereby improving the reliability of the circuit board under combined operating conditions such as thermal cycling and mechanical shock.

[0065] This embodiment preloads the interface (the surfaces in contact), which allows the interface adhesive 60 to enter the plastic deformation stage earlier, thereby improving its fatigue life under vibration load and increasing the number of cycles.

[0066] For example, the interface adhesive 60 can be acrylic or modified epoxy resin, etc.

[0067] Under dynamic loads (such as vibration and impact), differences in modulus or inconsistencies in deformation in multilayer structures can easily lead to stress concentration in the interface transition region. If the interface is right-angled or sharp, stress will be highly concentrated at certain points, which can easily induce microcracks and propagate to the circuit layer 10, causing electrical performance failure.

[0068] To solve the above problems, please refer to Figure 4 In some embodiments, the side of the circuit layer 10 near the buffer layer 30 has a first stress concentration region 101. The orthographic projection of the first stress concentration region 101 onto the longitudinal section of the circuit layer 10 is configured as a first arc shape, and the radius of curvature of the first arc shape is greater than or equal to 0.5 mm. For example, the radius of curvature can be any one of 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, or greater than or equal to any one of them. The side of the buffer layer 30 near the circuit layer 10 has a second stress concentration region 301 adapted to the first stress concentration region 101. The orthographic projection of the second stress concentration region 301 onto the longitudinal section of the buffer layer 30 is configured as a second arc shape adapted to the first arc shape.

[0069] By adopting the above scheme, the stress distribution can be made more uniform, the local peak stress level can be significantly reduced, thereby delaying the occurrence of cracks and enhancing the durability of the circuit board in complex mechanical environments.

[0070] It should be noted that the longitudinal section of the circuit layer 10 is a section parallel to the arrangement direction of the first and second connecting layers. The longitudinal section of the buffer layer 30 is also a section parallel to the arrangement direction of the first and second connecting layers. It is easy to understand that the stacking direction of the electromagnetic shielding film layer 50, the cover film layer 40, the circuit layer 10, the buffer layer 30, and the substrate layer 20 can be parallel to the direction of this longitudinal section. The protrusions 11 on the surface of the circuit layer 10 can be located on the side of the circuit layer 10 near the buffer layer 30, excluding the first stress concentration area 101.

[0071] In one example, the first stress concentration region 101 and the second stress concentration region 301 can be the corners and / or the areas around vias of the respective circuit layer 10 and buffer layer 30. It is easy to understand that the first and second arcs design the first stress concentration region 101 and the second stress concentration region 301 as arc-shaped transition zones, which can reduce the stress concentration factor (compared to not having this arc-shaped transition zone, the stress concentration factor Kt=σmax / σnominal will decrease from 3.0 to below 1.5, where σmax is the maximum local stress and σnominal is the nominal stress), thereby further improving the vibration resistance of the circuit board.

[0072] Please refer to Figure 1In some embodiments, the substrate layer 20 includes a PI substrate and a PDA layer disposed on the surface of the PI substrate. The PDA layer is located between the PI substrate and the circuit layer 10. The thickness of the PDA layer is 400nm~600nm, for example, the thickness of the PDA layer is 410nm, 420nm, 430nm, 440nm, 450nm, 460nm, 470nm, 480nm, 490nm, 500nm, 510nm, 520nm, 530nm, 540nm, 550nm, 560nm, 570nm, 580nm or 590nm, etc.

[0073] By adopting the above scheme, the PDA layer can play the role of stress buffering and energy dissipation during the stress process, which can ensure sufficient interface modification effect and avoid introducing new stress mismatch problems due to excessive PDA layer thickness.

[0074] It should be noted that PI (Polyimide) is a polymer containing repeating units of imide groups. PDA (Polydopamine) is a black or dark brown polymer made from dopamine.

[0075] Optionally, the elastic modulus of the substrate layer 20 is 2.8 GPa to 3.2 GPa. For example, the elastic modulus can be 2.85 GPa, 2.9 GPa, 2.95 GPa, 3 GPa, 3.05 GPa, 3.1 GPa or 3.15 GPa, etc., and the elastic modulus of the substrate layer 20 increases in a gradient from the side of the substrate layer 20 close to the buffer layer 30 to the side of the substrate layer 20 away from the buffer layer 30.

[0076] This configuration reduces the CTE (Coefficient of Thermal Expansion) difference between the interlayer interfaces in contact with the substrate layer 20 from 33 ppm / ℃ to 2 ppm / ℃.

[0077] It should be noted that CTE refers to the degree of dimensional change of a material when the temperature changes.

[0078] Optionally, the percentage difference in modulus between the side of the substrate layer 20 away from the buffer layer 30 and the side of the substrate layer 20 close to the buffer layer 30 is less than 20%.

[0079] By reducing the difference in modulus between the side of the substrate layer 20 away from the buffer layer 30 and the side of the substrate layer 20 close to the buffer layer 30, the interfacial shear stress during vibration can be reduced (Δσ=E×ε, where Δσ represents the change in shear stress, E represents the elastic modulus, and ε represents the strain; the smaller the difference in E, the lower the interfacial shear stress).

[0080] Please refer to Figures 1 to 5In some embodiments, the second connecting layer includes a cover film layer 40, which is bonded to the circuit layer 10. The cover film layer 40 includes a TPU modified cover film, which includes a PI cover film and a composite material. The composite material includes a TPU elastomer and BN nanosheets. The TPU elastomer accounts for 20wt% to 30wt% of the mass of the TPU modified cover film. For example, this mass percentage can be 21wt%, 22wt%, 23wt%, 24wt%, 25wt%, 26wt%, 27wt%, 28wt%, or 29wt%, etc. The PI cover film accounts for 65wt% to 75wt% of the mass of the TPU modified cover film (e.g., 70wt%).

[0081] By adopting the above solution, the added TPU elastomer can effectively improve the bending performance and bending resistance of the cover film 40, enabling the cover film 40 to better buffer stress and quickly recover its original shape when subjected to external forces (such as vibration, impact, or repeated bending), reducing the risk of microcracks or peeling caused by deformation. In addition, when the circuit board is subjected to vibration or mechanical impact, if the cover film 40 is too rigid, it is easy to cause relative displacement or delamination between it and the underlying circuit layer 10. After adding this proportion of TPU elastomer, the cover film 40 has a certain "flexible bonding" characteristic, which can better deform in tandem with the circuit layer 10 under dynamic loads, reducing the risk of interface stress concentration and cracking, thereby improving the overall stability and durability of the circuit structure.

[0082] It should be noted that BN (Boron Nitride) nanosheets are a two-dimensional material. BN is a covalently bonded compound composed of boron and nitrogen, and it has various crystal structures, including hexagonal boron nitride (h~BN), cubic boron nitride (c~BN), and rhombohedral boron nitride (r~BN).

[0083] In one example, the aspect ratio of the BN nanosheet is greater than or equal to 100. For example, the aspect ratio can be any one of 105, 110, 115, 120, 125, 130, 135, 140, 145, 150 or 200, or greater than or equal to any one of them.

[0084] This configuration allows the BN nanosheets to have a large planar size and a small thickness, enabling the formation of a continuously distributed reinforcing network in the cover film 40. This network structure can effectively improve the tensile strength and bending rigidity of the cover film 40, providing better support when subjected to external vibration or impact, and reducing the risk of deformation and breakage.

[0085] Furthermore, due to their large-area contact characteristics, BN nanosheets with high aspect ratios can better form strong interfacial bonding with TPU elastomers. Under external forces (such as vibration), this structure helps to evenly distribute local stress throughout the entire covering film layer 40, reducing the possibility of stress concentration causing microcracks or delamination failure, thereby improving the overall structural stability and vibration resistance reliability of the circuit board.

[0086] Finally, the combination of BN nanosheets and TPU elastomer enables the covering film 40 to possess both good flexibility and sufficient mechanical strength, effectively addressing structural deformation issues under complex dynamic load environments and preventing loss of support capacity due to excessive flexibility.

[0087] In this embodiment, the Shore A hardness of the TPU elastomer is limited to 85-90, so that the TPU elastomer can maintain sufficient flexibility to absorb vibration energy while providing the necessary rigidity to support structural stability and shape retention. This "combination of rigidity and flexibility" helps to effectively buffer and reduce shock when the circuit board is subjected to external impact or vibration, and also prevent damage caused by excessive deformation.

[0088] Optionally, the mass percentage of BN nanosheets in the TPU modified cover film is 3wt% to 8wt%, for example, this mass percentage can be 3.5wt%, 4wt%, 4.5wt%, 5wt%, 5.5wt%, 6wt%, 6.5wt%, 7wt%, 7.5wt%, etc.

[0089] This design effectively enhances the rigidity and load-bearing capacity of the cover film 40 without significantly affecting its flexibility. This allows the cover film 40 to better resist local deformation and crack propagation when subjected to vibration or impact, thereby improving the overall structural stability and vibration resistance of the circuit board.

[0090] Furthermore, BN nanosheets possess excellent surface activity, enabling them to form strong interfacial adhesion within the capping film 40, thereby enhancing interfacial bonding. Under dynamic loads (such as vibration and bending), this enhanced interfacial bonding helps prevent slippage or delamination between the capping film and the underlying circuit layer 10, maintaining the overall consistency of the multilayer structure. Simultaneously, BN nanosheets can also improve the compatibility between the TPU elastomer and the PI substrate, further enhancing interlayer adhesion.

[0091] Optionally, the elongation at break of the covering membrane 40 is 200% to 300%, for example, the elongation at break can be 210%, 220%, 230%, 240%, 250%, 260%, 270%, 280% or 290%, etc.

[0092] With this configuration, compared to the traditional cover film with a breaking elongation of only 80%, the breaking elongation of the cover film layer 40 in this embodiment is greatly improved, and the low-temperature (40℃) flexibility is enhanced, and it can absorb more alternating stress on the surface of the circuit layer 10 during vibration.

[0093] In one example, the TPU modified cover film is obtained by adding a composite material to the PI cover film. During the production process, a gradient film with a thickness of 40μm~60μm (e.g., 45μm, 50μm, 55μm, etc.) can be prepared by co-extrusion molding to serve as the TPU modified cover film. The surface layer of the gradient film can be the PI cover film, and the inner layer can be the TPU elastomer. In this case, the mass percentage of the TPU elastomer is 20wt%~30wt% (e.g., 30wt%), and the mass percentage of the PI cover film is 65wt%~75wt% (e.g., 70wt%). This can balance temperature resistance (Tg=150℃) and fatigue resistance.

[0094] Optionally, the thermal conductivity of the covering film 40 is 0.6 W / (m·K) to 1.0 W / (m·K), for example, it can be 0.65 W / (m·K), 0.7 W / (m·K), 0.75 W / (m·K), 0.8 W / (m·K), 0.85 W / (m·K), 0.9 W / (m·K), or 0.95 W / (m·K).

[0095] This configuration can significantly improve the thermal conductivity of the covering film layer 40.

[0096] In practical applications, circuit boards often experience frequent temperature changes (such as power-on / power-off and workload fluctuations), which causes the material to expand and contract repeatedly. If the thermal expansion coefficient of the covering film layer is too large, it is prone to fatigue damage due to deformation incoordination under long-term thermal cycling. In particular, it is more likely to cause structural failure when subjected to external vibration or impact.

[0097] To address the aforementioned issues, the coefficient of thermal expansion of the covering film 40 may optionally be 10 ppm / ℃ to 14 ppm / ℃. For example, this coefficient of thermal expansion may be 10.5 ppm / ℃, 11 ppm / ℃, 11.5 ppm / ℃, 12 ppm / ℃, 12.5 ppm / ℃, 13 ppm / ℃, 13.2 ppm / ℃, 13.4 ppm / ℃, 13.5 ppm / ℃, 13.6 ppm / ℃, or 13.8 ppm / ℃, etc.

[0098] This design avoids excessive thermal expansion coefficient of the covering film layer 40, delays material fatigue, and allows the circuit board to maintain good structural integrity and vibration resistance under thermo-mechanical coupling conditions.

[0099] It is understood that when the difference in thermal expansion coefficients between the buffer layer 30 and the circuit layer 10 is less than or equal to 5 ppm / ℃, the embodiments described above related to the specific values ​​of the thermal expansion coefficients of the circuit layer 10 and the cover film layer 40 are optional implementations and not strict limitations of this application. In this embodiment, the thermal expansion coefficient of either the circuit layer 10 or the cover film layer 40 can be taken from the relevant values ​​described in the above embodiments, and the other can be taken from a value that satisfies the difference limit in this embodiment. For example, assuming the thermal expansion coefficient of the circuit layer 10 is 18 ppm / ℃, the thermal expansion coefficient of the cover film layer 40 can be taken from 15 ppm / ℃, 16 ppm / ℃, 17 ppm / ℃, or other values ​​to satisfy the difference limit in this embodiment. In this embodiment, the thermal expansion coefficients of both the circuit layer 10 and the cover film layer 40 can also be made not to take the values ​​limited in the embodiments related to the thermal expansion coefficients of the circuit layer 10 and the cover film layer 40. For example, the thermal expansion coefficient of the circuit layer 10 can be taken from 16 ppm / ℃, and the thermal expansion coefficient of the cover film layer 40 can be taken from 15 ppm / ℃.

[0100] Please refer to Figures 1 to 5 In some embodiments, the second connection layer includes an electromagnetic shielding film layer 50, which is located on the side of the cover film layer 40 away from the circuit layer 10. The tensile strength of the electromagnetic shielding film layer 50 is greater than or equal to 150 MPa. For example, the tensile strength can be any one of 155 MPa, 160 MPa, 165 MPa, 170 MPa, 175 MPa, 180 MPa, 185 MPa, 190 MPa, 195 MPa, 200 MPa, 250 MPa, or 300 MPa, or greater than or equal to any one of them. The electromagnetic shielding film layer 50 includes an insulating layer 51, a shielding layer 52, and a conductive adhesive film layer 53 stacked sequentially. The conductive adhesive film layer 53 is located between the cover film layer 40 and the shielding layer 52.

[0101] By adopting the above scheme, the conformal deformation capability of the electromagnetic shielding film 50 during vibration is improved, which can effectively avoid EMI (Electromagnetic Interference) leakage caused by the breakage of the electromagnetic shielding film 50, and enable the electromagnetic shielding film 50 to have better electromagnetic shielding performance and bending performance.

[0102] It is understood that the electromagnetic shielding film layer 50 provided in this application embodiment has a much lower density than traditional copper foil shielding film and a greater tensile strength.

[0103] In one alternative embodiment, the insulating layer 51 is made of a mixture of graphene and polyester.

[0104] Optionally, the surface resistance of the insulating layer 51 is less than or equal to 5 Ω / sq. For example, the surface resistance can be any one of 4.5 Ω / sq, 4 Ω / sq, 3.5 Ω / sq, 3 Ω / sq, 2.5 Ω / sq, 2 Ω / sq, 1.5 Ω / sq, 1 Ω / sq, or less than or equal to any one of them.

[0105] This design results in a lower surface resistance of the insulating layer 51, a more uniform material distribution within it, and fewer defects, which is beneficial for the interfacial bonding between it and the shielding layer 52. Thus, under vibration or shock conditions, good interfacial bonding effectively prevents interlayer slippage, blistering, or detachment, thereby improving the structural integrity and reliability of the entire electromagnetic shielding film layer 50 under complex operating conditions. Furthermore, it ensures better insulation performance while exhibiting better elongation at break, enhancing resistance to deformation.

[0106] The shielding layer 52 includes multiple layers of silver alloy nanowires pressed onto the surface of the insulating layer 51 facing away from the covering film layer 40. The diameter of the silver alloy nanowires is 40nm~60nm, for example, the diameter can be 42nm, 44nm, 46nm, 48nm, 50nm, 52nm, 54nm, 56nm, 58nm, etc. The mass percentage of the silver alloy nanowires in the shielding layer 52 is 20wt%~40wt%, for example, the mass percentage can be 22wt%, 24wt%, 26wt%, 28wt%, 30wt%, 32wt%, 34wt%, 36wt%, 38wt%, etc.

[0107] By adopting the above scheme, the nanoscale silver alloy nanowires can have a higher aspect ratio and better flexibility. When subjected to external vibration or mechanical deformation, these fine and flexible silver alloy nanowires can undergo certain displacement and deformation within the shielding layer 52 without immediately breaking, thus maintaining the continuity and integrity of the shielding function. Simultaneously, the shielding layer 52 possesses sufficient mechanical strength to support the shielding function, and allows a portion of the silver alloy nanowires to be embedded to a certain extent into the surface of the insulating layer 51, forming an anchoring effect and preventing interlayer peeling or debonding caused by vibration. It can effectively disperse stress when subjected to external pressure or impact, avoiding damage caused by localized stress overload. Furthermore, within a set mass percentage range, the silver alloy nanowires can construct a robust yet somewhat elastic network structure within the shielding layer 52, helping to absorb and buffer externally applied mechanical energy, reducing the impact on the underlying structure, and thus improving vibration resistance.

[0108] It should be noted that the shielding layer 52 can be formed by pressing multilayer silver alloy nanowires onto the surface of the insulating layer 51.

[0109] Optionally, the conductive adhesive film layer 53 may be made of modified epoxy resin, and the thickness of the conductive adhesive film layer 53 may be 3μm to 5μm, for example, the thickness may be 3.2μm, 3.4μm, 3.6μm, 3.8μm, 4μm, 4.2μm, 4.4μm, 4.6μm or 4.8μm, etc.

[0110] With this configuration, the conductive adhesive film layer 53 of appropriate thickness can ensure sufficient adhesion while avoiding unevenness or local stress concentration caused by excessive thickness, and avoid losing the necessary buffering effect due to excessive thinness, thereby improving the impact resistance of the entire circuit board.

[0111] The conductive adhesive film layer 53 includes conductive particles. The conductive particles are made of silver-plated gold and have a particle size of 1μm to 3μm. For example, the particle size can be 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2μm, 2.2μm, 2.4μm, 2.6μm, or 2.8μm, etc.

[0112] By adopting the above scheme, after adding conductive particles to the material of the conductive adhesive film layer 53, the conductive particles can play a role in "bridging" or "stress buffering". When subjected to external forces (such as vibration, impact or bending), they can disperse local stress concentration, thereby delaying the initiation and propagation of microcracks and improving the fracture toughness and fatigue resistance of the conductive adhesive film layer 53 under dynamic loads. In addition, the silver-coated gold conductive particles have good conductivity and a certain elastic modulus. In the conductive adhesive film layer 53, they can not only form a stable conductive path (for grounding or shielding), but also absorb external vibration energy to a certain extent, thereby achieving a synergistic effect of conduction and buffering.

[0113] It should be noted that silver-coated gold conductive particles are composite particles with a metal coating on the surface and another metal inside (such as a gold core and a silver shell), and they have a certain degree of plasticity and ductility.

[0114] Optionally, the mass percentage of conductive particles in the conductive adhesive film layer 53 is 30wt% to 50wt%, for example, the mass percentage can be 32wt%, 34wt%, 36wt%, 38wt%, 40wt%, 42wt%, 44wt%, 46wt%, or 48wt%, etc.

[0115] This configuration allows conductive particles to form a dense distribution network within the conductive adhesive film layer 53, effectively hindering crack propagation paths, absorbing and dispersing external impact energy, and enhancing the overall tensile strength and fracture toughness of the material. Consequently, the conductive adhesive film layer 53 is less prone to brittle fracture or delamination under vibration or impact, improving the overall structural stability and vibration resistance reliability of the circuit board. Furthermore, due to the high thermal conductivity of silver-plated gold conductive particles, adding 30wt%~50wt% of these particles to the conductive adhesive film layer 53 significantly improves its thermal conductivity, resulting in a more uniform heat distribution. This reduces thermal stress between different layers, minimizing deformation and fatigue damage caused by temperature changes, thereby indirectly improving the vibration resistance life of the circuit board under complex operating conditions.

[0116] Optionally, the elastic modulus of the conductive adhesive film layer 53 is 1.0 GPa to 1.4 GPa. For example, the elastic modulus of the conductive adhesive film layer 53 can be 1.0 GPa, 1.2 GPa, 1.3 GPa or 1.4 GPa, etc.

[0117] This configuration allows the conductive adhesive film layer 53 to effectively absorb vibration energy.

[0118] It should be noted that when a second connection layer is provided on the side of the circuit layer 10 away from the first connection layer, a cover film layer 40 and an electromagnetic shielding film layer 50 can be provided in sequence.

[0119] Please refer to Figures 1 to 5 In some embodiments, the circuit board includes an edge protection layer located at the edge of the circuit board. The edge protection layer is located inside the first connection layer, inside the second connection layer, between the first connection and the circuit layer 10, or between the second connection and the circuit layer 10. The edge protection layer is an elastic sealant with a thickness of 0.3mm to 0.5mm. For example, the thickness can be 0.31mm, 0.32mm, 0.33mm, 0.34mm, 0.35mm, 0.36mm, 0.37mm, 0.38mm, 0.39mm, 0.4mm, 0.41mm, 0.42mm, 0.43mm, 0.44mm, 0.45mm, 0.46mm, 0.47mm, 0.48mm, or 0.49mm, etc.

[0120] By adopting the above solution, the edges of the circuit board can be prevented from peeling off first during vibration, which can ensure sufficient buffering capacity and prevent the overall thickness and assembly accuracy of the circuit board from being affected by excessively thick elastic sealant.

[0121] It is understood that, for any two adjacent layers among the electromagnetic shielding film layer 50, the cover film layer 40, the circuit layer 10, the buffer layer 30, and the substrate layer 20, an edge protection layer is applied to the junction of the side of one of the two adjacent layers and the other. The elastic sealant can be acrylic or modified epoxy resin, etc.

[0122] In one example, the edge protection layer can also be applied to the ends of the lines in the circuit layer 10. This embodiment can further prevent the circuit board edges from peeling off first during vibration.

[0123] See one example. Figure 5 The aforementioned circuit board can be a double-sided structure, meaning it can include two boards. Each board includes the electromagnetic shielding film layer 50, cover film layer 40, circuit layer 10, buffer layer 30, and substrate layer 20, which are stacked sequentially. The substrate layers 20 of the two boards can be stacked, such that the electromagnetic shielding film layer 50, cover film layer 40, circuit layer 10, and buffer layer 30 of each board are symmetrically arranged about the substrate layer 20. In another example, each board can also include the electromagnetic shielding film layer 50, cover film layer 40, circuit layer 10, and buffer layer 30, which are stacked sequentially, with the buffer layers 30 of the two boards stacked on opposite sides of the substrate layer 20.

[0124] To better illustrate the beneficial effects of the circuit board provided in the embodiments of this application, some embodiments are described below.

[0125] Example 1: A circuit board includes an electromagnetic shielding film layer 50, a cover film layer 40, a circuit layer 10, a buffer layer 30, and a substrate layer 20, which are sequentially stacked. In a sliced ​​state, the average grain size of the circuit layer 10 is 54 nm, and the twin density of the circuit layer 10 is [missing information]. The elongation of the circuit layer 10 is 24%; the material of the cover film layer 40 includes a TPU modified cover film, which is obtained by adding a composite material to the PI cover film. The composite material includes TPU elastomer and BN nanosheets. The mass percentage of TPU elastomer in the TPU modified cover film is 28wt%, and the aspect ratio of BN nanosheets is 122; the coefficient of thermal expansion of the buffer layer 30 is 14ppm / ℃, and the coefficient of thermal expansion of the circuit layer 10 is 18ppm / ℃; the substrate layer 20 is obtained by coating a PDA layer with a thickness of 500nm on the surface of the PI substrate.

[0126] Example 2: A circuit board includes an electromagnetic shielding film layer 50, a cover film layer 40, a circuit layer 10, a buffer layer 30, and a substrate layer 20, which are sequentially stacked. In a sliced ​​state, the average grain size of the circuit layer 10 is 63 nm, and the twin density of the circuit layer 10 is [missing information]. The elongation of the circuit layer 10 is 21%; the material of the cover film layer 40 includes a TPU modified cover film, which is obtained by adding composite materials to the PI cover film. The composite materials include TPU elastomer and BN nanosheets. The mass percentage of TPU elastomer in the TPU modified cover film is 23wt%, and the aspect ratio of BN nanosheets is 108; the coefficient of thermal expansion of the buffer layer 30 is 14ppm / ℃, and the coefficient of thermal expansion of the circuit layer 10 is 18ppm / ℃; the substrate layer 20 is obtained by coating a PDA layer with a thickness of 520nm on the surface of the PI substrate.

[0127] Example 3: A circuit board includes an electromagnetic shielding film layer 50, a cover film layer 40, a circuit layer 10, a buffer layer 30, and a substrate layer 20, which are sequentially stacked. In a sliced ​​state, the average grain size of the circuit layer 10 is 54 nm, and the twin density of the circuit layer 10 is [missing information]. The elongation of the circuit layer 10 is 24%; the cover film layer 40 is made of TPU modified cover film, which is obtained by adding composite materials to the PI cover film. The composite materials include TPU elastomer and BN nanosheets. The mass percentage of TPU elastomer in the TPU modified cover film is 28wt%, and the aspect ratio of BN nanosheets is 122; the coefficient of thermal expansion of the buffer layer 30 is 14ppm / ℃, and the coefficient of thermal expansion of the circuit layer 10 is 18ppm / ℃; the substrate layer 20 is obtained by coating a 500nm thick PDA layer on the surface of the PI substrate; the electromagnetic shielding film layer 50 includes an insulating layer 51, a shielding layer 52, and an adhesive film layer stacked sequentially. The adhesive film layer is relatively smaller than the insulating layer 51. Closer to the covering film layer 40, the electromagnetic shielding film layer 50 has a tensile strength of 156 MPa; the insulating layer 51 is made of a mixture of graphene and polyester, and its surface resistivity is 4.7 Ω / sq; the shielding layer 52 is formed by pressing multiple layers of silver alloy nanowires onto one surface of the insulating layer 51, the diameter of the silver alloy nanowires is 49 nm, and the mass percentage of the silver alloy nanowires in the shielding layer 52 is 32 wt%; the adhesive film layer has a thickness of 4.1 μm and is made of modified epoxy resin; the adhesive film layer includes conductive particles, which are made of silver-coated gold, have a particle size of 2.2 μm, and the mass percentage of the conductive particles in the adhesive film layer is 37 wt%; the elastic modulus of the adhesive film layer is 1.3 GPa.

[0128] Example 4: A circuit board includes an electromagnetic shielding film layer 50, a cover film layer 40, a circuit layer 10, a buffer layer 30, and a substrate layer 20, which are sequentially stacked. In a sliced ​​state, the average grain size of the circuit layer 10 is 54 nm, and the twin density of the circuit layer 10 is [missing information]. The elongation of the circuit layer 10 is 24%; the material of the cover film layer 40 includes a TPU modified cover film, which is obtained by adding composite materials to the PI cover film. The composite materials include TPU elastomer and BN nanosheets. The mass percentage of the TPU elastomer in the TPU modified cover film is 28wt%, and the aspect ratio of the BN nanosheets is 122; the coefficient of thermal expansion of the buffer layer 30 is 14ppm / ℃, and the coefficient of thermal expansion of the circuit layer 10 is 18ppm / ℃; the substrate layer 20 is obtained by coating a 500nm thick PDA layer on the surface of the PI substrate; the Shore A hardness of the TPU elastomer is 89; the mass percentage of the BN nanosheets in the TPU modified cover film is 7wt%; the elongation at break of the cover film layer 40 is 250%; the thermal conductivity of the cover film layer 40 is 0.8W / (m・K); and the coefficient of thermal expansion of the cover film layer 40 is 13ppm / ℃.

[0129] In summary, the embodiments of this application have the following beneficial effects: The circuit board provided in this embodiment includes an electromagnetic shielding film layer 50, a cover film layer 40, a circuit layer 10, a buffer layer 30, and a substrate layer 20 stacked sequentially. In the sliced ​​state, the average grain size of the circuit layer 10 is 50nm~80nm, and the twin density of the circuit layer 10 is... The elongation of the circuit layer 10 is 12% to 30%; the coefficient of thermal expansion of the buffer layer 30 is 10ppm / ℃ to 20ppm / ℃, and the difference between the coefficients of thermal expansion of the buffer layer 30 and the circuit layer 10 is less than or equal to 5ppm / ℃; the substrate layer 20 is obtained by coating a PDA layer with a thickness of 400nm to 600nm on the surface of the PI substrate; the material of the cover film layer 40 includes a TPU modified cover film, which is obtained by adding composite materials to the PI cover film. The composite materials include TPU elastomer and BN nanosheets. The mass ratio of TPU elastomer in the TPU modified cover film is 20wt% to 30wt%, and the aspect ratio of BN nanosheets is greater than or equal to 100, thereby improving the dislocation slip resistance of the circuit when subjected to vibration and enhancing the vibration resistance performance.

[0130] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A circuit board, characterized in that, It includes a first interconnect layer, a circuit layer, and a second interconnect layer, wherein the circuit layer is located between the first interconnect layer and the second interconnect layer, the average grain size of the circuit layer is 50nm~80nm, and the twin density of the circuit layer is [missing information]. .

2. The circuit board according to claim 1, characterized in that, The circuit layer includes a first grain and a second grain. The first grain is a grain with a size of less than 1 μm, and the number of the first grains accounts for more than or equal to 90%. The second grain is an equiaxed grain, and the grain size uniformity of the second grain is less than or equal to 10%.

3. The circuit board according to claim 1, characterized in that, The circuit layer has multiple protrusions on its surface near the first connection layer and / or the second connection layer. The average height of all the protrusions is 2μm to 3μm, the width of the protrusions is 3μm to 5μm, and the aspect ratio of the protrusions is 1 to 2.

5.

4. The circuit board according to claim 1, characterized in that, The first connecting layer includes a substrate layer and a buffer layer stacked together. The buffer layer is disposed between the substrate layer and the circuit layer. The coefficient of thermal expansion of the buffer layer is 10ppm / ℃ to 20ppm / ℃, and the difference between the coefficients of thermal expansion of the buffer layer and the circuit layer is less than or equal to 5ppm / ℃.

5. The circuit board according to claim 4, characterized in that, The surfaces of the buffer layer and the circuit layer that are in contact are bonded together by an interface adhesive. The surfaces of the buffer layer and the circuit layer that are in contact have undergone a pre-loading treatment, which includes applying a preset proportion of pre-tensile strain to the surfaces of the buffer layer and the circuit layer and maintaining it for a preset time. The preset proportion is 5% to 10%, the pre-tensile strain is 5% to 10%, and the preset time is 20h to 28h.

6. The circuit board according to claim 4, characterized in that, The side of the circuit layer near the buffer layer has a first stress concentration region, the orthographic projection of the first stress concentration region onto the longitudinal section of the circuit layer is constructed into a first arc shape, the radius of curvature of the first arc shape being greater than or equal to 0.5 mm; the side of the buffer layer near the circuit layer has a second stress concentration region adapted to the first stress concentration region, the orthographic projection of the second stress concentration region onto the longitudinal section of the buffer layer is constructed into a second arc shape adapted to the first arc shape.

7. The circuit board according to claim 1, characterized in that, The second connecting layer includes a cover film layer, which is bonded to the circuit layer. The cover film layer includes a TPU modified cover film, which includes a PI cover film and a composite material. The composite material includes a TPU elastomer and BN nanosheets. The mass percentage of the TPU elastomer in the TPU modified cover film is 20wt% to 30wt%.

8. The circuit board according to claim 7, characterized in that, The second connection layer includes an electromagnetic shielding film layer, which is located on the side of the cover film layer away from the circuit layer, and the tensile strength of the electromagnetic shielding film layer is greater than or equal to 150 MPa; the electromagnetic shielding film layer includes an insulating layer, a shielding layer and a conductive adhesive film layer stacked in sequence, and the conductive adhesive film layer is located between the cover film layer and the shielding layer.

9. The circuit board according to any one of claims 1 to 8, characterized in that, The circuit board includes an edge protection layer located at the edge of the circuit board. The edge protection layer is located inside the first connection layer, inside the second connection layer, between the first connection and the circuit layer, or between the second connection and the circuit layer. The edge protection layer is an elastic sealant with a thickness of 0.3mm to 0.5mm.

10. A method for manufacturing a circuit board, characterized in that, For manufacturing a circuit board as described in any one of claims 1 to 9, comprising: A substrate is provided, the substrate comprising a first interconnect layer and a circuit layer stacked thereon; A second connection layer is disposed on the side of the line layer opposite to the first connection layer.

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