Flash memory device and preparation method thereof
By forming titanium and nickel-platinum alloy layers in flash memory devices and generating nickel-platinum silicide and titanium silicide layers through thermal annealing, the problems of over-etching or thinning of nickel self-aligned silicides are solved, contact resistance is reduced, and the electrical performance of the devices is improved.
Patent Information
- Application Number
- CN202511159001.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-18
- Publication Date
- 2025-11-28
AI Technical Summary
In the prior art, when forming contact holes for NAND flash memory devices at the 55nm node, the nickel self-aligned silicide is prone to over-etching or becoming too thin, resulting in increased contact resistance or complete mis-etching, which affects device performance and electrical performance.
A titanium layer and a nickel-platinum alloy layer are formed on the surface of the storage area substrate on the flash memory cell side. A nickel-platinum silicide layer and a titanium silicide layer are generated through a thermal annealing process. These serve as etching sacrificial layers to prevent over-etching of the nickel-platinum silicide layer. The contact resistance is optimized through two thermal annealing processes.
This effectively avoids the problems of thin nickel-platinum silicide layers or complete etching errors, reduces contact resistance, improves device electrical performance, and enhances device reliability and electrical performance.
Smart Images
Figure CN121038280A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a flash memory device and its fabrication method. Background Technology
[0002] NAND Flash memory devices are currently the mainstream non-volatile storage devices, widely used in USB flash drives, solid-state drives (SSDs), mobile phone storage, etc. Their structure is based on NAND logic gates, featuring high density, low cost, and erasability / rewriting capability.
[0003] In 55nm NAND flash memory devices, before forming the interlayer insulating dielectric layer and etching the interlayer insulating dielectric layer to form contact holes, a nickel self-aligned silicide is formed on the substrate surface. The nickel self-aligned silicide acts as an etch barrier layer. Due to the high aspect ratio of the contact holes formed by etching the interlayer insulating dielectric layer (which opens the ion-doped region on the substrate surface), the etching window of the contact holes is narrow, making it easy to over-etch. This can lead to the complete mis-etching or under-etching of the nickel self-aligned silicide at the bottom of the contact hole. Under-etching of the nickel self-aligned silicide will cause an increase in contact resistance, affecting device performance; complete mis-etching of the nickel self-aligned silicide will cause bin631 failure. Summary of the Invention
[0004] This application provides a flash memory device and its fabrication method, which can solve at least one of the following problems: the contact resistance increases due to the thinness of the nickel self-aligned silicide at the bottom of the contact hole, affecting device performance; and the device's electrical performance fails due to complete mis-etching of the nickel self-aligned silicide at the bottom of the contact hole.
[0005] On one hand, embodiments of this application provide a method for fabricating a flash memory device, including:
[0006] A substrate is provided, the substrate including at least a storage region, and at least one flash memory cell is formed on the substrate of the storage region;
[0007] A titanium layer is formed on the substrate surface of the storage area on the side of the flash memory cell;
[0008] A nickel-platinum alloy layer of first thickness is formed, the first thickness of the nickel-platinum alloy layer covering the titanium layer;
[0009] A titanium nitride layer is formed, which covers a nickel-platinum alloy layer of the first thickness, wherein the stacked substrate, the titanium layer, the nickel-platinum alloy layer of the first thickness and the titanium nitride layer constitute a first stacked structure;
[0010] performing a thermal annealing process on the semiconductor structure after forming the first stack structure, so as to make the first stack structure transform into a second stack structure, wherein the second stack structure comprises: the substrate, a nickel platinum silicide layer, a titanium silicide layer, a nickel platinum alloy layer with a second thickness, and the titanium nitride layer, wherein the second thickness is less than the first thickness;
[0011] removing the titanium nitride layer and the nickel platinum alloy layer with the second thickness in the second stack structure;
[0012] performing a thermal annealing process on the semiconductor structure after removing the titanium nitride layer in the second stack structure.
[0013] Optionally, in the preparation method of the flash memory device, the thickness of the titanium layer is 10 angstroms to 50 angstroms.
[0014] Optionally, in the preparation method of the flash memory device, the thickness of the nickel platinum alloy layer with the first thickness is 100 angstroms to 300 angstroms.
[0015] Optionally, in the preparation method of the flash memory device, the thickness of the titanium nitride layer is 50 angstroms to 150 angstroms.
[0016] Optionally, in the preparation method of the flash memory device, in the second stack structure, the thickness of the titanium silicide layer is 15 angstroms to 75 angstroms.
[0017] Optionally, in the preparation method of the flash memory device, in the second stack structure, the thickness of the nickel platinum silicide layer is 150 angstroms to 450 angstroms.
[0018] Optionally, in the preparation method of the flash memory device, before forming the titanium layer on the substrate surface of the storage area on the side of the flash memory cell according to the self-alignment characteristic, the preparation method of the flash memory device further comprises: removing the natural oxide layer on the substrate surface of the storage area on the side of the flash memory cell by a SiCoNi etching process.
[0019] Optionally, in the preparation method of the flash memory device, after removing the natural oxide layer on the substrate surface of the storage area on the side of the flash memory cell, and before forming the titanium layer on the substrate surface of the storage area on the side of the flash memory cell, the preparation method of the flash memory device further comprises: performing a degassing treatment on the semiconductor structure after removing the natural oxide layer.
[0020] Optionally, in the preparation method of the flash memory device, after performing the thermal annealing process on the semiconductor structure after removing the titanium nitride layer in the second stack structure, the preparation method of the flash memory device further comprises:
[0021] An interlayer insulating dielectric layer is formed, which covers the titanium silicide layer in the second stacked structure;
[0022] The interlayer insulating dielectric layer is etched and stopped on the surface of the titanium silicide layer to form a contact hole;
[0023] A metal layer is filled into the contact hole to form a conductive plug.
[0024] On the other hand, embodiments of this application also provide a flash memory device, including:
[0025] A substrate, the substrate comprising at least a storage region, on which at least one flash memory cell is formed;
[0026] A nickel-platinum silicide layer is located on the substrate surface of the storage region on the side of the flash memory cell;
[0027] A titanium silicide layer, which covers the nickel-platinum silicide layer.
[0028] The technical solution of this application has at least the following advantages:
[0029] In the method for fabricating a flash memory device provided in this application, a first stacked structure is formed on the substrate surface of the storage area on the flash memory cell side. The first stacked structure consists of a titanium layer, a nickel-platinum alloy layer of a first thickness, and a titanium nitride layer. Then, a thermal annealing process is performed to transform the first stacked structure into a second stacked structure. The second stacked structure includes a stacked substrate, a nickel-platinum silicide layer, a titanium silicide layer, a nickel-platinum alloy layer of a second thickness (the unreacted remaining nickel-platinum alloy layer), and a titanium nitride layer. Next, the titanium nitride layer and the unreacted remaining nickel-platinum alloy layer in the second stacked structure are removed. Finally, a thermal annealing process is performed again. This application forms a titanium layer and a nickel-platinum alloy layer on the substrate surface, and after thermal annealing, the substrate, titanium layer, and nickel-platinum alloy layer react to generate a nickel-platinum silicide layer and a titanium silicide layer in the second stacked structure. The titanium silicide layer can serve as an etching sacrificial layer for subsequent contact hole etching processes, avoiding the situation where excessive etching in subsequent contact hole etching processes leads to an underly thin nickel-platinum silicide layer, resulting in increased contact resistance and affecting device performance. It also avoids the situation where excessive etching in subsequent contact hole etching processes leads to the complete erroneous etching of the nickel-platinum silicide layer, resulting in device electrical performance failure. Thus, the device electrical performance is improved and the contact resistance is reduced. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0031] Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention;
[0032] Figures 2-4 This is a schematic diagram of the semiconductor structure in each process step of fabricating a flash memory device according to an embodiment of the present invention;
[0033] The reference numerals in the attached figures are explained as follows:
[0034] 10 - Substrate, 20 - Titanium layer, 31 - Nickel-platinum alloy layer of first thickness, 32 - Nickel-platinum alloy layer of second thickness, 40 - Titanium nitride layer, 50 - Nickel-platinum silicide layer, 60 - Titanium silicide layer. Detailed Implementation
[0035] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0036] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0038] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0039] This application provides a method for fabricating a flash memory device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention. The method for fabricating the flash memory device includes:
[0040] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the formation of the titanium nitride layer according to an embodiment of this application. A substrate 10 is provided, the substrate 10 including at least a storage region, and at least one flash memory cell is formed on the substrate 10 of the storage region.
[0041] In this embodiment, the substrate 10 is a silicon substrate.
[0042] Preferably, before forming a titanium layer on the substrate surface of the storage region on the flash memory cell side according to the self-alignment characteristics (step S2), the method for fabricating the flash memory device may further include: removing the natural oxide layer on the surface of the substrate 10 of the storage region on the flash memory cell side by means of a SiCoNi etching process.
[0043] Furthermore, after removing the natural oxide layer on the substrate surface of the storage area on the flash memory cell side, and before forming a titanium layer on the substrate surface of the storage area on the flash memory cell side (step S2), the method for fabricating the flash memory device may further include: performing a degassing treatment on the semiconductor structure after removing the natural oxide layer to remove moisture impurities from the surface of the semiconductor structure.
[0044] Then, proceed to step S2: Continue to refer to Figure 2 A titanium layer 20 is formed on the surface of the substrate 10 of the storage area on the side of the flash memory cell in an environment without the introduction of nitrogen gas.
[0045] In this embodiment, the thickness of the titanium layer 20 is 10 angstroms to 50 angstroms.
[0046] Next, proceed to step S3: Continue to refer to Figure 2 A nickel-platinum alloy layer 31 of first thickness is formed, which covers the titanium layer 20.
[0047] Preferably, the thickness of the first nickel-platinum alloy layer 31 is 100 angstroms to 300 angstroms.
[0048] Next, proceed to step S4: Continue to refer to Figure 2In a nitrogen-filled environment, a titanium nitride layer 40 is formed, which covers the nickel-platinum alloy layer 31 of the first thickness. The stacked substrate 10, the titanium layer 20, the nickel-platinum alloy layer 31 of the first thickness and the titanium nitride layer 40 constitute a first stacked structure.
[0049] Preferably, the thickness of the titanium nitride layer 40 is 50 angstroms to 150 angstroms.
[0050] The titanium nitride layer 40 protects the underlying nickel-platinum alloy layer from oxidation during the annealing process, ensuring the purity of the silicide reaction. Furthermore, the titanium nitride layer 40 can also prevent nickel atoms from diffusing upwards to the surface, avoiding the formation of an unintended high-resistivity phase.
[0051] Further, proceed to step S5: Refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the second stacked structure according to an embodiment of this application. A thermal annealing process is performed on the semiconductor structure after the formation of the first stacked structure to transform the first stacked structure into the second stacked structure. The annealing temperature is 450°C to 750°C. The second stacked structure includes: the stacked substrate 10, nickel-platinum silicide layer 50, titanium silicide layer 60, nickel-platinum alloy layer 32 of second thickness, and titanium nitride layer 40, wherein the second thickness is less than the first thickness.
[0052] During the annealing process in step S5, the original first stacked structure is transformed into: a stacked substrate 10, a nickel-platinum silicide layer 50, a titanium silicide layer 60, a nickel-platinum alloy layer 32 of a second thickness, and a titanium nitride layer 40. Specifically, silicon atoms in the substrate 10 diffuse into the titanium layer 20 to obtain the titanium silicide layer (TiSi) 60, and nickel atoms in the nickel-platinum alloy layer 31 diffuse through the titanium layer 20 to the interface of the substrate 10, reacting with the silicon substrate to generate a nickel-platinum silicide layer (NiPtSi) 50. Finally, the nickel-platinum silicide layer 50, the titanium silicide layer 60, the nickel-platinum alloy layer of a second thickness (the unreacted remaining nickel-platinum alloy layer), and the titanium nitride layer 40 are stacked sequentially from bottom to top on the surface of the substrate 10.
[0053] The nickel-platinum alloy layer 32 of the second thickness in the second stacked structure is the nickel-platinum alloy layer in the first stacked structure that has not reacted with the substrate, so the second thickness is less than the first thickness.
[0054] Preferably, in the nickel-platinum silicide layer 50, platinum allows the silicide to maintain a stable NiSi phase at high temperatures (>700°C), preventing its transformation into the high-resistivity NiSi2. Therefore, the resulting nickel-platinum silicide layer 50 can reduce contact resistance. Furthermore, the titanium silicide layer 60 can suppress the "silicon consumption" effect, reducing excessive etching of the underlying silicon substrate. In this embodiment, the nickel-platinum silicide layer 50 and the titanium silicide layer 60 constitute a self-aligned metal silicide.
[0055] In this embodiment, in the second stacked structure, the thickness of the titanium silicide layer 60 is 15 angstroms to 75 angstroms.
[0056] Furthermore, in the second stacked structure, the thickness of the nickel-platinum silicide layer 50 is 150 angstroms to 450 angstroms.
[0057] Next, proceed to step S6: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after removing the titanium nitride layer and the second thickness of the nickel-platinum alloy layer according to an embodiment of this application, wherein the titanium nitride layer 40 and the second thickness of the nickel-platinum alloy layer 32 in the second stacked structure are removed.
[0058] Finally, step S7 is executed: a thermal annealing process is performed on the semiconductor structure after removing the titanium nitride layer 40 in the second stacked structure, wherein the annealing temperature is 750℃~950℃. The main function of this (second) thermal annealing process is to transform the high-resistivity metal silicide (nickel-platinum silicide layer 50 and titanium silicide layer 60) into low-resistivity metal silicide (nickel-platinum silicide layer 50 and titanium silicide layer 60), that is, the main function of this (second) thermal annealing process is to reduce the resistivity of the nickel-platinum silicide layer 50 and titanium silicide layer 60.
[0059] Furthermore, after performing a thermal annealing process on the semiconductor structure after removing the titanium nitride layer in the second stacked structure, the method for fabricating the flash memory device may further include:
[0060] Step S8.1: Form an interlayer insulating dielectric layer (not shown), which covers the titanium silicide layer 60 in the second stacked structure;
[0061] Step S8.2: Etch the interlayer insulating dielectric layer and stop at the surface of the titanium silicide layer 60 to form a contact hole;
[0062] Step S8.3: Fill the contact hole with a metal layer to form a conductive plug, which contacts the titanium silicide layer 60.
[0063] In this application, by forming a titanium layer and a nickel-platinum alloy layer on the substrate surface, and after the first thermal annealing, the substrate, titanium layer, and nickel-platinum alloy layer react to generate a nickel-platinum silicide layer and a titanium silicide layer in the second stacked structure. The titanium silicide layer can serve as an etching sacrificial layer for the subsequent contact hole etching process, avoiding the situation where excessive etching in the subsequent contact hole etching process leads to an underly thin nickel-platinum silicide layer, resulting in increased contact resistance and affecting device performance. It also avoids the situation where excessive etching in the subsequent contact hole etching process leads to the complete erroneous etching of the nickel-platinum silicide layer, resulting in device electrical performance failure. Thus, the device electrical performance is improved and the contact resistance is reduced.
[0064] Based on the same inventive concept, this application also provides a flash memory device, see reference. Figure 4 The flash memory device includes:
[0065] Substrate 10, the substrate including at least a storage region, on which at least one flash memory cell is formed;
[0066] A nickel-platinum silicide layer 50 is located on the surface of the substrate 10 of the storage area on the side of the flash memory cell;
[0067] A titanium silicide layer 60 covers the nickel-platinum silicide layer 50.
[0068] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a flash memory device, characterized in that, include: A substrate is provided, the substrate including at least a storage region, and at least one flash memory cell is formed on the substrate of the storage region; A titanium layer is formed on the substrate surface of the storage area on the side of the flash memory cell; A nickel-platinum alloy layer of first thickness is formed, the first thickness of the nickel-platinum alloy layer covering the titanium layer; A titanium nitride layer is formed, which covers a nickel-platinum alloy layer of the first thickness, wherein the stacked substrate, the titanium layer, the nickel-platinum alloy layer of the first thickness and the titanium nitride layer constitute a first stacked structure; A thermal annealing process is performed on the semiconductor structure after the formation of the first stacked structure to transform the first stacked structure into a second stacked structure, wherein the second stacked structure includes: the stacked substrate, a nickel-platinum silicide layer, a titanium silicide layer, a nickel-platinum alloy layer of a second thickness, and the titanium nitride layer, wherein the second thickness is less than the first thickness; Remove the titanium nitride layer and the nickel-platinum alloy layer of the second thickness from the second stacked structure; A thermal annealing process is performed on the semiconductor structure after the titanium nitride layer in the second stacked structure is removed.
2. The method for fabricating a flash memory device according to claim 1, characterized in that, The thickness of the titanium layer is 10 angstroms to 50 angstroms.
3. The method for fabricating a flash memory device according to claim 1, characterized in that, The thickness of the first nickel-platinum alloy layer is 100 angstroms to 300 angstroms.
4. The method for fabricating a flash memory device according to claim 1, characterized in that, The thickness of the titanium nitride layer is 50 angstroms to 150 angstroms.
5. The method for fabricating a flash memory device according to claim 1, characterized in that, In the second stacked structure, the thickness of the titanium silicide layer is 15 angstroms to 75 angstroms.
6. The method for fabricating a flash memory device according to claim 1, characterized in that, In the second stacked structure, the thickness of the nickel-platinum silicide layer is 150 angstroms to 450 angstroms.
7. The method for fabricating a flash memory device according to claim 1, characterized in that, Before forming a titanium layer on the substrate surface of the storage region on the flash memory cell side according to the self-alignment characteristics, the method for fabricating the flash memory device further includes: removing the natural oxide layer on the substrate surface of the storage region on the flash memory cell side by means of a SiCoNi etching process.
8. The method for fabricating a flash memory device according to claim 7, characterized in that, After removing the native oxide layer from the substrate surface of the storage region on the flash memory cell side and before forming a titanium layer on the substrate surface of the storage region on the flash memory cell side, the method for fabricating the flash memory device further includes: performing a degassing treatment on the semiconductor structure after removing the native oxide layer.
9. The method for fabricating a flash memory device according to claim 1, characterized in that, The method for fabricating the flash memory device further includes, after performing a thermal annealing process on the semiconductor structure following the removal of the titanium nitride layer in the second stacked structure: An interlayer insulating dielectric layer is formed, which covers the titanium silicide layer in the second stacked structure; The interlayer insulating dielectric layer is etched and stopped on the surface of the titanium silicide layer to form a contact hole; A metal layer is filled into the contact hole to form a conductive plug.
10. A flash memory device, characterized in that, include: A substrate, the substrate comprising at least a storage region, on which at least one flash memory cell is formed; A nickel-platinum silicide layer is located on the substrate surface of the storage region on the side of the flash memory cell; A titanium silicide layer, which covers the nickel-platinum silicide layer.