Control circuit hexadecimal signal generation method, annunciator and multifunctional regulator

Abstract

The invention relates to the technical field of electronic engineering, and discloses a control circuit hexadecimal signal generation method, an annunciator and a multifunctional regulator, and the method comprises the steps: collecting control circuit configuration, analyzing a constraint identifier and a level conversion condition, and extracting a circuit association node; analyzing node cross-domain characteristics, generating a jump propagation trajectory, extracting a critical section and calculating a time sequence margin coefficient, dividing a signal conversion block based on the coefficient, identifying a coding and decoding check chain, analyzing phase alignment logic to construct a signal check sequence, querying a block delay path, extracting an optimization point and calculating time sequence convergence confidence, and finally, generating an eye pattern verification matrix, analyzing noise margin characteristics and anti-interference codes, and finally generating an anti-attenuation hexadecimal signal sequence of the target control circuit. Therefore, signal generation of the control circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of electronic engineering technology, and in particular to a method for generating hexadecimal signals for a control circuit, a signal generator, and a multi-functional controller. Background Technology

[0002] As the core execution unit of an electronic system, the control circuit's ability to generate hexadecimal signals determines the system's communication accuracy and control efficiency. Furthermore, hexadecimal signals, using 0-9 and AF encoding, are widely used in bus protocols, data conversion, and microcontroller instruction transmission to ensure high-density encoding and rapid identification of information.

[0003] Currently, existing methods rely on predefined hardware logic circuits or fixed software algorithms (such as the instruction set of a static microcontroller) to generate signals through manual encoding or table lookup. These methods are inflexible when dealing with dynamic signal sequences or environmental interference, and are prone to clock deviations, signal delays, and increased bit error rates, which affect the signal generation of the control circuit. Therefore, a hexadecimal signal generation method for the control circuit is needed to improve the signal generation of the control circuit. Summary of the Invention

[0004] This invention provides a method for generating hexadecimal signals for control circuits, a signal generator, and a multi-functional controller to improve signal generation in control circuits.

[0005] Firstly, a method for generating hexadecimal signals for a control circuit is provided, including: The circuit configuration in the control circuit is acquired, and the constraint identifiers corresponding to the circuit configuration are parsed. The level transition conditions corresponding to the constraint identifiers are analyzed, and the circuit association nodes in the control circuit are extracted based on the level transition conditions. Analyze the cross-domain features corresponding to the circuit-related nodes, generate the jump propagation trajectory associated with the cross-domain features, extract the critical trajectory segment in the jump propagation trajectory, and calculate the timing margin coefficient corresponding to the critical trajectory segment. Based on the timing margin coefficient, the signal conversion blocks corresponding to the circuit configuration are divided, the codec check chains in the signal conversion blocks are identified, and the phase alignment logic in the codec check chains is analyzed to construct the signal verification sequence corresponding to the codec check chains. Based on the signal verification sequence, query the block delay path corresponding to the signal conversion block, extract the path optimization points in the block delay path, and calculate the time series convergence confidence corresponding to the path optimization points. Based on the timing convergence confidence, an eye diagram verification matrix corresponding to the signal verification sequence is generated. The noise tolerance features in the eye diagram verification matrix are analyzed, and the anti-interference coding in the noise tolerance features is identified to generate a hexadecimal signal sequence for the target control circuit with respect to attenuation.

[0006] In a second aspect, a signal device is provided, the signal device storing a computer data program, characterized in that, when the computer data program is executed by a processor, it implements the steps of a control circuit hexadecimal signal generation method as described in any one of claims 1 to 8.

[0007] Thirdly, a multifunctional controller is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements the steps of a control circuit hexadecimal signal generation method as described in any one of claims 1 to 8. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of an application environment for a hexadecimal signal generation method for a control circuit according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating a method for generating hexadecimal signals in a control circuit according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the signal verification process in the hexadecimal signal generation method of the control circuit in one embodiment of the present invention; Figure 4 This is a schematic diagram of the internal structure of a signal device in one embodiment of the present invention; Figure 5 This is another structural schematic diagram of the multifunctional controller in one embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] The hexadecimal signal generation method for control circuits provided in this embodiment of the invention can be applied to, for example... Figure 1 In this application environment, the client communicates with the server via a network. The server can collect the circuit configuration in the control circuit, parse the constraint identifiers corresponding to the circuit configuration, analyze the level transition conditions corresponding to the constraint identifiers, and extract the circuit-related nodes in the control circuit based on the level transition conditions. It can also analyze the cross-domain features corresponding to the circuit-related nodes, generate the jump propagation trajectory associated with the cross-domain features, extract the critical trajectory segments in the jump propagation trajectory, and calculate the timing margin coefficients corresponding to the critical trajectory segments. Based on the timing margin coefficients, it can divide the signal conversion blocks corresponding to the circuit configuration and identify the codec check chains in the signal conversion blocks. The process involves analyzing the phase alignment logic in the codec verification chain to construct a signal verification sequence corresponding to the codec verification chain. Based on the signal verification sequence, the block delay path corresponding to the signal conversion block is queried, path optimization points in the block delay path are extracted, and the timing convergence confidence corresponding to the path optimization points is calculated. Based on the timing convergence confidence, an eye diagram verification matrix corresponding to the signal verification sequence is generated. The noise tolerance features in the eye diagram verification matrix are analyzed, and anti-interference coding in the noise tolerance features is identified to generate a hexadecimal signal sequence for the target control circuit with respect to attenuation. The client can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. The server can be implemented using a standalone server or a server cluster consisting of multiple servers. The invention will be described in detail below through specific embodiments.

[0012] Please see Figure 2 As shown, Figure 2 A flowchart illustrating a method for generating hexadecimal signals for a control circuit according to an embodiment of the present invention includes the following steps: S1. Acquire the circuit configuration in the control circuit, parse the constraint identifiers corresponding to the circuit configuration, analyze the level transition conditions corresponding to the constraint identifiers, and extract the circuit association nodes in the control circuit based on the level transition conditions.

[0013] This invention can accurately capture the basic constraints of circuit operation by collecting the circuit configuration in the control circuit and parsing the constraint identifiers corresponding to the circuit configuration, providing a targeted basis for subsequent signal generation; at the same time, it can quickly locate the core constraints affecting signal output, improving the adaptation efficiency of the overall signal generation process.

[0014] The control circuit refers to the core unit of a closed-loop control system composed of components such as a microcontroller, logic gates, and signal transmission buses. It is responsible for receiving input commands and converting them into execution signals. For example, in an industrial PLC control circuit, the CPU module parses sensor data and outputs hexadecimal control signals to the servo motor driver via the I / O interface circuit. The circuit configuration refers to the set of connection topologies, parameter settings, and operating modes of the hardware components in the control circuit. It includes information such as component models, pin connections, and clock frequency settings. For example, in the configuration of an embedded control circuit, the MCU model can be clearly identified as STM32F103. The PI bus rate is set to 18MHz, and the GPIO pin level is constrained to 3.3V through a resistor network. The constraint identifier refers to the hard rule marking in the circuit configuration that limits signal transmission and conversion, covering parameters such as voltage threshold range, timing synchronization requirements, and noise tolerance. For example, the constraint identifier of a certain CAN bus control circuit will indicate that the common-mode voltage of the differential signal must be between -2V and 7V, and the bit time must include timing division rules such as synchronization segment (1TQ) and propagation segment (3TQ). Optionally, the circuit configuration in the acquisition control circuit can be realized by the circuit description language extraction method, such as: using the Cadence Spectre simulation tool to import the circuit netlist file and automatically generate configuration information to obtain the circuit configuration. The parsing of the constraint identifier corresponding to the circuit configuration can be realized by the constraint file parsing algorithm, such as: using Synopsys Design Compiler to read the SDC format constraint file and mark the key electrical rules to obtain the constraint identifier.

[0015] Furthermore, based on the level conversion conditions, this invention extracts the circuit-related nodes in the control circuit, which can accurately locate the key interacting nodes in the signal transmission path, providing a focus for subsequent analysis and laying the foundation for analyzing signal propagation laws and optimizing the transmission path.

[0016] The circuit-related nodes refer to the set of nodes in the control circuit that have direct or indirect signal interaction with the driving components and have a significant impact on the level conversion process. These include input signal nodes, feedback adjustment nodes, load nodes, etc. For example, in the control circuit of a DC-DC converter, the circuit-related nodes may include PWM signal input nodes, output voltage sampling nodes, inductor current detection nodes, error amplifier output nodes, etc. Changes in the state of these nodes will directly change the result of the level conversion.

[0017] As an embodiment of the present invention, the step of extracting circuit-related nodes in the control circuit based on the level transition conditions includes: identifying the driving component corresponding to the control circuit based on the level transition conditions; analyzing the transition association mode corresponding to the level transition conditions based on the driving component; loading the node query template corresponding to the transition association mode; identifying the driving association elements in the node query template; and extracting the circuit-related nodes in the control circuit based on the driving association elements.

[0018] The driving component refers to the core hardware module in the control circuit that directly participates in the level conversion operation. It has the function of receiving input signals and outputting corresponding levels according to set rules. It typically includes transistor switching circuits, level converters, and driving chips. For example, in a motor control circuit, a 74HC245 bus transceiver serves as the driving component, converting the input 5V logic level to a 3.3V output to match the voltage requirements of subsequent circuits. Its conversion rate can reach 20MHz. The conversion association mode refers to the dynamic interaction rules and connection logic formed between the driving component and other circuit nodes during the level conversion process. It reflects the signal flow, timing coordination, and parameter influence relationships during level conversion. For example, in an SPI communication control circuit, when the driving component converts the clock signal from low to high, the data input node needs to synchronously complete data latching. This "clock transition-data latching" linkage is called the conversion association mode. A specific conversion association pattern is formed; the node query template refers to a predefined set of structured query rules for accurately locating nodes related to level conversion in the circuit, including query dimensions such as node type, signal characteristics, and connection attributes. For example, for the scenario of TTL level to RS485 level conversion, the node query template may include query items such as "differential signal output node", "enable control node", and "signal ground reference node", and the impedance of the wires between nodes is limited to ≤50Ω; the drive association elements refer to the key parameters and characteristics in the node query template that determine the association strength between the drive component and other nodes, including signal transmission delay threshold, level matching accuracy, load tolerance range, etc. For example, in a switching circuit where the drive component is a MOSFET, the drive association elements may include "gate drive voltage fluctuation range ≤±0.5V", "on-resistance between source and drain ≤10mΩ", "switching time ≤50ns", etc.

[0019] Furthermore, the identification of the driving components corresponding to the control circuit can be achieved through circuit function module analysis methods, such as using Cadence Sigrity to extract the MOSFET driving structure in the power management unit to obtain the driving components; the analysis of the conversion association patterns corresponding to the level conversion conditions can be achieved through state machine modeling techniques, such as using MATLAB Stateflow to perform pattern matching on the high and low level switching logic to obtain the conversion association patterns; the loading of the node query template corresponding to the conversion association patterns can be achieved through XML configuration file parsing methods, such as importing a predefined netlist query rule file through Altium Designer to obtain the node query template; the identification of driving association elements in the node query template can be achieved through critical path tracing algorithms, such as using Synopsys PrimeTime to extract the driving buffer units in the clock tree synthesis report to obtain the driving association elements; the extraction of circuit association nodes in the control circuit can be achieved through netlist topology analysis techniques, such as using MentorGraphics HyperLynx to parse the interconnect nodes in the PCB design file to obtain the circuit association nodes.

[0020] S2. Analyze the cross-domain features corresponding to the circuit-related nodes, generate the jump propagation trajectory associated with the cross-domain features, extract the critical trajectory segment in the jump propagation trajectory, and calculate the timing margin coefficient corresponding to the critical trajectory segment.

[0021] This invention, by analyzing the cross-domain characteristics of the circuit-related nodes, can break through the limitations of analysis in a single circuit domain and comprehensively capture the interaction patterns of nodes in different signal domains; it can reveal the potential cross-domain influence mechanisms between nodes, provide a multi-dimensional perspective for understanding the complex characteristics of signal propagation, and improve the ability to predict dynamic changes in signals.

[0022] The cross-domain characteristics refer to the comprehensive characteristics exhibited by circuit-related nodes when they interact with signals in different voltage domains, signal types, or transmission protocols. These characteristics include dimensions such as level compatibility, timing matching, and signal integrity. For example, in the conversion from the TTL level domain to the RS485 differential domain, the cross-domain characteristics of a circuit-related node may be a combination of common-mode rejection ratio ≥60dB, transmission delay ≤50ns, and differential signal swing ≥200mV.

[0023] As an embodiment of the present invention, the analysis of the cross-domain characteristics corresponding to the circuit-associated node includes: parsing the voltage domain identifier pairs in the circuit-associated node; analyzing the specific identifier level values ​​of the voltage domain identifier pairs; determining the drive tolerance threshold corresponding to the associated drive node based on the identifier level values; calculating the level swing difference corresponding to the associated drive node based on the drive tolerance threshold; and analyzing the cross-domain characteristics corresponding to the circuit-associated node based on the level swing difference.

[0024] The voltage domain identifier pair refers to a pair of identifiers in the circuit association node used to mark different voltage operating ranges. It consists of a source domain identifier and a target domain identifier, used to distinguish the start and end voltage domains of signal transmission. For example, in a hybrid voltage control circuit, there may be an identifier pair like "VD1-VD2", where VD1 represents a 3.3V digital voltage domain and VD2 represents a 12V analog voltage domain, thus clarifying the cross-domain path of the signal from the digital domain to the analog domain. The identifier level value refers to the specific voltage value corresponding to each identifier in the voltage domain identifier pair. It is a reference quantity for level transition, including high-level threshold, low-level threshold, and transition critical point voltage. For example, in a voltage domain identifier pair "VDD-VSS", the identifier level value can be set as follows: VDD high level ≥ 2.4V, low level ≤ 0.4V; VSS high level ≥ 1.8V, low level ≤ 0.3V; and the transition critical point is set to 1.2V as the level transition threshold. Judgment Criteria: The drive tolerance threshold refers to the range of input and output voltage deviations that an associated drive node can withstand during cross-domain transmission of drive signals. It is a critical parameter to ensure the stability of level conversion. For example, the drive tolerance threshold of an associated drive node may be set to allow an input voltage deviation of ±0.3V and an output voltage fluctuation of no more than ±0.2V. When the voltage deviation of the cross-domain signal is within this range, it can ensure that the drive node works normally without false triggering. The level swing difference refers to the difference between the level change amplitude of the input signal and the level change amplitude of the output signal during cross-domain transmission of the associated drive node. It reflects the attenuation or gain characteristics of the signal during cross-domain conversion. For example, if the level swing of the input signal of a node is 0V-5V (swing 5V), and the level swing of the output signal after cross-domain conversion is 0V-3.3V (swing 3.3V), then the level swing difference corresponding to this node is 1.7V, which can be used to evaluate the energy loss of signal conversion.

[0025] Furthermore, the parsing of voltage domain identifier pairs in the circuit-associated nodes can be achieved through netlist voltage domain annotation methods, such as using Synopsys IC Compiler to extract power domain definition attributes from the standard cell library to obtain voltage domain identifier pairs; the analysis of the specific identifier level values ​​of the voltage domain identifier pairs can be achieved through SPICE simulation technology, such as using Cadence Virtuoso ADE tools to perform DC operating point analysis on the power network to obtain identifier level values; the determination of the drive tolerance threshold corresponding to the associated drive node can be achieved through process corner simulation methods, such as using Mentor Graphics Eldo to perform PVT condition scanning to obtain drive capability boundary values ​​to obtain drive tolerance thresholds; the calculation of the level swing difference corresponding to the associated drive node can be achieved through signal integrity analysis methods, such as using Keysight ADS to perform transient simulation to measure the high and low level differences to obtain level swing differences; the analysis of the cross-domain characteristics corresponding to the circuit-associated nodes can be achieved through mixed-signal verification technology, such as using Siemens EDA Questa to perform protocol checks on digital-analog interfaces to obtain cross-domain characteristics.

[0026] This invention generates the jump propagation trajectory associated with the cross-domain features, which can intuitively present the jump path and propagation law of the signal between different domains, providing a basis for accurate analysis of the dynamic characteristics of the signal; it can clearly locate the key nodes and potential bottlenecks in the jump process, and improve the controllability of signal generation.

[0027] The transition propagation trajectory refers to the propagation path and timing evolution process between different circuit domains (such as digital domain, analog domain, RF domain, etc.) when a signal level in the control circuit transitions (e.g., from low level to high level or vice versa). It includes key parameters such as node triggering sequence, signal delay, and amplitude changes. For example, in a high-speed data acquisition circuit, when the ADC sampling clock signal transitions from 0V to 3.3V, its transition propagation trajectory can be described as follows: First, the sample-and-hold circuit is triggered (…). After a 2.5ns delay, the signal reaches the comparator input. ), and then quantization encoding is completed in 1.8ns ( Finally, it is output through the SPI interface. The entire trajectory records the transmission path and time relationship of the level transition between different functional modules. Optionally, the generation of the transition propagation trajectory associated with the cross-domain features can be achieved by signal integrity simulation methods, such as using Keysight PathWave ADS to perform transient analysis and trace the signal propagation path along the transmission line to obtain the transition propagation trajectory.

[0028] Furthermore, by extracting the critical trajectory segment in the transition propagation trajectory and calculating the timing margin coefficient corresponding to the critical trajectory segment, the present invention can accurately pinpoint the critical path most susceptible to timing interference in signal transmission, providing a clear direction for targeted optimization; and can quantitatively evaluate the timing stability of the trajectory segment, enhancing the timing controllability and anti-interference capability of signal generation.

[0029] The critical trajectory segment refers to the physical signal path corresponding to the transition propagation trajectory of a continuous critical sequence. It includes the complete transmission link from the starting node to the ending node and is the core object of timing optimization. For example, the critical trajectory segment corresponding to the continuous critical sequence {A5, A6, A7} on the SPI bus could be a physical path starting from the MOSI pin of the master controller, passing through a 20cm PCB trace, a signal buffer, and finally reaching the DI pin of the slave device. The total delay of this trajectory segment exceeds 30% of the system timing budget and requires targeted optimization. The timing margin coefficient refers to a quantitative evaluation index of the timing characteristics of the critical trajectory segment, reflecting the adaptation relationship between the actual propagation delay of the trajectory segment and the timing constraints. For example, for a certain critical trajectory segment, ( Set to 10ns (the maximum allowable delay standard of the system), discrete points , (i.e., the actual propagation time of the signal at that point), substituting into the formula, SI can be calculated. The smaller SI is, the closer the trajectory segment timing is to the constraint limit.

[0030] As an embodiment of the present invention, the step of extracting the critical trajectory segment in the jump propagation trajectory includes: parsing the propagation delay index in the jump propagation trajectory; identifying the set of excessive delay points in the propagation delay index based on a preset time constraint threshold; generating a continuous critical sequence corresponding to the set of excessive delay points; and extracting the critical trajectory segment in the continuous critical sequence.

[0031] The propagation delay index refers to the ratio of the delay time of each signal transmission node in the jump propagation trajectory to the standard reference value. It is used to quantify the impact of a node on signal timing and is usually expressed as a dimensionless value. For example, in an I2C bus communication circuit, the reference delay from the rising edge of the standard clock to the valid data establishment is 50ns, while the actual measured delay time of a certain node is 60ns. Then the propagation delay index of that node is 1.2 (i.e., 60ns / 50ns). The larger the index, the more significant the negative impact of the node on timing. The set of nodes exceeding the standard delay point refers to the set of nodes whose propagation delay index exceeds the preset timing constraint threshold. The delay time of these nodes exceeds the system's tolerable range and can lead to signal timing disorder. For example, in a high-speed ADC sampling circuit, the preset delay index exceeds the standard reference value. The order constraint threshold is 1.1. If the propagation delay indices of nodes N3, N7, and N12 on the sampling clock path are detected to be 1.3, 1.25, and 1.4 respectively, then these three nodes constitute an out-of-specification delay point set, and the cause of their delay needs to be analyzed in detail. The continuous critical sequence refers to the largest continuous subsequence formed by adjacent out-of-specification nodes in the out-of-specification delay point set, which reflects the key areas in the transition propagation trajectory where timing problems occur continuously. For example, in the propagation delay detection of a certain SPI bus, the out-of-specification delay point set includes nodes A2, A3, A5, A6, A7, and A9, where A2 is adjacent to A3 and A5 is adjacent to A7, thus forming two continuous critical sequences {A2, A3} and {A5, A6, A7}. These sequences represent the timing-sensitive areas in the SPI bus that need to be optimized first.

[0032] Furthermore, the analysis of the propagation delay index in the jump propagation trajectory can be achieved using time series analysis tools, such as using Synopsys PrimeTime to check setup and hold times and calculate path delay parameters to obtain the propagation delay index; the identification of the set of excessive delay points in the propagation delay index can be achieved using static time series analysis methods, such as using Cadence Tempus to perform maximum delay path detection and mark violation nodes to obtain the set of excessive delay points; the association and generation of the continuous critical sequence corresponding to the set of excessive delay points can be achieved using time series path tracing algorithms, such as using Mentor Graphics Questa Formal verification tools to perform critical path continuity analysis to obtain the continuous critical sequence; the extraction of critical trajectory segments in the continuous critical sequence can be achieved using waveform matching techniques, such as using a Keysight Infiniium oscilloscope to capture and segment excessive signal waveform segments to obtain the critical trajectory segments.

[0033] In another embodiment of the present invention, the timing margin coefficient corresponding to the critical trajectory segment can be calculated by the following formula:

[0034] in, This represents the timing margin coefficient corresponding to the critical trajectory segment. This represents the total number of discrete points in the critical trajectory segment. Index representing the number of discrete points. Represents the time-series constraint threshold (unit: seconds). This represents the propagation delay value (in seconds) corresponding to the i-th discrete point.

[0035] In detail, the discrete point refers to the node that is discretized and sampled on the critical trajectory segment, which is the basic unit for timing analysis. In the formula, N represents the total number of points, and i marks the sequence number. For example, on a critical trajectory segment from the CPU to the peripheral device, sampling points are set every 2cm along the signal path, for a total of 5 points (N=5). Each point is a discrete point, corresponding to... arrive The timing constraint threshold refers to the maximum permissible propagation delay standard preset to ensure normal signal transmission. In the above formula, it serves as an ideal delay reference, compared to the actual delay (…). In contrast, for example, in high-speed communication circuits, to avoid data conflicts, a certain setting is implemented. If the actual discrete point is delayed This indicates that the timing margin may be insufficient at this point, requiring adjustments to the circuit layout or component parameters; the propagation delay value refers to the actual time taken for the signal to travel from input to output at the i-th discrete point of the critical trajectory segment, and is used in the formula to sum... The calculation measures the timing deviation at that point. For example, at a discrete point on a trajectory segment, the signal is transmitted through a resistor-capacitor network, and the measured input-to-output time is 7 ns. ), combined Substituting these values ​​into the formula allows for the calculation of the impact of that point on the timing margin. If multiple points... If it's too large, the overall SI will decrease.

[0036] S3. Based on the timing margin coefficient, divide the signal conversion blocks corresponding to the circuit configuration, identify the codec check chain in the signal conversion block, and analyze the phase alignment logic in the codec check chain to construct the signal verification sequence corresponding to the codec check chain.

[0037] Based on the timing margin coefficient, this invention divides the circuit configuration into signal conversion blocks, which can accurately identify regions with different timing characteristics in the circuit and provide a basis for differentiated optimization. It can match and adapt conversion strategies according to the margin situation, improve the efficiency of cross-domain signal conversion, ensure the overall timing stability and signal quality of the circuit, and help optimize the circuit configuration efficiently.

[0038] The signal conversion block refers to a circuit region with relatively consistent timing margin characteristics, which is divided based on the conversion partition boundary. The timing constraints and delay patterns of signal conversion within the same block are similar, which facilitates the targeted design of conversion logic. For example, the circuit can be divided into blocks such as "high margin conversion area" (timing margin coefficient 1.2-1.8, stable signal delay and sufficient margin) and "low margin risk area" (timing margin coefficient 0.3-0.6, timing needs to be optimized) by using critical partition points and conversion partition boundaries.

[0039] As an embodiment of the present invention, the step of dividing the signal conversion blocks corresponding to the circuit configuration based on the timing margin coefficient includes: parsing the timing distribution characteristics corresponding to the timing margin coefficient; identifying the critical partition points corresponding to the circuit configuration according to the timing distribution characteristics; mapping the conversion partition boundaries corresponding to the critical partition points; and dividing the signal conversion blocks corresponding to the circuit configuration based on the conversion partition boundaries.

[0040] The timing distribution characteristics refer to the numerical distribution patterns and variations of timing margin coefficients at different nodes and signal paths in the circuit. This includes differences in the magnitude of the margin coefficients, central tendency (such as mean and median), and dispersion (such as variance), reflecting the overall state of the circuit's timing characteristics. For example, in a mixed-signal circuit, calculating the timing margin coefficients for 50 signal paths reveals that 20 paths have coefficients concentrated between 0.8 and 1.2 (mean 1.0), 15 are between 1.3 and 1.7 (mean 1.5), and 15 are between 0.3 and 0.7 (mean 0.5). This multi-interval dispersion with relative concentration within each interval constitutes the timing distribution characteristics of the circuit. The critical partition point refers to the point at which, based on the timing distribution characteristics, the circuit signal... Key nodes identified in the signal path where the timing margin coefficient changes significantly (e.g., a sudden drop from a high margin range to a low margin range) serve as boundary markers for dividing signal conversion blocks. For example, in a circuit with continuous signal paths, the timing margin coefficient is stable at 1.2-1.5 in the first half, and then suddenly drops to 0.4-0.6 after a certain node. This node can be identified as a critical partition point. The conversion partition boundary refers to the virtual or physical boundary formed by connecting or extending the critical partition points, used to define the range of the signal conversion block and clearly separate blocks with different timing characteristics. For example, in a circuit layout, multiple critical partition points are distributed along the signal transmission direction. Connecting these points according to the signal path forms a broken line or curve from input to output, and this line is the conversion partition boundary.

[0041] Furthermore, the analysis of the timing distribution characteristics corresponding to the timing margin coefficient can be achieved through statistical timing analysis methods, such as using Synopsys PrimeTime to perform multi-process corner timing distribution histogram statistics to obtain timing distribution characteristics; the identification of the critical partition points corresponding to the circuit configuration can be achieved through voltage domain cross-detection technology, such as using Cadence Innovus to automatically identify power domain boundary sensitive nodes to obtain critical partition points; the mapping of the conversion partition boundaries corresponding to the critical partition points can be achieved through layout marking algorithms, such as using MentorGraphics Calibre to run hierarchical layout boundary extraction commands to obtain conversion partition boundaries; the division of the signal conversion blocks corresponding to the circuit configuration can be achieved through physical partitioning methods, such as using Ansys RedHawk to perform voltage domain-based automatic layout partitioning to obtain signal conversion blocks.

[0042] This invention identifies the codec verification chain in the signal conversion block and analyzes the phase alignment logic in the codec verification chain, which can accurately locate the critical path of data verification, lay a solid foundation for data transmission reliability analysis, clarify the signal synchronization mechanism, ensure the consistency of data transmission and reception timing across blocks, and reduce the error risk of cross-block communication.

[0043] The encoding / decoding verification chain refers to a complete data processing chain within the signal conversion block, consisting of an encoding module, a transmission link, a decoding module, and a verification unit connected in series. This chain is used to encode, transmit, decode, and verify the accuracy of data transmitted across blocks. For example, in the signal conversion block of high-speed serial communication, data first passes through an 8B / 10B encoding module (encoding 8 bits of data into 10 bits), then through a differential transmission link (at a rate of 5Gbps), then is restored by the decoding module, and finally passes through a CRC verification unit (generating an 8-bit checksum). Each link works together to ensure reliable data transmission across blocks, forming the encoding / decoding verification chain. The phase alignment logic refers to the logic within the signal conversion block... This is a control mechanism used to adjust the phase relationship between the encoded output signal, the transmission link delay signal, and the decoded input signal, so that each signal is precisely synchronized along the time axis. For example, in a multi-channel data conversion block, the parallel signals after encoding will introduce a phase difference due to different link lengths (e.g., channel 1 link delay is 2ns, channel 2 delay is 3ns). The phase alignment logic dynamically adjusts the phase of each channel signal through a delay line (which can compensate for 0-5ns) or a phase interpolator, so that the rising and falling edges of the decoded signal are aligned, ensuring accurate data sampling. Optionally, the identification of the encoding / decoding verification chain in the signal conversion block can be achieved by a protocol analyzer, such as using a Keysight Infiniium oscilloscope in conjunction with protocol decoding software to extract the data verification sequence, thereby obtaining the encoding / decoding verification chain. The analysis of the phase alignment logic in the encoding / decoding verification chain can be achieved by a timing verification tool, such as using Synopsys SpyGlass to perform clock domain cross-checking and identify synchronization logic units, thereby obtaining the phase alignment logic.

[0044] Furthermore, by constructing the signal verification sequence corresponding to the encoding and decoding verification chain, the present invention can provide a real-time comparison benchmark for data transmission, accurately identify encoding errors and transmission distortions, enhance the dynamic verification capability of the verification chain, correct deviations in signal conversion in a timely manner, and ensure the integrity of data interaction.

[0045] The signal verification sequence refers to a reference sequence generated based on the signal check factor and used for comparison with the actual transmitted signal. It includes standard encoding results, check bits and timing markers. For example, for 8-bit data "0x5A", the signal verification sequence using even parity can be "0x5A+1 even parity bit (0)", and it also includes a timing marker indicating that the sequence should be transmitted within 100-200ns. Transmission errors can be quickly identified through comparison.

[0046] As an embodiment of the present invention, constructing the signal verification sequence corresponding to the codec verification chain includes: mapping the verification trigger tag corresponding to the codec verification chain; querying the timing data and tag interface covered by the verification trigger tag; generating the signal execution link corresponding to the control circuit based on the timing data and the tag interface; analyzing the signal verification factor corresponding to the signal execution link; and constructing the signal verification sequence corresponding to the codec verification chain based on the signal verification factor.

[0047] The verification trigger tag is a specific identifier in the codec verification chain used to initiate the signal verification process. It includes information such as the trigger time, verification range, and priority. It marks the signal segments to be verified according to preset rules. For example, in the codec verification chain of SPI communication, the verification trigger tag might be set to "automatically trigger after 16 bytes of data are continuously transmitted," and carry the starting address tag of the data block to ensure the verification process starts precisely at the designated node. The timing data refers to the time-dimensional parameters of the signal during transmission, encoding, and decoding within the coverage area of ​​the verification trigger tag, including the rising / falling edge time, duration, and interval period. For example, in the timing data of a UART communication, the start bit trigger time corresponding to the verification trigger tag is recorded as 100ns, each data bit lasts 62.5ns (corresponding to a 16MHz baud rate), and the stop bit end time is 875ns, providing a time reference for generating the verification sequence. The tag interface refers to the physical or logical port through which the verification trigger tag interacts with various modules (such as encoding units and verifiers) in the codec verification chain. It is used to transmit tag information and receive feedback signals. For example, in Ethernet... In the network encoding / decoding verification chain, the tag interface may be an 8-bit register interface. The verification trigger tag writes the verification start signal (active high) and data length (e.g., 64 bytes) to the verifier through this interface, and simultaneously reads the verification completion status. The signal execution chain refers to the complete transmission path of the signal formed in the control circuit from generation to verification based on timing data and the tag interface. It includes the connection relationship and signal flow of each functional module. For example, in I2C communication, the signal execution chain may be: MCU internal data register → I2C encoding module → SDA bus → slave device I2C decoding module → CRC verification unit. The interaction of each node in the chain follows the timing rules defined by the tag interface. The signal verification factor refers to the key parameter that affects the accuracy of signal verification. It is determined by the characteristics of the signal execution chain, including data length, encoding method, and verification algorithm type. For example, in CAN bus verification, the signal verification factor may include "data frame length is 0-8 bytes", "Cyclic Redundancy Check (CRC-15) is used", and "the padding bit rule is to insert a reverse bit after 5 consecutive identical bits". These factors directly determine the generation logic of the verification sequence.

[0048] Furthermore, the mapping of the verification trigger tag corresponding to the codec verification chain can be implemented using protocol decoding methods, such as using a Teledyne LeCroy protocol analyzer to extract specific trigger fields from data packets to obtain the verification trigger tag; the querying of the timing data covered by the verification trigger tag can be implemented using timing database retrieval technology, such as using the Mentor Graphics Questa verification platform to perform tag-based timing data queries to obtain the timing data; the querying of the tag interface covered by the verification trigger tag can be implemented using interface definition language parsing methods, such as using the Cadence Incisive verification tool to parse the interface definition in the UVM register model to obtain the tag interface; the generation of the signal execution link corresponding to the control circuit can be implemented using RTL synthesis technology, such as using Synopsys Design The Compiler converts the hardware description language into a gate-level netlist and extracts the critical path to obtain the signal execution link. The analysis of the signal check factor corresponding to the signal execution link can be achieved through formal verification methods, such as using the JasperGold formal verification tool to perform equivalence checks and calculate the check difference, thereby obtaining the signal check factor. The construction of the signal check sequence corresponding to the encoding / decoding check chain can be achieved through a CRC generation algorithm, such as using the Xilinx Vivado tool to call the CRC generator IP core to calculate the check code sequence, thereby obtaining the signal check sequence.

[0049] Specifically, for a more intuitive understanding of the execution logic and data flow relationship of constructing the encoding / decoding verification chain and signal verification sequence in this scheme, please refer to [reference needed]. Figure 3 The signal verification process diagram is shown below. Figure 3 As the core process framework of the codec verification system, it clearly presents the complete link from verification triggering to sequence construction: the input layer focuses on key information of the codec verification chain (verification trigger tag, timing data), which is the basis for subsequent verification; the processing layer transforms the original trigger information into an executable verification strategy through a step-by-step logic of "querying and verifying the frame header → querying the frame tail → verifying the frame tail → calculating the signal execution link parameters"; the output layer uses verification results such as "output frame header position" as the key outcome. It should be noted that the relationship between each link in the flowchart is essentially an abstract refinement of the codec verification-signal verification logic. In actual scenarios, the complexity of parameter calculation (such as the dynamic relationship between timing data and verification factors) and the diversity of link adaptation (different verification trigger tags correspond to different verification algorithm rules) are far greater than what is shown in the diagram. This architecture is only a concise display of the core logic, providing an intuitive reference for understanding the systematic approach to codec verification and signal verification sequence construction.

[0050] S4. Based on the signal verification sequence, query the block delay path corresponding to the signal conversion block, extract the path optimization point in the block delay path, and calculate the timing convergence confidence corresponding to the path optimization point.

[0051] Based on the signal verification sequence, this invention queries the block delay path corresponding to the signal conversion block, which can accurately locate the key link in the delay generation during signal conversion, providing clear direction for targeted optimization, effectively shortening signal transmission delay, and improving the timeliness of circuit signal conversion.

[0052] The block delay path refers to the cumulative delay path of a signal within a specific signal conversion block, from the input end through encoding, transmission, and decoding to the output end. This delay path is caused by factors such as circuit component characteristics, wiring length, and load effects. It includes the delay values ​​and timing relationships of each node. For example, in a certain SPI communication conversion block, the block delay path can be described as follows: data travels from the MCU output pin (delay 0.5ns) → through a 20cm PCB trace (delay 3.2ns) → through a level converter (delay 1.8ns) → to the slave device input pin (delay 0.3ns). The total delay of the entire path is 5.8ns. This records the delay distribution and transmission order of the signal at each stage within the block, which is an important basis for analyzing signal timing performance. Optionally, the query for the block delay path corresponding to the signal conversion block can be achieved through static timing analysis methods, such as using Synopsys PrimeTime to perform critical path delay analysis based on voltage domain partitioning to obtain the block delay path.

[0053] Furthermore, by extracting path optimization points in the block delay path and calculating the timing convergence confidence corresponding to the path optimization points, the present invention can accurately pinpoint the key locations for delay improvement, providing targeted targets for efficient optimization; and can quantitatively evaluate the expected effects of optimization measures, improve circuit timing stability and signal transmission efficiency, and ensure the controllability of overall performance.

[0054] The path optimization point refers to the key location identified based on the core domain point that contributes the most to the total delay in the block delay path and has optimization potential. Adjusting the parameters of these points can significantly reduce the overall delay. For example, in a certain block delay path, the total delay is 6.5ns, of which the delay of the core domain point "differential signal transmission line termination matching resistor" accounts for 40% (i.e., 2.6ns). By adjusting the resistance value from 100Ω to 75Ω (matching the transmission line impedance), the delay at this point can be reduced to 1.2ns, and the total delay can be optimized to 5.1ns. The location of this termination matching resistor is the path optimization point. The timing convergence confidence refers to the reliability of the signal achieving timing convergence (i.e., effective signal transmission without timing conflicts) at the path optimization point. The closer its value is to 1, the more stable the timing. For example, for a certain circuit optimization point, substituting the parameters, we get Cz=0.85, which means that this point has an 85% probability of meeting the timing constraints. Cz can be improved by optimizing to reduce jitter, etc., to ensure the reliability of signal timing.

[0055] As an embodiment of the present invention, the step of extracting path optimization points in the block delay path includes: analyzing the delay change scenarios covered by the block delay path; querying the core change elements associated with the delay change scenarios; determining the timing synchronization domain corresponding to the conversion delay trajectory based on the core change elements; locating the core domain points in the timing synchronization domain; and extracting path optimization points in the block delay path based on the core domain points.

[0056] The aforementioned delay change scenario refers to a specific situation in which the signal transmission delay changes significantly due to changes in the circuit's operating state (such as load changes, temperature fluctuations, signal frequency adjustments, etc.) within the block delay path. This reflects the dynamic process of delay values ​​changing with external or internal conditions. For example, in the block delay path of a certain DDR memory interface, when the data transmission frequency increases from 1600MHz to 2400MHz, the transmission delay of the PCB traces increases from 2.5ns to 3.8ns; or when the ambient temperature rises from 25℃ to 85℃, the delay of the chip's internal buffer increases from 0.8ns to 1.2ns. These changes are due to frequency and temperature variations. All situations that cause delay variations fall under the category of delay change scenarios. The core change factors refer to the key parameters or physical quantities that cause changes in the delay value within these scenarios, directly determining the magnitude and trend of the delay change. These typically include signal frequency, load impedance, temperature coefficient, and power supply voltage. For example, in a high-speed serial link delay change scenario, the core change factors might be "signal frequency increases from 5Gbps to 10Gbps," "transmission line characteristic impedance deviates from the standard value of 50Ω, becoming 55Ω," and "power supply voltage fluctuates from 1.0V to 0.95V." These factors combined increase the link delay from 1.2ns to 1.8ns. ns is the core basis for analyzing the causes of delay variations; the timing synchronization domain refers to the circuit region in the conversion delay trajectory where all signals follow the same clock reference and timing constraints. The transmission and sampling of signals within the domain maintain timing consistency and are not affected by clock interference from other domains. For example, in the interface circuit between an FPGA and an ADC, there exists a timing synchronization domain based on a 100MHz system clock. This domain includes ADC sampling control signals, data output signals, and FPGA input buffers. The rising edges of all signals are synchronized with the rising edge of the 100MHz clock (period 10ns), and the sampling window is fixed at 30% of the clock period. (i.e., 3ns) to ensure no deviation in signal timing within the domain; the core domain point refers to the key node in the timing synchronization domain that plays a decisive role in the overall delay characteristics. Small changes in its delay value will significantly affect the timing performance of the entire synchronization domain. It usually includes clock source nodes, signal buffer output terminals, key sampling points, etc. For example, in the above-mentioned 100MHz timing synchronization domain, the output terminal of the ADC sample-and-hold circuit is the core domain point. When the delay of this node increases from the original 1.5ns to 2.0ns, it will cause the setup time of the entire synchronization domain to be reduced from 4ns to 3.5ns, directly affecting the stability of data sampling, and it needs to be a key monitoring object.

[0057] Furthermore, the analysis of the delay change scenarios covered by the block delay path can be achieved through multi-process angle timing analysis methods, such as using Cadence Tempus to perform PVT conditional scanning and generate delay change reports to obtain the delay change scenarios; the query of the core change elements associated with the delay change scenarios can be achieved through critical path analysis methods, such as using Synopsys PrimeTime for sensitivity analysis and extracting the process parameters that dominate the delay changes to obtain the core change elements; the determination of the timing synchronization domain corresponding to the conversion delay trajectory can be achieved through clock domain cross-analysis methods, such as using Mentor Graphics Questa to perform CDC verification and identify the synchronous clock domain boundary to obtain the timing synchronization domain; the location of the core domain points in the timing synchronization domain can be achieved through timing hotspot detection technology, such as using Ansys RedHawk to perform timing violation analysis and mark key synchronization nodes to obtain the core domain points; the extraction of path optimization points in the block delay path can be achieved through timing optimization algorithms, such as using Intel Quartus Prime to perform critical path reorganization and identify optimizable logic units to obtain the path optimization points.

[0058] In another embodiment of the present invention, the calculation of the temporal convergence confidence corresponding to the path optimization point can be performed by the following formula:

[0059] in, This represents the temporal convergence confidence level corresponding to the path optimization point. Indicates the effective value of jitter (unit: seconds). Indicates the scaling factor. Indicates the system clock cycle (unit: s). Represents the timing margin coefficient. Indicates the exponential factor. Indicates signal amplitude (unit: V). Indicates the effective value of noise (unit: V). This represents the noise adjustment factor.

[0060] In detail, the jitter RMS value refers to the root mean square value of the random deviation of the signal transition edge from the ideal position, which measures the stability of the signal timing. In the formula, it is used to reflect the negative impact of timing uncertainty on convergence confidence. The larger J is, the more difficult the timing converges. For example, in a system, the ideal period of the clock signal transition edge is 10ns (system clock period T=10ns), and the actual measured effective value of the transition edge deviation J=0.5ns. When substituted into the formula, this value will lower Cz, indicating that jitter needs to be suppressed to improve timing reliability. The scaling factor refers to a coefficient used to adjust the influence of parameters such as jitter to adapt to different circuit scenarios. It is used to balance the relative weight of jitter with other parameters (such as system clock period T) in the formula, so that the formula calculation adapts to the actual circuit characteristics. For example, in high-speed, high-frequency circuits (T=1ns), setting k to 2 can enhance the influence weight of J on Cz; in low-speed circuits (T=10ns), the scaling factor can be adjusted to 2. In s), k is set to 0.5 to reduce the relative influence of J. By flexibly adjusting k, the formula can accurately calculate the confidence level in different scenarios. The system clock period refers to the time it takes for the system master clock to complete one oscillation. It is the basic reference for timing constraints and serves as the timing benchmark in the formula. Together with jitter J and timing margin Sl, it determines whether the signal can be transmitted stably within the clock period. For example, if the system clock period T = 5ns, if the signal transmission delay is too large, it cannot complete establishment and maintenance within T, which will reduce Cz. Assuming that the signal delay at a certain optimization point accounts for 60% of T (i.e., 3ns), combined with parameters such as J, Cz can be calculated, reflecting the possibility of timing convergence at that point under clock period constraints. The exponential factor refers to the exponential parameter used to adjust the influence of the "jitter-timing margin" related terms in the formula on Cz. It controls the rate at which the calculation results of this part change with J, Sl, etc. For example, when β = 2, (J / (k T Sl))² will cause an increase in J or a decrease in Sl to have a more significant decay on Cz; when β=1, it affects the relative linearity. If a scenario requires emphasizing the impact of jitter on timing, β=3 can be set so that a small increase in J causes Cz to decrease rapidly. β can be used to adapt to the timing sensitivity requirements of different circuits. The signal amplitude refers to the maximum range of signal voltage variation (e.g., from 0V to 3.3V, then A=3.3V). In the formula, it is used to represent the signal's own energy. Compared with the effective noise value N, it reflects the signal's ability to resist noise interference. The larger A and the smaller N, the better the timing convergence and the higher Cz. For example, if A=2V and N=0.5V, A / N=4. Substituting this into the formula, this ratio will increase Cz. If the noise increases to N=1V, A / N=2, then Cz decreases, indicating a decrease in the signal's immunity to interference, requiring optimization of the signal amplitude or suppression of noise. The effective noise value refers to the root mean square value of the noise voltage in the circuit, measuring the intensity of noise interference. In the formula, it works together with the signal amplitude A to reflect the signal transmission in a noisy environment. For signal quality, the larger N is, the more susceptible the signal is to interference, and the lower the timing convergence confidence level Cz becomes. For example, if there is thermal noise or crosstalk noise in the circuit, and the measured effective noise value N = 0.3V, the signal amplitude A = 1.8V, and A / N = 6, this value is used in the calculation. If the noise increases to N = 0.6V, A / N = 3, it will significantly lower Cz, and filtering and other measures need to be taken to reduce N. The noise adjustment factor refers to the coefficient that fine-tunes the influence of the effective noise value N in the formula. It is used to compensate for the deviation of the calculation results due to the noise distribution characteristics in the actual circuit (such as the difference between impulse noise and Gaussian noise). For example, if the circuit is mainly filled with impulse noise, its actual influence is greater than that of Gaussian noise. α = 0.2 can be set to enhance the influence of N on Cz. If the noise is mainly Gaussian and easily suppressed by filtering, α = 0.1 can be set to make the formula calculation more consistent with the actual noise interference on timing convergence and improve the accuracy of confidence assessment.

[0061] S5. Based on the timing convergence confidence, generate the eye diagram verification matrix corresponding to the signal verification sequence, analyze the noise tolerance features in the eye diagram verification matrix, and identify the anti-interference coding in the noise tolerance features to generate the target control circuit with respect to attenuation hexadecimal signal sequence.

[0062] Based on the timing convergence confidence, this invention generates an eye diagram verification matrix corresponding to the signal verification sequence. This can transform the abstract confidence into an intuitive eye diagram feature index, accurately locate signal quality problems, improve verification efficiency and the pertinence of signal optimization, and ensure the coordinated achievement of circuit timing and signal quality standards.

[0063] The eye diagram verification matrix refers to a multi-dimensional parameter table generated based on timing jitter indicators to comprehensively evaluate signal quality. It includes indicators such as eye height, eye width, and jitter tolerance at different sampling times. For example, in the eye diagram verification matrix of a 10Gbps signal, the horizontal axis represents the sampling time (covering one clock cycle, such as 0-100ps, with a step size of 10ps), and the vertical axis represents the eye height (voltage amplitude). The matrix elements record the eye width (e.g., at a sampling time of 50ps, the eye width is 0.7UI) and jitter tolerance (e.g., tolerable jitter of ±0.3ns) at each sampling point, which can intuitively determine the reliability of the signal under different timing conditions.

[0064] As an embodiment of the present invention, generating the eye diagram verification matrix corresponding to the signal verification sequence based on the timing convergence confidence includes: analyzing the timing verification threshold corresponding to the timing convergence confidence; obtaining the timing-sensitive path in the signal verification sequence based on the timing verification threshold; querying the level transition data corresponding to the timing-sensitive path; collecting the timing jitter index in the level transition data; and generating the eye diagram verification matrix corresponding to the signal verification sequence based on the timing jitter index.

[0065] The timing verification thresholds refer to critical indicators set based on timing convergence confidence levels to determine whether signal timing meets design requirements. These include setup time thresholds, hold time thresholds, and cycle jitter thresholds. For example, in a DDR4 memory interface, based on timing convergence confidence levels, the setup time threshold is set to 30% of the clock cycle (e.g., 2.4ns for an 8ns clock cycle), the hold time threshold is 1.2ns, and the cycle jitter threshold is ±0.5ns. When the actual signal setup time is 2.2ns and the hold time is 1.3ns... When the jitter is ±0.4ns, the threshold requirements are met. The timing-sensitive path refers to the critical signal transmission path in the signal verification sequence that is highly sensitive to timing changes and is prone to functional failure due to timing deviations. It is usually selected by timing verification threshold. For example, in the signal verification sequence of the PCIe bus, the path from the TX output buffer of the transmitting end to the RX input buffer of the receiving end is identified as a timing-sensitive path because it involves high-speed differential signal transmission (such as 8GT / s) and the sampling window of the receiving end is only 25% of the clock cycle (about 0.3125ns). If there is an additional delay of more than 0.1ns on the path, it may cause the receiver to fail to sample. The level conversion data refers to the set of relevant parameters when the signal on the timing-sensitive path is converted from one logic level to another, including the conversion time, rise / fall time, overshoot / undershoot amplitude, etc. For example, in LVDS signal transmission, the level conversion data records the process of the signal converting from -350mV to +350mV: the rise time is 0.2ns (10%-90%), the conversion time is 0.5ns after the rising edge of the clock, and the overshoot amplitude is 50mV. These data are used to analyze the impact of the level conversion process on timing jitter. The timing jitter index refers to the parameter that quantifies the degree of timing instability in the level conversion data, including components such as periodic jitter (TJ), random jitter (RJ), and deterministic jitter (DJ). For example, measuring a high-speed clock signal yields a periodic jitter TJ of 0.8 ns (peak-to-peak value), which can be further decomposed into random jitter RJ = 0.2 ns (RMS) and deterministic jitter DJ = 0.6 ns (peak-to-peak value). DJ can be further subdivided into data correlation jitter (DDJ) of 0.4 ns and duty cycle distortion (DCD) of 0.2 ns. These metrics directly affect the eye diagram's opening.

[0066] Furthermore, the timing verification threshold corresponding to the timing convergence confidence can be obtained through statistical timing analysis methods, such as using Synopsys PrimeTime to perform Monte Carlo simulation and calculate the 3σ delay boundary value to obtain the timing verification threshold; obtaining the timing-sensitive path in the signal verification sequence can be achieved through a critical path extraction algorithm, such as using Cadence Innovus to perform timing constraint-driven path search and mark sensitive paths to obtain the timing-sensitive path; querying the level transition data corresponding to the timing-sensitive path can be achieved through mixed-signal simulation technology, such as using Keysight ADS to perform transient simulation and extract voltage jump waveform data to obtain the level transition data; acquiring the timing jitter index in the level transition data can be achieved through a jitter analyzer, such as using a Tektronix DPO70000 series oscilloscope to perform clock jitter measurement and calculate the RMS value to obtain the timing jitter index; generating the eye diagram verification matrix corresponding to the signal verification sequence can be achieved through signal integrity analysis methods, such as using Ansys... HFSS performs channel simulation and generates a multi-bit eye diagram superposition matrix, thereby obtaining the eye diagram verification matrix.

[0067] This invention analyzes the noise tolerance features in the eye diagram verification matrix and identifies the anti-interference coding in the noise tolerance features. This allows for the quantitative analysis of the signal's anti-interference capability and precise location of noise impact patterns. Furthermore, it can extract coding rules adapted to noisy environments to improve the stability and signal quality of circuits under complex interference.

[0068] The noise tolerance feature refers to the set of key indicators in the eye diagram verification matrix that measure the signal's ability to maintain correct logical recognition in a noisy environment. This includes high-level noise tolerance (the difference between the lower limit of the high-level signal and the maximum noise value), low-level noise tolerance (the difference between the minimum noise value and the upper limit of the low-level signal), and the variation of eye diagram opening under different noise intensities. For example, in the eye diagram of a high-speed serial signal, if the effective high-level range is [2.0V, 2.5V] and the maximum noise value is 0.3V, then the high-level noise tolerance is 2.0V - 0.3V = 1.7V; if the effective low-level range is [0.5V, 1.0V] and the minimum noise value is 0.2V, then the low-level noise tolerance is 0.2V - 1.0V (taking the absolute value as 0.8V). These values ​​reflect the basic ability of the signal to resist noise interference. Furthermore, by combining the change in eye width from 1.2ns to 0.5ns as the noise intensity increases from 0.1V to 1.0V, the attenuation characteristics of the tolerance with increasing noise can be analyzed, providing a basis for anti-interference design. Interference coding refers to a coding method that enhances the anti-interference and error correction capabilities of signals transmitted in noisy environments by employing special coding rules (such as adding redundant bits and introducing error correction algorithms) based on noise tolerance characteristics. For example, in an industrial control bus, the original data is encoded as 8-bit binary, which is susceptible to noise interference leading to bit errors. Based on noise tolerance analysis, Hamming coding can be used to extend the 8-bit data to 12 bits (adding 4 redundant check bits). When noise causes a 1-bit error in the signal, it can be automatically corrected by the check bits. For example, the original data "01010101" is encoded as "010101011010". During transmission, noise causes the 5th bit to flip to "010111011010". The receiving end can identify and correct this error using the redundant bits, ensuring reliable data transmission in scenarios with low noise tolerance. By optimizing the coding to adapt to the noise environment, the signal's anti-interference capability is improved. Optionally, the analysis of the noise tolerance characteristics in the eye diagram verification matrix can be achieved through eye diagram template testing methods, such as using Keysight. The Infiniium oscilloscope performs eye diagram template testing and calculates noise margin parameters to obtain noise tolerance features. The identification of anti-interference coding in the noise tolerance features can be achieved through bit error rate analysis techniques, such as using Tektronix BERTScope to identify coding patterns and extract error correction coding features to obtain anti-interference coding.

[0069] This invention enhances the signal's resistance to attenuation during transmission and reduces signal distortion over long distances or complex paths by generating a hexadecimal signal sequence for the target control circuit to resist attenuation. It can also adapt to the anti-interference requirements of the circuit and provide a standardized sequence for subsequent signal decoding and verification, ensuring the signal generation efficiency of the control circuit.

[0070] The hexadecimal signal sequence refers to an ordered signal combination formed by converting the binary control instructions, data information, or check codes of the target control circuit according to the rule that every 4 binary bits correspond to 1 hexadecimal bit (0-9, AF). This combination combines simplicity and anti-attenuation characteristics. For example, if a control circuit needs to transmit the instruction "Start Sampling + Channel 3 + Sampling Frequency 1MHz", the corresponding binary sequence is "1011 0011 1100 0101", which is converted to a hexadecimal signal sequence of "B3-C5". During transmission, because each hexadecimal bit carries 4 bits of information, the number of signal transitions can be reduced (the original 16-bit binary code requires 16 level changes, while the converted 4-bit code only requires 4), reducing the risk of signal distortion caused by attenuation. It also facilitates rapid circuit parsing and verification. Optionally, the generation of the anti-attenuation hexadecimal signal sequence for the target control circuit can be achieved through forward error correction coding methods, such as using Xilinx Vivado. The HLS tool integrates a Reed-Solomon encoder to generate a hexadecimal data stream with a parity bit, thus obtaining a hexadecimal signal sequence.

[0071] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0072] In one embodiment, a signal transmitter is provided, which may be a high-speed signal transmission device, and its internal structure diagram may be as follows: Figure 4 As shown, the signal generator includes a signal generation module, an encoding and verification unit, a timing adjustment circuit, and an interface module connected via an internal bus. The signal generation module provides the capability to generate hexadecimal base signals. The encoding and verification unit includes an anti-interference encoding circuit, a CRC checker, and a storage buffer. The anti-interference encoding circuit converts binary signals into hexadecimal sequences, and the storage buffer temporarily stores the signals to be transmitted and the checksums. The timing adjustment circuit provides a timing reference for the signal conversion of the encoding and verification unit, ensuring that signal transitions are synchronized with the system clock. The interface module communicates with external control circuits via a high-speed differential bus, supporting bidirectional signal transmission and status feedback. When the signal generator program is executed by the processor, it implements the client-side functions or steps of a hexadecimal signal generation method for a control circuit.

[0073] In one embodiment, a multi-functional controller is provided, the computer device being a client, and its internal structure diagram can be as follows: Figure 5As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with an external server via a network connection. When executed by the processor, the computer program implements the functions or steps of a hexadecimal signal generation method for a control circuit on the client side.

[0074] In one embodiment, a multi-functional controller is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it performs the following steps: The circuit configuration in the control circuit is acquired, and the constraint identifiers corresponding to the circuit configuration are parsed. The level transition conditions corresponding to the constraint identifiers are analyzed, and the circuit association nodes in the control circuit are extracted based on the level transition conditions. Analyze the cross-domain features corresponding to the circuit-related nodes, generate the jump propagation trajectory associated with the cross-domain features, extract the critical trajectory segment in the jump propagation trajectory, and calculate the timing margin coefficient corresponding to the critical trajectory segment. Based on the timing margin coefficient, the signal conversion blocks corresponding to the circuit configuration are divided, the codec check chains in the signal conversion blocks are identified, and the phase alignment logic in the codec check chains is analyzed to construct the signal verification sequence corresponding to the codec check chains. Based on the signal verification sequence, query the block delay path corresponding to the signal conversion block, extract the path optimization points in the block delay path, and calculate the time series convergence confidence corresponding to the path optimization points. Based on the timing convergence confidence, an eye diagram verification matrix corresponding to the signal verification sequence is generated. The noise tolerance features in the eye diagram verification matrix are analyzed, and the anti-interference coding in the noise tolerance features is identified to generate a hexadecimal signal sequence for the target control circuit with respect to attenuation.

[0075] It should be noted that the functions or steps that the multi-functional controller can achieve are described in the relevant descriptions of the server side and client side in the aforementioned method embodiments. To avoid repetition, they will not be described one by one here.

[0076] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0077] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0078] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. In the above multiple embodiments, each embodiment can be combined with each other or independent. Deleting any one of them will not affect the technical implementation of other embodiments. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for generating hexadecimal signals for a control circuit, characterized in that, include: The circuit configuration in the control circuit is acquired, and the constraint identifiers corresponding to the circuit configuration are parsed. The level transition conditions corresponding to the constraint identifiers are analyzed, and the circuit association nodes in the control circuit are extracted based on the level transition conditions. Analyze the cross-domain features corresponding to the circuit-related nodes, generate the jump propagation trajectory associated with the cross-domain features, extract the critical trajectory segment in the jump propagation trajectory, and calculate the timing margin coefficient corresponding to the critical trajectory segment. Based on the timing margin coefficient, the signal conversion blocks corresponding to the circuit configuration are divided, the codec check chains in the signal conversion blocks are identified, and the phase alignment logic in the codec check chains is analyzed to construct the signal verification sequence corresponding to the codec check chains. Based on the signal verification sequence, query the block delay path corresponding to the signal conversion block, extract the path optimization points in the block delay path, and calculate the time series convergence confidence corresponding to the path optimization points. Based on the timing convergence confidence, an eye diagram verification matrix corresponding to the signal verification sequence is generated. The noise tolerance features in the eye diagram verification matrix are analyzed, and the anti-interference coding in the noise tolerance features is identified to generate a hexadecimal signal sequence for the target control circuit with respect to attenuation.

2. The method for generating hexadecimal signals for a control circuit as described in claim 1, characterized in that, The step of extracting circuit-related nodes in the control circuit based on the level conversion condition includes: Based on the level transition conditions, identify the driving component corresponding to the control circuit; Based on the driving component, analyze the conversion association mode corresponding to the level conversion condition; Load the node query template corresponding to the transformation association mode; Identify the driving association elements in the node query template; Based on the aforementioned driving association elements, the circuit association nodes in the control circuit are extracted.

3. The method for generating hexadecimal signals for a control circuit as described in claim 1, characterized in that, The analysis of the cross-domain characteristics corresponding to the circuit-related nodes includes: Parse the voltage domain identifier pairs in the associated nodes of the circuit; Analyze the voltage domain identifier for specific identifier level values; Based on the identified level value, determine the drive tolerance threshold corresponding to the associated drive node; Based on the drive tolerance threshold, calculate the level swing difference corresponding to the associated drive node; Based on the level swing difference, the cross-domain characteristics corresponding to the circuit-related nodes are analyzed.

4. The method for generating hexadecimal signals for a control circuit as described in claim 1, characterized in that, Extracting the critical trajectory segment from the jump propagation trajectory includes: Analyze the propagation delay index in the jump propagation trajectory; Based on a preset timing constraint threshold, identify the set of delay points exceeding the standard in the propagation delay index; Generate a continuous critical sequence corresponding to the set of excessive delay points; The critical trajectory segment extracted from the continuous critical sequence and the corresponding time margin coefficient can be calculated using the following formula: in, This represents the timing margin coefficient corresponding to the critical trajectory segment. This represents the total number of discrete points in the critical trajectory segment. Index representing the number of discrete points. Indicates the time-series constraint threshold. This represents the propagation delay value corresponding to the i-th discrete point.

5. The method for generating hexadecimal signals for a control circuit as described in claim 1, characterized in that, The step of dividing the signal conversion blocks corresponding to the circuit configuration based on the timing margin coefficient includes: Analyze the temporal distribution characteristics corresponding to the aforementioned temporal margin coefficient; Based on the timing distribution characteristics, identify the critical partition points corresponding to the circuit configuration; Map the transformation partition boundary corresponding to the critical partition point; Based on the conversion partition boundary, the signal conversion blocks corresponding to the circuit configuration are divided.

6. The method for generating hexadecimal signals for a control circuit as described in any one of claims 1, characterized in that, The construction of the signal verification sequence corresponding to the encoding / decoding verification chain includes: Map the verification trigger tags corresponding to the encoding / decoding verification chain; Query the timing data and tag interface of the verification trigger tag coverage; Based on the timing data and the tag interface, a signal execution link corresponding to the control circuit is generated; Analyze the signal verification factor corresponding to the signal execution link; Based on the signal verification factor, construct the signal verification sequence corresponding to the encoding / decoding verification chain.

7. The method for generating hexadecimal signals for a control circuit as described in any one of claims 1, characterized in that, The extraction of path optimization points in the block delay path includes: Analyze the latency change scenarios covered by the block latency path; Query the core change elements associated with the delayed change scenario; Based on the core change elements, determine the timing synchronization domain corresponding to the conversion delay trajectory; Locate the core domain point in the timing synchronization domain; Based on the core domain points, path optimization points are extracted from the block delay paths, and the temporal convergence confidence corresponding to the path optimization points can be calculated using the following formula: in, This represents the temporal convergence confidence level corresponding to the path optimization point. Indicates the effective value of jitter. Indicates the scaling factor. Indicates the system clock cycle. Represents the timing margin coefficient. Indicates the exponential factor. Indicates signal amplitude. Indicates the effective value of the noise. This represents the noise adjustment factor.

8. The method for generating hexadecimal signals for a control circuit as described in any one of claims 1, characterized in that, The step of generating the eye diagram verification matrix corresponding to the signal verification sequence based on the time-series convergence confidence includes: Analyze the temporal verification threshold corresponding to the temporal convergence confidence score; Based on the time-series verification threshold, the time-sensitive path in the signal verification sequence is obtained; Query the level transition data corresponding to the timing-sensitive path; Collect timing jitter indicators from the level conversion data; Based on the timing jitter index, an eye diagram verification matrix corresponding to the signal verification sequence is generated.

9. A signal device, said signal device storing a computer data program, characterized in that, When the computer data program is executed by the processor, it implements the steps of the control circuit hexadecimal signal generation method as described in any one of claims 1 to 8.

10. A multi-functional controller, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the control circuit hexadecimal signal generation method as described in any one of claims 1 to 8.

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