Chip design method, device and medium

Abstract

The invention discloses a chip design method, chip design equipment and a medium, and relates to the technical field of chips, during chip design, a target module in a chip is firstly determined, power supply planning of the target module is independently adjusted to avoid the influence of voltage drop on crosstalk when the wiring density is too large, crosstalk prevention is started in advance in the power supply planning stage, and the crosstalk is prevented from being damaged. After the layout and wiring design of the chip is carried out according to the power supply plan and the module layout, the crosstalk condition existing in the chip is directly analyzed, and if the crosstalk occurs in a target module, a mode of enlarging the layout space of the target module is adopted to cope with the crosstalk; if crosstalk occurs in other modules, a mode of adjusting electrical parameters of a signal line is adopted to cope with the crosstalk. Crosstalk prevention is carried out in the chip design stage, and different response modes are adopted according to different areas where crosstalk is located, so that the influence of crosstalk on normal working of the chip is avoided, and the accuracy and stability of the chip during working are improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip design method, apparatus and medium. Background Technology

[0002] With the rapid development of chip manufacturing technology, integrated circuit design is moving towards the goals of multifunctionality, high performance, low power consumption, ultra-high speed, portability, high yield, long lifespan, and short design cycle. Simultaneously, device size is shrinking proportionally, and the number of transistors that can be placed on a chip is increasing dramatically. As functions become more complex, chips are no longer limited to single-function circuits but are composite systems integrating digital and analog circuits. The increased frequency and component density also lead to increasingly severe crosstalk problems, which can interfere with signal reception and affect the correctness and stability of electronic system operation.

[0003] It is evident that how to deal with crosstalk in chips is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a chip design method, device, and medium that can solve the problem of crosstalk affecting the normal operation of a chip.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a chip design method, comprising:

[0006] Identify the target module in the chip; the target module is the module with the highest wiring density in the chip.

[0007] The power planning of the chip is determined based on the chip module layout, and the power planning of the target module is adjusted when the power planning of the target module does not meet the voltage drop specifications of the chip.

[0008] Layout and wiring should be carried out according to power planning and module layout;

[0009] Analyze the crosstalk of each signal line in the chip after the placement and routing are completed;

[0010] If crosstalk exists in the target module, the layout space of the target module will be increased by a preset value, and the process will jump back to the layout and routing steps based on power planning and module layout.

[0011] If crosstalk exists in other modules, the electrical parameters of the corresponding signal lines are adjusted to repair the crosstalk. Other modules refer to modules in the chip other than the target module.

[0012] Optionally, the target module in the chip is determined, including:

[0013] The chip is physically synthesized according to the predetermined layout plan and the chip's physical parameters to obtain the chip's module layout.

[0014] Analyze the signal flow between modules in the module layout to determine the interaction breadth of each module;

[0015] The module with the greatest interaction breadth is identified as the target module.

[0016] Optionally, the power planning of the chip is determined based on the chip's module layout, including:

[0017] Determine the module layout corresponding to each module in the chip, and identify the target sub-modules that need to be powered in each module;

[0018] The power planning of the chip is determined based on the principle that each module has a corresponding power line and that the power line will pass through each target sub-module in the module.

[0019] Optionally, layout and wiring may be performed according to power planning and module layout, including:

[0020] Arrange the chip's power lines according to the power supply plan;

[0021] Arrange the modules according to the module layout;

[0022] The signal lines of the chip are arranged based on the signal flow between the arranged modules to complete the chip placement and routing.

[0023] Optionally, the power planning of the chip is determined based on the chip's module layout, and the power planning of the target module is adjusted when the power planning of the target module does not meet the chip's voltage drop specifications, including:

[0024] Chip power planning is determined by chip module layout.

[0025] Verify whether the first power network in the power planning meets the chip's voltage drop specifications; where the first power network is the power network of all modules in the chip other than the target module.

[0026] If the first power network does not meet the chip's voltage drop specifications, then jump back to the step of determining the chip's power planning based on the chip's module layout to redetermine the chip's power planning.

[0027] If the first power network meets the chip's voltage drop specifications, then verify whether the second power network in the power planning meets the chip's voltage drop specifications; where the second power network is the power network of the target module.

[0028] If the second power network does not meet the chip's voltage drop specifications, adjust the second power network and jump back to the step of verifying whether the second power network in the power planning meets the chip's voltage drop specifications.

[0029] If the second power network meets the chip's voltage drop specifications, then proceed to the placement and routing step based on power planning and module layout.

[0030] Optionally, the layout space of the target module can be increased by a preset value, including:

[0031] Determine the reserved space around the target module; where the reserved space is the unoccupied space reserved between each module when determining the module layout of the chip;

[0032] Adjust the chip module layout by merging the target module with the preset space to increase the layout area of ​​the target module; where the preset space is a space of a preset value in the reserved space.

[0033] Optionally, the electrical parameters of the signal line include the length of the signal line; adjusting the electrical parameters of the corresponding signal line to correct crosstalk present in the signal line includes:

[0034] If there is crosstalk between the first signal line and the second signal line in other modules, the target signal line is determined; wherein, the target signal line is the longer signal line among the first signal line and the second signal line.

[0035] A buffer is used to split the target signal line to repair the crosstalk between the first signal line and the second signal line.

[0036] Optionally, the electrical parameters of the signal line include the driving capability of the signal line; adjusting the electrical parameters of the corresponding signal line to repair crosstalk present in the signal line includes:

[0037] Identify the affected signal line corresponding to the crosstalk;

[0038] Increase the driving capability of the damaged signal line to the target value to repair the crosstalk present in the signal line.

[0039] To address the aforementioned technical problems, embodiments of the present invention also provide an electronic device, comprising:

[0040] Memory, used to store computer programs;

[0041] A processor is used to execute computer programs to implement the steps of the chip design method described above.

[0042] To address the aforementioned technical problems, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned chip design method.

[0043] As can be seen from the above technical solution, the target module in the chip is first identified, and the power supply planning of the target module is independently adjusted to avoid the impact of voltage drop on crosstalk when the wiring density is too high. Crosstalk prevention begins in the power supply planning stage. After the chip layout and routing design is carried out according to the power supply planning and module layout, the crosstalk situation in the chip is directly analyzed. If the crosstalk occurs in the target module, the layout space of the target module is increased to deal with it; if the crosstalk occurs in other modules, the electrical parameters of the signal lines are adjusted to deal with it. The beneficial effect of this invention is that crosstalk prevention is carried out in the chip design stage, and different coping methods are adopted according to different areas where crosstalk occurs, thereby avoiding the impact of crosstalk on the normal operation of the chip and improving the accuracy and stability of the chip during operation. Attached Figure Description

[0044] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A schematic flowchart of a chip design method provided in an embodiment of the present invention;

[0046] Figure 2 A schematic flowchart of another chip design method provided in an embodiment of the present invention;

[0047] Figure 3 A schematic diagram of a chip module layout and signal flow provided for an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of power planning for a chip after voltage drop specification verification, provided as an embodiment of the present invention.

[0049] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0051] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0052] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] Next, a chip design method provided by an embodiment of the present invention will be described in detail. See also Figure 1 As shown, Figure 1 This is a flowchart illustrating a chip design method provided in an embodiment of the present invention; the chip design method includes:

[0054] S11: Identify the target module in the chip; where the target module is the module with the highest wiring density in the chip;

[0055] Understandably, signal integrity (SI) is crucial for chip applications. Signal integrity refers to the ability of a signal to maintain its quality and timing characteristics during transmission, directly affecting the performance and reliability of the chip. However, signal crosstalk can affect signal integrity, leading to logic and timing problems that prevent the chip from achieving correct timing convergence or functioning properly. Crosstalk occurs when two or more signal traces are spaced apart and distributed in parallel. Coupling capacitance exists between them, transmitting pulses from one node to another. The signal energy on one trace is coupled to an adjacent trace (the victim signal line) through this capacitance, causing noise or distortion to superimposed on the original signal, ultimately compromising signal integrity. Crosstalk is more likely to occur when signal lines are close together, meaning that areas with high wiring density are more prone to crosstalk problems, as these areas typically involve dense signal lines and higher current demands. Therefore, in order to facilitate the subsequent resolution of crosstalk, this application will first identify the module with the highest wiring density in the chip after the chip module layout is completed, so that the crosstalk of the target module can be processed separately in the future.

[0056] It should be noted that a module in a chip refers to a collection of independent logic or circuit units within the chip, divided according to specific functions or physical attributes. These modules work together through internal interconnections (such as buses and signal paths) to achieve the overall function of the chip. This application does not impose any special limitations on the specific implementation methods of the chip and its modules, nor on the specific methods for determining the target modules. Similarly, this application does not impose any special limitations on the specific implementation methods of the chip's module layout; reasonable floorplanning and placement can reduce the probability of signal crosstalk.

[0057] S12: Determine the power planning of the chip based on the chip module layout, and adjust the power planning of the target module when the power planning of the target module does not meet the voltage drop specifications of the chip.

[0058] It's easy to understand that each module of a chip needs power to function properly. Therefore, after determining the chip's module layout, it's necessary to further define the chip's power plan to ensure a stable, clean, and efficient power supply for the chip in various operating scenarios. This application does not impose specific limitations on the power planning methods. Considering the significant difference in wiring density between the target module and other modules, the target module can be isolated during power planning, with separate first power networks for other modules and second power networks for the target module. Because the target module has a relatively high wiring density, it is more prone to large voltage drops and has weaker crosstalk immunity. Crosstalk can easily lead to logic misjudgments or timing violations in the target module. Therefore, if the power plan for the area where the target module is located does not meet the voltage drop specifications during power planning, the power plan for the target module can be adjusted separately to prevent large voltage drops from occurring during the power planning stage, thereby reducing the probability of subsequent crosstalk.

[0059] S13: Perform layout and wiring according to power planning and module layout;

[0060] Understandably, after determining the chip's module layout and power planning, the power lines on the chip can be laid out according to the power planning; and the layout can be carried out according to the module layout, allocating the logic units representing each module in the netlist to specific physical locations on the chip. Then, the signal lines between the modules on the chip can be laid out according to the signal transmission situation of each module corresponding to the module layout; finally, the chip's placement and routing are completed.

[0061] S14: Analyze the crosstalk of each signal line in the chip after the placement and routing are completed;

[0062] It is easy to understand that after the placement and routing are completed, crosstalk analysis can be performed. The goal of crosstalk analysis is to quantify the coupling noise between adjacent signal lines in the chip, and then verify whether this noise will cause timing violations or logic misjudgments. If it will cause signal errors, then crosstalk is determined to exist between the corresponding signal lines. This application does not impose any special limitations on the specific implementation method of crosstalk analysis; it can be achieved through simulation tools or testing the chip with testing equipment.

[0063] S15: If crosstalk exists in the target module, the layout space of the target module will be increased by a preset value, and the process will jump back to the layout and routing steps based on power planning and module layout.

[0064] Understandably, to effectively address crosstalk issues and reduce the number of crosstalk analysis iterations required to achieve timing convergence, this application handles crosstalk in two scenarios. If crosstalk occurs in the area where the target module is located, the application returns to the initial chip design steps from a module layout perspective, adjusting the initially determined chip module layout. This is done by increasing the layout space of the target module to increase the spacing between signal lines, thereby reducing crosstalk and achieving crosstalk recovery. Since the chip module layout has changed at this point, the application needs to jump back to step S13, adjust the chip layout and routing according to the adjusted module layout, and then repeat step S14. This process continues until crosstalk no longer exists in the area where the target module is located. This application does not impose specific limitations on the specific values ​​of the preset values, and there are multiple options for the specific implementation of the layout space adjustment; this application does not impose any specific limitations on these options either.

[0065] S16: If crosstalk exists in other modules, adjust the electrical parameters of the corresponding signal lines to repair the crosstalk; where other modules are modules in the chip other than the target module.

[0066] On the other hand, if crosstalk occurs in other modules, since the wiring density of those modules is relatively low, there is no need to adjust the chip layout. The crosstalk can be repaired directly by adjusting the electrical parameters of the corresponding signal lines. The electrical parameters of the signal lines include the length, width, and driving capability of the signal lines, etc., which are not specifically limited in this application.

[0067] As one specific embodiment, see Figure 2 As shown, Figure 2This is a flowchart illustrating another chip design method provided by an embodiment of the present invention. The chip is designed as modules according to application requirements, then the modules are laid out and physically synthesized. Based on the results of physical synthesis, the interaction methods between modules are obtained by analyzing the data flow, as well as the breadth of interaction between any given module and other modules. If a module has strong interaction with multiple other modules, it indicates that the wiring density in the area where that module is located is high, and it is identified as the target module. Then, based on the results of physical synthesis, the chip's power supply planning is completed, and the voltage drop specifications of the power network obtained from the power supply planning are detected and verified. After verification, the chip is laid out and routed, and crosstalk analysis and repair are performed after the layout and routing.

[0068] This invention identifies the target module after chip module placement and ensures that the voltage drop of the target module's power network meets design requirements with a certain margin by analyzing voltage drop and adjusting power planning. Then, placement and routing are performed, along with crosstalk analysis and repair. Crosstalk prevention begins early in chip design, minimizing its occurrence during power planning to save routing resources. Different solutions are provided for crosstalk in different areas, reducing the number of iterations required for crosstalk analysis and repair to achieve timing convergence. Beyond adjusting the target module's power planning during the power planning stage to reduce crosstalk probability, further crosstalk analysis and repair are conducted to ensure effective resolution of crosstalk issues.

[0069] See Figure 3 As shown, Figure 3 A schematic diagram of a chip module layout and signal flow is provided for an embodiment of the present invention; as an optional embodiment, determining the target module in the chip includes:

[0070] The chip is physically synthesized according to the predetermined layout plan and the chip's physical parameters to obtain the chip's module layout.

[0071] Analyze the signal flow between modules in the module layout to determine the interaction breadth of each module;

[0072] The module with the greatest interaction breadth is identified as the target module.

[0073] It's easy to understand that when designing a chip, the operator first needs to determine a preliminary layout plan based on the chip's subsequent application requirements. This preliminary plan determines the locations of interfaces and memory within the chip, and the chip's size and shape, among other physical parameters, are determined based on application cost constraints and application scenario limitations. This layout plan and the chip's physical parameters are then input as constraints into specific software tools. The software then performs physical synthesis on the chip based on these pre-defined conditions. Physical synthesis refers to optimizing the synthesis results by changing the netlist layout during integrated circuit design. This involves adjusting the netlist layout or modifying / adding nodes without changing the design functionality, thereby optimizing design performance and resource utilization. It also addresses timing, area, and power consumption issues caused by real physical effects, ensuring the chip ultimately functions correctly and achieves its performance goals. Physical synthesis converts the layout plan into a timing-optimized netlist closely related to the layout plan, resulting in the final optimized module layout. Then, through the results of this physical synthesis, the data flow can be analyzed. Data flow refers to the electrical signal flow between modules during actual operation, such as... Figure 3 As shown, arrows indicate signal flow, and double arrows indicate signal interaction between two modules. This application does not impose specific limitations on the chip layout and the specific implementation methods of physical parameters; these need to be set and adjusted according to the actual application requirements of the chip. Similarly, this application does not impose specific limitations on the specific implementation methods of physical synthesis.

[0074] It should be noted that the breadth of interaction refers to the scope and degree of information exchange and functional collaboration between different modules. In this application, it mainly refers to how many different modules a module interacts with, that is, the number of interaction objects of a module. For any module in the chip, by analyzing the data flow, the interaction method between that module and other modules and the number of specific interaction objects can be determined. The greater the breadth of interaction of a module, the more signal lines that the module needs during routing, that is, the higher the routing density. Therefore, by determining the breadth of interaction of each module, the number of interaction objects corresponding to each module can be directly determined to identify the target module with the highest routing density and the area corresponding to that target module. Figure 3 As shown in the figure, the integrated module distribution and interaction diagram are as follows. The chip includes modules A, B, C, D, E, F, G, H, L, and K. Among them, module H interacts with other modules the most frequently, so module H has the highest wiring density. Therefore, module H is identified as the target module.

[0075] Specifically, by analyzing the signal flow, the number of signal lines required for each module can be accurately determined, thereby enabling the identification of the target module. This method is simple, effective, and easy to implement.

[0076] As an optional embodiment, determining the chip's power planning based on the chip's module layout includes:

[0077] Determine the module layout corresponding to each module in the chip, and identify the target sub-modules that need to be powered in each module;

[0078] The power planning of the chip is determined based on the principle that each module has a corresponding power line and that the power line will pass through each target sub-module in the module.

[0079] Understandably, after physical synthesis, power planning, placement and routing, and crosstalk analysis and repair need to be completed sequentially based on the module layout obtained from physical synthesis. First, power planning for the chip is required. Each module in the chip needs power to function properly; therefore, the power lines for each module need to be planned during the design phase. Considering that a module typically contains multiple sub-modules to implement its functions (a sub-module refers to a relatively independent sub-functional block within the module with a specific function), it is also necessary to further determine the target sub-modules that require power. If all sub-modules require power, then the target sub-modules include all sub-modules within the module. When designing the power lines for this module, the power lines need to pass through all target sub-modules in the module to provide power to each target sub-module. This application does not specifically limit the specific implementation method of power planning; a uniform power network composed of power lines can be used. This application also does not specifically limit the specific type and implementation method of the power lines.

[0080] Specifically, during power planning, it is necessary to ensure that each module and each target sub-module within it are powered so that each module can subsequently receive effective power based on this power plan, ensuring the normal operation of the chip.

[0081] As an optional embodiment, layout and routing are performed according to power planning and module layout, including:

[0082] Arrange the chip's power lines according to the power supply plan;

[0083] Arrange the modules according to the module layout;

[0084] The signal lines of the chip are arranged based on the signal flow between the arranged modules to complete the chip placement and routing.

[0085] It's easy to understand that during placement and routing, power lines are typically arranged sequentially, followed by modules and then signal lines. Power lines usually use the topmost, thickest metal layer. When arranging modules, the power connection points in the power planning design and their compatibility with the power network are considered. This application does not impose specific limitations on the specific types and implementation methods of signal lines; hardware placement and routing can be used directly. Considering that crosstalk repair may require adjustments to the module layout, simulated placement and routing can be performed in simulation software first, and the final chip design scheme can be determined after crosstalk repair is completed.

[0086] Specifically, power lines are first laid out to ensure the power supply quality and reliability of the entire chip. Then, modules are laid out to determine the interconnect topology of the chip. Finally, signal lines are laid out based on the laid-out power lines and modules. The whole process meets timing and physical rules to ensure a reliable chip design.

[0087] See Figure 4 As shown, Figure 4 This invention provides a schematic diagram of power planning for a chip after voltage drop specification verification. As an optional embodiment, the power planning of the chip is determined based on the chip's module layout, and the power planning of the target module is adjusted when the target module's power planning does not meet the chip's voltage drop specification, including:

[0088] Chip power planning is determined by chip module layout.

[0089] Verify whether the first power network in the power planning meets the chip's voltage drop specifications; where the first power network is the power network of all modules in the chip other than the target module.

[0090] If the first power network does not meet the chip's voltage drop specifications, then jump back to the step of determining the chip's power planning based on the chip's module layout to redetermine the chip's power planning.

[0091] If the first power network meets the chip's voltage drop specifications, then verify whether the second power network in the power planning meets the chip's voltage drop specifications; where the second power network is the power network of the target module.

[0092] If the second power network does not meet the chip's voltage drop specifications, adjust the second power network and jump back to the step of verifying whether the second power network in the power planning meets the chip's voltage drop specifications.

[0093] If the second power network meets the chip's voltage drop specifications, then proceed to the placement and routing step based on power planning and module layout.

[0094] Understandably, after determining the power plan, it is necessary to further verify the IR drop (voltage drop) of the power network obtained from the power plan to verify whether the power network obtained after the design meets the voltage drop design requirements. Considering that the wiring density of the target module is different from that of other modules, the voltage drop of its corresponding area will be significantly different from that of the corresponding area of ​​other modules. Therefore, this application chooses to verify the voltage drop of the first power network and the second power network separately. After the power plan is completed, it is first determined whether the first power network of the corresponding area of ​​other modules meets the voltage drop specification. If it does not meet the specification, a new power plan needs to be determined. This new power plan is a new power plan obtained after redesigning the entire chip. After the first power network meets the voltage drop specification, it is then determined whether the second power network of the corresponding area of ​​the target module meets the voltage drop specification. If it does not meet the specification, the power plan of the second power network of the corresponding area of ​​the target module is adjusted separately, and a new second power network is determined. This process continues until the second power network meets the voltage drop specification. The first and second power networks that meet the voltage drop specification are determined as the final power plan of the chip, and subsequent placement and routing steps are performed.

[0095] It should be noted that voltage drop refers to the voltage drop caused by the resistance (R) and current (I) of the power network. Voltage drop specification refers to the allowable voltage drop range in the chip design, and generally, a certain design margin is reserved. This application does not specifically limit the specific implementation methods of the first and second power networks, etc. The specific implementation methods of the voltage drop specification need to be determined according to the actual design requirements of the chip; this application does not specifically limit the specific methods of adjusting the power planning and adjusting the second power network. For example... Figure 4 As shown in the figure, the final power plan of the chip is obtained after the second power network is adjusted separately. The second power network in the area where the target module is located is significantly different from the first power network in the area where other modules are located. Different textures represent metal wiring in different layers.

[0096] Furthermore, for secondary power networks with high wiring density, balanced EM (Electromigration) can be considered. When designing and adjusting the secondary power network, the maximum allowable current density of its metal paths is limited. After voltage drop verification, the current distribution of the secondary power network is calculated using methods such as power consumption simulation to check whether the current density on all metal paths exceeds the limit. For locations exceeding the limit, the network is optimized or redesigned. By further considering balanced EM, the probability of crosstalk occurring in the target module area is further reduced, improving the overall reliability of the chip.

[0097] Specifically, during power planning, it's crucial to consider in advance whether the power network meets voltage drop requirements. This is especially important for the secondary power network corresponding to target modules with high wiring density, which can be individually adjusted to meet these requirements, thus preventing crosstalk proactively. If the voltage drop requirement isn't met, a separate power network optimization strategy is developed for the target module's area, optimizing the wiring paths and current distribution of the power lines to reduce parasitic parameters and prevent crosstalk. After physical synthesis, the results are used to predict areas with high wiring density, and power planning in these areas is used to prevent crosstalk problems. This proactive prevention effectively reduces the number of iterations required for crosstalk analysis and repair to achieve timing convergence.

[0098] As an optional embodiment, increasing the layout space of the target module by a preset value includes:

[0099] Determine the reserved space around the target module; where the reserved space is the unoccupied space reserved between each module when determining the module layout of the chip;

[0100] Adjust the chip module layout by merging the target module with the preset space to increase the layout area of ​​the target module; where the preset space is a space of a preset value in the reserved space.

[0101] It is easy to understand that if the crosstalk occurs in the area corresponding to the target module, it is necessary to return to the chip placement stage. This involves increasing the placement area of ​​the target module using extra space around it, thus dispersing signal lines and reducing interference. After reconfiguring the target module's placement area, placement and routing are performed again, and crosstalk analysis is repeated iteratively until the crosstalk is completely or adequately repaired. To ensure sufficient space for crosstalk repair in the target module, reserved space can be designed between the various modules during the initial chip placement planning and module placement. In particular, after determining the target module, a larger reserved space can be designed around it. This application does not impose specific limitations on the specific implementation of the reserved space. The specific size of the reserved space can be determined based on the mechanical energy of the iterative operations during actual crosstalk repair, and this application does not impose specific limitations on it.

[0102] Specifically, for the target module, it is necessary to return to the layout stage to adjust its corresponding layout area, fundamentally reduce the physical source of crosstalk, and ensure the effective resolution of crosstalk on high-density signal lines in the target module, saving time and ensuring the reliability of the chip.

[0103] As an optional embodiment, the electrical parameters of the signal line include the length of the signal line; adjusting the electrical parameters of the corresponding signal line to repair crosstalk present in the signal line includes:

[0104] If there is crosstalk between the first signal line and the second signal line in other modules, the target signal line is determined; wherein, the target signal line is the longer signal line among the first signal line and the second signal line.

[0105] A buffer is used to split the target signal line to repair the crosstalk between the first signal line and the second signal line.

[0106] It is understandable that if crosstalk occurs in the region corresponding to other modules, the crosstalk situation in the region of other modules will be less severe than that in the region of the target module. Therefore, to reduce the impact on chip area, the signal lines can be directly adjusted. Specifically, a long signal line can be divided into two or more shorter segments by inserting a buffer into the signal line. This reduces the parallel length of any shorter segment, effectively reducing the total coupling capacitance of the signal line and the resulting crosstalk noise. At the same time, the inserted buffer can act as a driver, reducing the output impedance of the second half of the signal line corresponding to the buffer, canceling noise interference, and maintaining signal stability. This application does not make any special limitations on the specific type and implementation of the buffer. Buffers can also be used to divide another signal line other than the target signal line in the first and second signal lines, or two buffers can be used simultaneously to divide the first and second signal lines respectively. There are various options for adjusting the signal line length, and it is not limited to the implementation method provided in this embodiment. This application does not make any special limitations here.

[0107] Specifically, for crosstalk from other modules, buffers can be used to precisely resolve crosstalk generated by specific signal lines, resulting in lower costs, avoiding excessive impact on chip area and power consumption, and effectively improving the anti-interference capability of specific signal lines.

[0108] As an optional embodiment, the electrical parameters of the signal line include the driving capability of the signal line; adjusting the electrical parameters of the corresponding signal line to repair crosstalk present in the signal line includes:

[0109] Identify the affected signal line corresponding to the crosstalk;

[0110] Increase the driving capability of the damaged signal line to the target value to repair the crosstalk present in the signal line.

[0111] It is easy to understand that, considering the amplitude of crosstalk noise largely depends on the drive strength of the affected signal line (which refers to a signal line whose performance or signal quality has deteriorated due to interference), the crosstalk of a specific signal line can be repaired by addressing its drive capability. There are various ways to adjust the drive capability, such as indirectly increasing the drive by increasing the width of the affected signal line to reduce its impedance, directly replacing the driver corresponding to the affected signal line with a more powerful driver, or adding an amplifier. The specific methods for improving the drive capability and the specific values ​​of the target values ​​can be designed and adjusted according to actual application requirements; this application does not impose any particular limitations here.

[0112] Specifically, by strengthening the driving capability of the affected signal line itself to resist interference, crosstalk can be fundamentally repaired. This method is more precise, efficient, has less impact on the chip design itself, and does not incur significant delay costs.

[0113] See Figure 5 As shown, Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. To solve the above-mentioned technical problems, an embodiment of the present invention also provides an electronic device, comprising:

[0114] Memory 60 is used to store computer programs;

[0115] Processor 61 is used to execute computer programs to implement the steps of the chip design method as described above.

[0116] The electronic devices provided in this embodiment may include, but are not limited to, smartphones, tablets, laptops, or desktop computers.

[0117] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0118] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the chip design method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, and the storage method may be temporary or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, data in the chip design method.

[0119] In some embodiments, the electronic device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0120] Those skilled in the art will understand that Figure 5 The structures shown do not constitute a limitation on electronic devices and may include more or fewer components than those shown.

[0121] For a description of the features in the electronic device provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the chip design method, which will not be repeated here.

[0122] It is understood that if the chip design method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0123] To address the aforementioned technical problems, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned chip design method.

[0124] For a description of the features in the computer-readable storage medium provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the chip design method, which will not be repeated here.

[0125] To address the aforementioned technical problems, embodiments of the present invention also provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the aforementioned chip design method.

[0126] For a description of the features in the computer program product provided in the embodiments of the present invention, please refer to the relevant descriptions in the embodiments of the chip design method, which will not be repeated here.

[0127] To address the aforementioned technical problems, embodiments of the present invention also provide a chip design apparatus, comprising:

[0128] The target module determination unit is used to determine the target module in the chip; wherein, the target module is the module with the highest wiring density in the chip;

[0129] The power planning unit is used to determine the power planning of the chip based on the chip module layout, and to adjust the power planning of the target module when the power planning of the target module does not meet the voltage drop specifications of the chip.

[0130] Layout and routing unit, used for layout and routing according to power planning and module layout;

[0131] The crosstalk analysis unit is used to analyze the crosstalk of each signal line in the chip after the placement and routing are completed.

[0132] The first repair unit is used to increase the layout space of the target module by a preset value if crosstalk exists in the target module, and then jump back to the step of layout and routing based on power planning and module layout.

[0133] The second repair unit is used to adjust the electrical parameters of the corresponding signal line to repair the crosstalk in the signal line if crosstalk exists in other modules; wherein, other modules are modules in the chip other than the target module.

[0134] For a description of the features in the chip design apparatus provided in the embodiments of the present invention, please refer to the relevant descriptions of the embodiments of the chip design method, which will not be repeated here.

[0135] The foregoing has provided a detailed description of a chip design method, apparatus, and medium provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0136] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0137] The chip design method, apparatus, and medium provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A chip design method, characterized in that, include: Identify the target module in the chip; wherein, the target module is the module with the highest wiring density in the chip; The power planning of the chip is determined based on the chip's module layout, and the power planning of the target module is adjusted when the power planning of the target module does not meet the voltage drop specifications of the chip. Layout and wiring are performed according to the power plan and the module layout; Analyze the crosstalk of each signal line in the chip after the placement and routing are completed; If the target module has crosstalk, the layout space of the target module is increased by a preset value, and the process jumps back to the step of layout and routing based on the power planning and the module layout. If crosstalk exists in other modules, the electrical parameters of the corresponding signal lines are adjusted to repair the crosstalk in the signal lines; wherein, the other modules are modules in the chip other than the target module.

2. The chip design method according to claim 1, characterized in that, Identify the target module in the chip, including: The chip is physically synthesized according to a predetermined layout plan and the chip's physical parameters to obtain the chip's module layout; Analyze the signal flow between modules in the module layout to determine the interaction breadth of each module; The module with the greatest interaction breadth is identified as the target module.

3. The chip design method according to claim 1, characterized in that, Determining the power planning of the chip based on the chip's module layout includes: Determine the module layout corresponding to each module in the chip, and identify the target sub-modules that need to be powered in each module; The power planning of the chip is determined based on the principle that each module has a corresponding power line and that the power line passes through each target sub-module in the module.

4. The chip design method according to claim 1, characterized in that, Based on the power plan and the module layout, the layout and routing are performed, including: The power lines of the chip are arranged according to the power plan; Arrange the modules according to the module layout; The signal lines of the chip are arranged based on the signal flow between the arranged modules to complete the chip layout and routing.

5. The chip design method according to claim 1, characterized in that, The power planning of the target module is determined based on the module layout of the chip, and the power planning of the target module is adjusted when the power planning of the target module does not meet the voltage drop specifications of the chip, including: The power planning of the chip is determined based on the module layout of the chip; Verify whether the first power network in the power plan meets the voltage drop specifications of the chip; wherein, the first power network is the power network of other modules in the chip besides the target module; If the first power network does not meet the voltage drop specification of the chip, then jump back to the step of determining the power planning of the chip based on the chip module layout, so as to redetermine the power planning of the chip. If the first power network meets the voltage drop specifications of the chip, then verify whether the second power network in the power planning meets the voltage drop specifications of the chip; wherein, the second power network is the power network of the target module; If the second power network does not meet the voltage drop specifications of the chip, then the second power network is adjusted, and the process jumps back to the step of verifying whether the second power network in the power plan meets the voltage drop specifications of the chip. If the second power network meets the voltage drop specifications of the chip, then proceed to the step of layout and routing according to the power plan and the module layout.

6. The chip design method according to any one of claims 1 to 5, characterized in that, Increasing the layout space of the target module by a preset value includes: Determine the reserved space around the target module; wherein, the reserved space is the unoccupied space reserved between each module when determining the module layout of the chip; Adjust the module layout of the chip and merge the target module with a preset space to increase the layout area of ​​the target module; wherein, the preset space is a space of a preset value in the reserved space.

7. The chip design method according to any one of claims 1 to 5, characterized in that, The electrical parameters of the signal line include the length of the signal line; Adjusting the electrical parameters of the corresponding signal lines to repair crosstalk present in the signal lines includes: If there is crosstalk between the first signal line and the second signal line in other modules, a target signal line is determined; wherein, the target signal line is the longer signal line between the first signal line and the second signal line. A buffer is used to split the target signal line in order to repair the crosstalk between the first signal line and the second signal line.

8. The chip design method according to any one of claims 1 to 5, characterized in that, The electrical parameters of the signal line include the driving capability of the signal line; Adjusting the electrical parameters of the corresponding signal lines to repair crosstalk present in the signal lines includes: Identify the victim signal line corresponding to the crosstalk; Increase the driving capability of the affected signal line to a target value to repair the crosstalk present in the signal line.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the chip design method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the chip design method as described in any one of claims 1 to 8.

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