Centralized station terminal

Abstract

The invention relates to the technical field of power distribution equipment, and discloses a centralized station terminal which comprises a main control module, an FPGA module, a remote control bus driving circuit, a remote signaling bus driving circuit, a plurality of remote control expansion circuits, a plurality of remote signaling expansion circuits and a plurality of telemetering expansion circuits. Wherein the main control module is provided with a PCIe interface, the FPGA module is connected with the main control module through a PCIe bus, and the remote control bus driving circuit and the remote signaling bus driving circuit are both electrically connected with the FPGA module. And the plurality of remote control expansion circuits are electrically connected with the remote control bus driving circuit and are used for outputting remote control signals. And the plurality of remote signaling expansion circuits are electrically connected with the remote signaling bus driving circuit and are used for receiving the remote signaling signals. And the plurality of telemetering expansion circuits are directly and electrically connected with the FPGA module and are used for receiving telemetering signals. According to the centralized station terminal, the FPGA module can process the telemetering signals received by the multiple telemetering expansion circuits in parallel, and transmits the collected data to the main control module through the PCIe bus at a high speed, so that the equipment data collection efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of power distribution equipment technology, and more specifically to a centralized station terminal. Background Technology

[0002] Distribution Terminal Units (DTUs) are core terminal devices in distribution network automation systems. They are primarily deployed at switching stations, distribution rooms, ring main units, and prefabricated substations in medium-voltage distribution networks. They achieve real-time data acquisition, status signal detection, and execution of remote control commands through "three-remote" functions. Existing DTUs mostly use IIC chips or microcontroller serial ports to acquire remote signaling and telemetry data. This not only results in significant time delays and increases the burden on the software system and programming workload, but the IIC chips themselves lack a high-impedance state. To improve data acquisition efficiency, some DTUs directly use the CPU's GPMC bus to acquire remote signaling and telemetry data. However, the CPU's GPMC bus often requires sequential data acquisition, leaving room for improvement in acquisition efficiency. Furthermore, some CPUs lack a GPMC bus or have incomplete bus interfaces, making the above solutions unfeasible. Summary of the Invention

[0003] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a centralized station terminal that can realize parallel acquisition and processing of telemetry data and improve the data acquisition speed of the equipment.

[0004] To solve the above problems, the technical solution adopted by the present invention is as follows: A centralized station terminal, comprising: a main control module having a PCIe interface; an FPGA module connected to the main control module via a PCIe bus; a remote control bus drive circuit electrically connected to the FPGA module; a remote signaling bus drive circuit electrically connected to the FPGA module; a plurality of remote control expansion circuits electrically connected to the remote control bus drive circuit for outputting remote control signals; a plurality of remote signaling expansion circuits electrically connected to the remote signaling bus drive circuit for receiving remote signaling signals; and a plurality of telemetry expansion circuits electrically connected to the FPGA module for receiving telemetry signals.

[0005] Compared to existing technologies, the advantages of this invention are as follows: This solution uses an FPGA module to handle the acquisition and transmission of telemetry, telesignaling, and remote control data, and transmits the data to the main control module via the faster PCIe bus, reducing the burden on the main control module. It is suitable for domestically produced CPUs that lack a GPMC bus or have an incomplete bus interface. Because the FPGA module has parallel processing capabilities, it can process ADC data acquired by multiple telemetry extension circuits in parallel, thereby improving the device's efficiency in acquiring telemetry data and increasing the overall data acquisition efficiency. Furthermore, the device enhances the driving capability of the FPGA module through telemetry bus driver circuits and remote control bus driver circuits, thereby improving the device's ability to process remote control and telesignaling signals.

[0006] In the aforementioned centralized station terminal, the remote control extension circuit includes a data latch and a first bus transceiver. The input pin of the data latch is electrically connected to the remote control bus drive circuit. The data latch is controlled by a first enable signal output by the FPGA module. The output pin of the data latch is electrically connected to the first input / output pin of the first bus transceiver in a one-to-one correspondence. The second input / output pin of the first bus transceiver outputs the remote control signal. The first bus transceiver is controlled by a second enable signal output by the main control module.

[0007] In the aforementioned centralized station terminal, the output enable control pin of the first bus transceiver is electrically connected to the main control module, and the output enable control pin of the first bus transceiver is connected to a pull-up resistor.

[0008] In the aforementioned centralized station terminal, the remote signaling extension circuit includes a second bus transceiver. The first input / output pin of the second bus transceiver is used to receive the remote signaling signal. The second input / output pin of the second bus transceiver is electrically connected to the remote signaling bus driving circuit. The second bus transceiver is controlled by the third enable signal output by the FPGA module.

[0009] In the aforementioned centralized station terminal, the telemetry extension circuit includes an analog-to-digital converter (ADC). The analog input / output pins of the ADC are used to receive the telemetry signals, and the digital input / output pins of the ADC are electrically connected to the FPGA module. The ADC is controlled by a fourth enable signal, a read control signal, and a write control signal output by the FPGA module.

[0010] In the aforementioned centralized station terminal, the remote control bus drive circuit includes a third bus transceiver. The first input / output pin of the third bus transceiver is electrically connected to the remote control expansion circuit, and the second input / output pin of the third bus transceiver is electrically connected to the FPGA module.

[0011] In the aforementioned centralized station terminal, the remote signaling bus driving circuit includes a fourth bus transceiver. The first input / output pin of the fourth bus transceiver is electrically connected to the remote signaling expansion circuit, and the second input / output pin of the fourth bus transceiver is electrically connected to the FPGA module.

[0012] In the aforementioned centralized station terminal, a set of input / output pins of the FPGA module is defined as a remote control & remote signaling data bus, and both the remote control bus driver circuit and the remote signaling bus driver circuit are electrically connected to the remote control & remote signaling data bus.

[0013] In the aforementioned centralized station terminal, several sets of input and output pins of the FPGA module are respectively defined as several ADC data buses, and several telemetry expansion circuits are electrically connected to several ADC data buses.

[0014] The aforementioned centralized station terminal includes at least four sets of remote control extension circuits, at least four sets of remote signaling extension circuits, and at least four sets of telemetry extension circuits. Each set of remote control extension circuits can output at least 16 remote control signals, each set of remote signaling extension circuits can receive at least 16 remote signaling signals, and each set of telemetry extension circuits can receive at least 16 telemetry signals.

[0015] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the centralized station terminal according to an embodiment of the present invention.

[0017] Figure 2 This is a circuit schematic diagram of the PCIe bus of the FPGA module in an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of the remote signaling bus driving circuit according to an embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of the remote control bus drive circuit according to an embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram of the first remote control extension circuit according to an embodiment of the present invention.

[0021] Figure 6 This is a schematic diagram of the second remote control extension circuit according to an embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of the third remote control extension circuit according to an embodiment of the present invention.

[0023] Figure 8This is a schematic diagram of the fourth remote control extension circuit according to an embodiment of the present invention.

[0024] Figure 9 This is a schematic diagram of the first remote signaling extension circuit according to an embodiment of the present invention.

[0025] Figure 10 This is a schematic diagram of the second remote signaling extension circuit according to an embodiment of the present invention.

[0026] Figure 11 This is a schematic diagram of the third remote signaling extension circuit according to an embodiment of the present invention.

[0027] Figure 12 This is a schematic diagram of the fourth remote signaling extension circuit according to an embodiment of the present invention.

[0028] Figure 13 This is a schematic diagram of the first telemetry extension circuit according to an embodiment of the present invention.

[0029] Figure 14 This is a schematic diagram of the second telemetry extension circuit according to an embodiment of the present invention.

[0030] Figure 15 This is a schematic diagram of the third telemetry extension circuit according to an embodiment of the present invention.

[0031] Figure 16 This is a schematic diagram of the fourth telemetry extension circuit according to an embodiment of the present invention.

[0032] Figure 17 This is a circuit schematic diagram of the remote control and remote signaling data bus of the FPGA module in an embodiment of the present invention.

[0033] Figure 18 This is a circuit schematic diagram of the first and second ADC data buses of the FPGA module in an embodiment of the present invention.

[0034] Figure 19 This is a circuit schematic diagram of the third and fourth ADC data buses of the FPGA module in an embodiment of the present invention. Detailed Implementation

[0035] The embodiments of the present invention are described in detail below, with reference to... Figure 1This invention provides a centralized station terminal, comprising a main control module with a PCIe interface, an FPGA (Programmable Gate Array) module, a remote control bus driver circuit, a remote signaling bus driver circuit, several remote control expansion circuits, several remote signaling expansion circuits, and several telemetry expansion circuits. The FPGA module is electrically connected to the main control module via the PCIe bus. The remote control expansion circuits are electrically connected to the FPGA module via the remote control bus driver circuit, the remote signaling expansion circuits are electrically connected to the FPGA module via the remote signaling bus driver circuit, and the telemetry expansion circuits are directly electrically connected to the FPGA module. The remote control expansion circuits output remote control signals, the remote signaling expansion circuits receive remote signaling signals, and the telemetry expansion circuits receive telemetry signals. The FPGA module transmits the remote signaling data and telemetry data collected by the remote signaling and telemetry expansion circuits to the main control module via the PCIe bus. The main control module generates control commands based on the collected real-time remote signaling data and telemetry data. The FPGA module generates remote control signals based on the control commands and transmits them to remote devices via the remote control expansion circuits, thereby controlling the remote devices.

[0036] This centralized station terminal uses an FPGA module to process the acquisition and transmission of telemetry, telesignaling, and remote control data, and transmits the data to the main control module via a high-speed PCIe bus, reducing the burden on the main control module. It is suitable for domestic CPUs that do not have a GPMC (General Purpose Memory Controller) bus or have an incomplete bus interface. The PCIe bus is an upgraded version of the PCI bus, offering significant improvements in data transmission speed, bandwidth, and flexibility. PCIe 1.0 and 2.0 use 8b / 10b encoding, with each byte (8b) transmitted using 10 bits, achieving bandwidth speeds of 250MB / s and 500MB / s at 2.5GHz and 5GHz clock speeds, respectively. PCIe 3.0 and 4.0 use 128b / 130b encoding, further reducing waste and achieving a bandwidth of 1000MB / s at 8GHz clock speed. Therefore, by using the PCIe bus, data collected by the FPGA module can be transmitted to the main control module, significantly improving the transmission efficiency of telemetry, remote control, and remote signaling data compared to the GPMC bus with a transmission speed of no more than 100MB / s, thus enhancing the real-time performance of data and control. Furthermore, due to the parallel processing capability of the FPGA module, compared to using the GPMC bus of the CPU module to acquire telemetry data, it can simultaneously process ADC data acquired by multiple telemetry expansion circuits without waiting in queues to process the ADC data acquired by each telemetry expansion circuit, saving ADC data acquisition time and further improving the data transmission efficiency of the equipment. Directly acquiring ADC data from four AD76176 chips via the CPU's GPMC bus takes approximately 17.60µs, while the solution in this embodiment of the invention takes approximately the acquisition time of one AD7616 chip, or 4.23µs, saving 3 / 4 of the time. This meets the sampling rate requirement of 180 points per cycle and may even meet the future requirement of 256 points per cycle. Since the FPGA module itself contains logic processing circuitry, this centralized station terminal equipment eliminates the need for additional CPLD (Programmable Logic Device) logic processing chips; the expansion cost is mainly in the FPGA module, resulting in high cost-effectiveness.

[0037] Reference Figure 1 In this embodiment, the main control module uses TI's industrial-grade control chip AM6442. This chip features five native Gigabit Ethernet ports, a 16-bit GPMC data bus, a 133MHz bus speed, dual-core ARM Cortex-A53, single / quad-core Cortex-R5F with a clock speed of up to 1.0GHz, a real-time processing core with a clock speed of up to 800MHz, a computing power of up to 6720 DMIPS, and also includes a PCIe 2.0 bus. Figure 2As can be seen, the FPGA module only needs three sets of differential lines—one pair for receiving, one pair for transmitting, and one pair as clock lines—to complete the connection of one PCIe bus channel, resulting in fewer connection lines. Understandably, the main control module can also use Rockchip RK series processors, such as the RK3568, RK3562, and RK3588, or other chips with PCIe bus interfaces, such as the Allwinner T536 series.

[0038] Reference Figures 17 to 19 In this embodiment, the FPGA module U18 adopts the PH1A series from Anlu Technology. The centralized station terminal includes four remote control expansion circuits, four remote signaling expansion circuits, and four telemetry expansion circuits. Each remote control expansion circuit can output 16 remote control signals, each remote signaling expansion circuit can receive 16 remote signaling signals, and each telemetry expansion circuit can receive 16 telemetry signals, thereby realizing the processing of a total of 64 remote control signals, 64 remote signaling signals, and 64 telemetry signals, meeting the requirements of the State Grid standardized centralized station terminal: 64 telemetry signals, 56 remote signaling signals, and 24 remote control signals. Since the data volume of remote signaling and remote control signals is relatively small, in order to save FPGA input / output pin resources, in this embodiment, remote signaling and remote control signals share a set of FPGA pins as a remote control & remote signaling data bus. However, the four telemetry data channels, due to their larger data volume, need to be controlled separately. The four sets of input / output pins of the FPGA module are configured as four sets of ADC data buses, which are electrically connected to the four telemetry expansion circuits respectively. The logic processing circuit resources within the FPGA module are configured as one remote control & remote signaling bus module and four ADC data bus modules. The remote control & remote signaling bus module is used to process remote control signals and remote signaling signals, while the four ADC data bus modules are used to process the telemetry signals of the four telemetry expansion circuits in parallel, so as to improve the efficiency of the device in acquiring and processing telemetry data.

[0039] Reference Figures 5 to 8In this embodiment, the four-way remote control expansion circuit consists of four data latches U299, U301, U303, and U305, and four first bus transceivers U300, U302, U304, and U306. The input pins of the four data latches, i.e., 1D0 to 2D7, are connected to the remote control bus driver circuit, and the output pins are electrically connected to the first input and output pins of the corresponding first bus transceivers, i.e., 1A0 to 2A7. The four data latches are controlled by four first enable signals FPGA_CS2nA_YK1, FPGA_CS1nB_YK2, FPGA_CS1nC_YK3, and FPGA_CS1nD_YK4 issued by the FPGA module. When any first enable signal is high, the corresponding data latch is selected, receives the remote control signal output by the FPGA module, and temporarily stores it. The second output pins of the four first bus transceivers, namely 1B0 to 2B7, are used to output remote control signals to the corresponding remote devices. The four first bus transceivers are controlled by four sets of second enable signals output by the main control module: KOUTEN_YK10, KOUTEN_YK11; KOUTEN_YK20, KOUTEN_YK21; KOUTEN_YK30, KOUTEN_YK31; KOUTEN_YK40, KOUTEN_YK41. The enable pins of the chips of the four first bus transceivers used to receive the second enable signals are all connected to pull-up resistors to ensure that when the main control module is powered on and the main control module's pins are in the input state, the first bus transceivers are not enabled and are in a high-impedance state, thereby avoiding erratic remote control signal fluctuations. During the initialization of the main control module uboot and kernel, the pins that output these second enable signals are initialized and set to high level. Only when the application is running and the state of these pins is confirmed to be valid, stable, or as expected according to the pre-configuration or settings, the corresponding pins are set to low level, so that the enabled first bus transceiver outputs the remote control signal temporarily stored in the corresponding data latch to the corresponding remote device, thereby realizing reliable control of the remote device.

[0040] Reference Figures 9 to 12In this embodiment, the four-channel remote signaling expansion circuit consists of four second bus transceivers U4, U9, U298, and U297. The first input / output pins 1A0 to 2A7 of the second bus transceivers are connected to multiple remote signaling signals, and the second input / output pins 1B0 to 2B7 are electrically connected to the remote signaling bus driver circuit. The four second bus transceivers are controlled by four third enable signals output by the FPGA module: FPGA_CS2nA_YX1#, FPGA_CS2nB_YX2#, FPGA_CS2nC_YX3#, and FPGA_CS2nD_YX4#. When any third enable signal is low, the corresponding second bus transceiver transmits the received remote signaling signal to the remote signaling bus driver circuit, which then transmits it to the FPGA module. The FPGA module then reads the signal into the main control module via the PCIe bus for processing.

[0041] Reference Figure 3 and Figure 4 In this embodiment, the remote control bus driving circuit and the remote signaling bus driving circuit are respectively composed of a third bus transceiver and a fourth bus transceiver. The first input / output pins 1A0 to 2A7 of the third bus transceiver are electrically connected to the input pins 1D0 to 2D7 of the four data latches, respectively. The second input / output pins 1B0 to 2B7 are electrically connected to the pins of the remote control and remote signaling data bus of the FPGA module, respectively. The first input / output pins 1A0 to 2A7 of the fourth bus transceiver are electrically connected to the second input / output pins 1B0 to 2B7 of the four second bus transceivers, respectively. The second input / output pins 1B0 to 2B7 are also electrically connected to the pins of the remote control and remote signaling data bus of the FPGA module, respectively. In this embodiment, the data latch is selected from the 16-bit AiP74LVC16373 of AMEC, the first bus transceiver is selected from the 16-bit dual-power bus transceiver of AMEC's ​​AiP74LVCH16T245, and the second, third and fourth bus transceivers are selected from the 16-bit dual-power bus transceiver of Nexperia's 74LVCH162245ADGG, which supports dual power supply and has high reliability and stability.

[0042] Reference Figures 13 to 16In this embodiment, the four-channel telemetry expansion circuit consists of four analog-to-digital converters (ADCs) U308, U309, U310, and U311. The analog input / output pins V0A and V0A_GND to V7B and V7B_GND of the 16 analog channels of the ADCs are used to receive the 16 telemetry signals. The 16 digital input / output pins DB0 to DB15 are electrically connected to the corresponding pins of the ADC data bus of the FPGA module. The four ADCs are controlled by four fourth enable signals output by the FPGA module: FPGA_CS0nA_YC1, FPGA_CS0nB_YC2, FPGA_CS0nC_YC3#, and FPGA_CS0nD_YC4#. When the fourth enable signal is low, the corresponding ADC converts the analog telemetry signal into a corresponding digital value, transmits it to the FPGA module via the ADC data bus, and the FPGA module acquires the data from the main control module via the PCIe bus. The four analog-to-digital converters (ADCs) are also controlled by four write control signals (FPGA_RnW_A, FPGA_RnW_B, FPGA_RnW_C, and FPGA_RnW_D) and four read control signals (FPGA_READ_A, FPGA_READ_B, FPGA_READ_C, and FPGA_READ_D) output from the FPGA module. Under the control of these four write and read control signals, they read telemetry signals into the FPGA module. In this embodiment, all four ADCs are 16-channel AD7616 ADCs. It is understood that the centralized station terminal of this embodiment can increase or decrease the number of remote control expansion circuits, remote signaling expansion circuits, and telemetry expansion circuits, or increase or decrease the number of each of these circuits, to meet higher sampling requirements.

[0043] It should be noted that in the description of this invention, any descriptions of orientation, such as up, down, front, back, left, right, etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings. They are only for the purpose of facilitating the description of this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and should not be construed as a limitation of this invention.

[0044] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the stated number, while "above," "below," "within," etc. are understood to include the stated number. If "first" or "second" is mentioned, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0045] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0046] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A centralized station terminal, characterized in that, include: The main control module has a PCIe interface; The FPGA module is connected to the main control module via a PCIe bus; The remote control bus driver circuit is electrically connected to the FPGA module; The remote signaling bus driver circuit is electrically connected to the FPGA module; Several remote control extension circuits are electrically connected to the remote control bus drive circuit and are used to output remote control signals; Several remote signaling extension circuits are electrically connected to the remote signaling bus drive circuit and are used to receive remote signaling signals; Several telemetry extension circuits are electrically connected to the FPGA module and are used to receive telemetry signals.

2. The centralized station terminal according to claim 1, characterized in that, The remote control extension circuit includes a data latch and a first bus transceiver. The input pin of the data latch is electrically connected to the remote control bus driving circuit. The data latch is controlled by a first enable signal output by the FPGA module. The output pin of the data latch is electrically connected to the first input / output pin of the first bus transceiver in a one-to-one correspondence. The second input / output pin of the first bus transceiver outputs the remote control signal. The first bus transceiver is controlled by a second enable signal output by the main control module.

3. The centralized station terminal according to claim 2, characterized in that, The output enable control pin of the first bus transceiver is electrically connected to the main control module, and the output enable control pin of the first bus transceiver is connected to a pull-up resistor.

4. The centralized station terminal according to claim 1, characterized in that, The remote signaling extension circuit includes a second bus transceiver. The first input / output pin of the second bus transceiver is used to receive the remote signaling signal. The second input / output pin of the second bus transceiver is electrically connected to the remote signaling bus driver circuit. The second bus transceiver is controlled by a third enable signal output by the FPGA module.

5. The centralized station terminal according to claim 1, characterized in that, The telemetry extension circuit includes an analog-to-digital converter (ADC). The analog input / output pins of the ADC are used to receive the telemetry signal. The digital input / output pins of the ADC are electrically connected to the FPGA module. The ADC is controlled by a fourth enable signal, a read control signal, and a write control signal output by the FPGA module.

6. The centralized station terminal according to claim 1, characterized in that, The remote control bus driving circuit includes a third bus transceiver. The first input / output pin of the third bus transceiver is electrically connected to the remote control expansion circuit, and the second input / output pin of the third bus transceiver is electrically connected to the FPGA module.

7. The centralized station terminal according to claim 1, characterized in that, The remote signaling bus driving circuit includes a fourth bus transceiver. The first input / output pin of the fourth bus transceiver is electrically connected to the remote signaling expansion circuit, and the second input / output pin of the fourth bus transceiver is electrically connected to the FPGA module.

8. The centralized station terminal according to claim 1, characterized in that, A set of input / output pins of the FPGA module is defined as the remote control & remote signaling data bus, and both the remote control bus driver circuit and the remote signaling bus driver circuit are electrically connected to the remote control & remote signaling data bus.

9. The centralized station terminal according to claim 1, characterized in that, The FPGA module's input / output pins are defined as several ADC data buses, and the telemetry extension circuits are electrically connected to the ADC data buses.

10. The centralized station terminal according to claim 1, characterized in that, It includes at least four sets of the aforementioned remote control extension circuits, at least four sets of the aforementioned remote signaling extension circuits, and at least four sets of the aforementioned telemetry extension circuits. Each set of the aforementioned remote control extension circuits can output at least 16 channels of the aforementioned remote control signals, each set of the aforementioned remote signaling extension circuits can receive at least 16 channels of the aforementioned remote signaling signals, and each set of the aforementioned telemetry extension circuits can receive at least 16 channels of the aforementioned telemetry signals.

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