Analog-to-digital converter circuit

Abstract

The invention provides an analog-to-digital converter circuit. The analog-to-digital converter circuit comprises a programmable gain amplifier (PGA), a buffer, a differential-integral analog-to-digital converter (ADC) and a bandwidth control circuit. The PGA is configured to receive and amplify an input signal to generate an amplified signal. The buffer is configured to receive the amplified signal and output a corresponding buffer signal. The differential-integral ADC is configured to receive the amplified signal or the buffered signal and output a corresponding digital signal. The bandwidth control circuit is configured to generate a first control signal and a second control signal, the first control signal is output to the programmable gain amplifier to control the bandwidth of the programmable gain amplifier, and the second control signal determines to enable or disable the buffer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an analog-to-digital converter circuit, and more particularly to an analog-to-digital converter circuit with controllable bandwidth. BACKGROUND

[0002] High resolution analog-to-digital converters (ADCs) are very common in analog or precision sensing applications. In recent years, high speed high resolution ADCs are required. In order to amplify the input analog signal or other small signals, an amplifier, such as a closed loop amplifier, is usually added in front of the output of the ADC. However, the gain and bandwidth of the closed loop amplifier are basically inversely proportional, that is, the higher the gain, the smaller the bandwidth, which will limit the upper limit of the sampling bandwidth of the high speed ADC, causing the speed of the high speed ADC to be reduced or having a large signal distortion.

[0003] Although adding other circuits with amplifiable bandwidth between the closed loop amplifier and the high speed ADC can solve the problem of insufficient sampling bandwidth of the high speed ADC, it will increase the circuit noise and cause distortion. Therefore, a solution to the above problems is needed. SUMMARY

[0004] An analog-to-digital converter circuit is provided, which includes a programmable gain amplifier, a buffer, a differential integrating analog-to-digital converter, and a bandwidth control circuit. The programmable gain amplifier is configured to receive and amplify an input signal to generate an amplified signal. The buffer is configured to receive the amplified signal and output a corresponding buffer signal. The differential integrating analog-to-digital converter is configured to receive the amplified signal or the buffer signal and output a corresponding digital signal. The bandwidth control circuit is configured to generate a first control signal and a second control signal, wherein the first control signal is output to the programmable gain amplifier to control the bandwidth of the programmable gain amplifier, and the second control signal determines whether to enable or disable the buffer.

[0005] According to some embodiments of the present disclosure, the analog-to-digital converter circuit further includes a switch having a first end and a second end, and the first end is coupled to the input end of the buffer and the second end is coupled to the output end of the buffer, wherein the bandwidth control circuit generates a third control signal to control the switch to be turned on or turned off.

[0006] According to some embodiments of the present disclosure, when the bandwidth of the programmable gain amplifier is not less than the input bandwidth required by the differential integrating analog-to-digital converter, the bandwidth control circuit outputs the second control signal to disable the buffer and outputs the third control signal to turn on the switch, so that the programmable gain amplifier outputs the amplified signal to the differential integrating analog-to-digital converter through the turned-on switch.

[0007] According to some embodiments of the present disclosure, when the bandwidth of the programmable gain amplifier is less than the input bandwidth required by the differential-integral analog-to-digital converter, the bandwidth control circuit outputs a second control signal to enable the buffer and outputs a third control signal to turn off the switch, so that the programmable gain amplifier outputs the amplified signal to the buffer, and the buffer outputs the buffered signal to the differential-integral analog-to-digital converter.

[0008] The present disclosure provides an ADC circuit capable of controlling the bandwidth of a PGA. Through the bandwidth control circuit, a user can determine the gain and bandwidth of the PGA, and let the bandwidth control circuit automatically control the state of the buffer between the PGA and the differential-integral ADC according to the gain and bandwidth of the PGA. If the PGA can provide an input bandwidth not less than the required input bandwidth of the differential-integral ADC due to low gain, the bandwidth control circuit will automatically disable the buffer, so that the PGA can directly output the amplified signal to the differential-integral ADC, thereby reducing the power consumption caused by enabling the buffer for a long time, and at the same time, the output signal of the differential-integral ADC is less affected by noise. If the PGA causes the bandwidth to be less than the required input bandwidth of the differential-integral ADC due to high gain, the bandwidth control circuit will automatically enable the buffer, so that the ADC circuit, while having the high gain of the PGA, provides an input bandwidth not less than the required input bandwidth of the differential-integral ADC through the buffer, to avoid the output signal of the differential-integral ADC from being affected by noise or completely distorted due to insufficient sampling. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1A Figure 1B An example of a differential-integral analog-to-digital converter according to embodiments of the present disclosure.

[0010] Figure 2 A schematic diagram of an analog-to-digital converter circuit according to embodiments of the present disclosure.

[0011] Figure 3A Figure 3B Examples of programmable gain amplifiers according to embodiments of the present disclosure.

[0012] Figure 4 An example of a buffer according to embodiments of the present disclosure.

[0013] LIST OF SYMBOLS

[0014] 10, 130: differential-integral analog-to-digital converter (ADC)

[0015] 22, 24, 26, 28: operational amplifier

[0016] 100: ADC circuit

[0017] ​​110: programmable gain amplifier (PGA)

[0018] 120: buffer

[0019] 140: digital filter

[0020] 150: bandwidth control circuit

[0021] S1, S2, S3, S4, SB: switch

[0022] C1, C2: capacitor

[0023] Vref: reference signal

[0024] Vin, Vin1: input signal

[0025] Vout, Vout1: output signal

[0026] Vamp: amplified signal

[0027] Vbuff: buffered signal

[0028] Vadc: digital signal

[0029] Vpga, Ve, VB: control signal

[0030] Vin_p: positive input signal

[0031] Vin_n: negative input signal

[0032] Vout_p: positive output signal

[0033] Vout_n: negative output signal

[0034] R1, R2: resistor DETAILED DESCRIPTION

[0035] In order to make the above and other objects, features and advantages of the present application more comprehensible, a preferred embodiment will now be described in detail with reference to the drawings.

[0036] The following summary provides some embodiments so that one skilled in the art can more readily understand them. These embodiments are not intended to limit the present application, however. It will be appreciated that one skilled in the art will be able to devise many arrangements which, although not explicitly described herein, will fall within the scope of the embodiments. Embodiments can be adjusted, for example, by changing the order of processes and / or including more or fewer steps than those described herein, without departing from the scope of the embodiments.

[0037] The delta-sigma analog-to-digital converter (ADC) is a widely used high-resolution ADC, and with the increasing demand for high-output-speed delta-sigma ADCs, high-speed delta-sigma ADCs are becoming increasingly important. Figure 1A , Figure 1B Examples of a differential-integral ADC 10 are shown for the first and second halves of a sampling period, respectively. The differential-integral ADC 10 includes switches S1-S4, capacitors C1 and C2, and an operational amplifier.

[0038] like Figure 1A As shown, in the first half of a sampling cycle, switches S1 and S2 are on while switches S3 and S4 are off, causing an input signal Vin to charge capacitor C1. Then, in the second half of a sampling cycle, as... Figure 1B As shown, switches S1 and S2 are open while switches S3 and S4 are open, causing the voltage on capacitor C1 to be transferred to capacitor C2. This voltage is then passed through an operational amplifier and a reference signal Vref to obtain an output signal Vout (i.e., the result of the current sampling period). However, the differential-integral ADC 10 requires a high-bandwidth input due to its over-sampling characteristic. If the input signal Vin's bandwidth is insufficient, the differential-integral ADC 10 will not be able to sample in time, leading to increased noise or distortion of the input signal Vin. To solve these problems, this disclosure provides an ADC circuit with controllable input signal bandwidth.

[0039] Figure 2 An ADC circuit 100 according to an embodiment of this disclosure includes a programmable gain amplifier (PGA) 110, a buffer 120, a differential-integral ADC 130, a digital filter 140, and a bandwidth control circuit 150. The PGA 110 receives an input signal Vin1 (e.g., an analog signal or a precision sensing signal) and amplifies it by a preset amplification factor to generate an amplified signal Vamp, which is then output to the buffer 120. The buffer 120 receives the amplified signal Vamp and outputs a corresponding buffered signal Vbuff to the differential-integral ADC 130. The sampling period operation of the differential-integral ADC 130 is similar to... Figure 1A , Figure 1BThe differential-integral ADC 130 converts the buffered signal Vbuff and outputs a corresponding digital signal Vadc to the digital filter 140. The digital filter 140 filters the digital signal Vadc and outputs an output signal Voutl.

[0040] The bandwidth control circuit 150 generates control signals Vpga, Ve, and VB to control the PGA 110, the buffer 120, and a switch SB, respectively. According to the gain of the PGA 110 (or the gain set by the user), the bandwidth control circuit 150 controls the PGA 110 through the control signal Vpga so that the PGA 110 has optimal parameters such as gain and bandwidth. For example, the bandwidth control circuit 150 increases the current of the PGA 110 (e.g., doubles the current) through the control signal Vpga to increase the bandwidth. For example, if the gain of the PGA 110 is preset to be 32 times or more (e.g., 128 times), the bandwidth of the PGA 110 is excessively reduced due to the high gain. In this case, the bandwidth control circuit 150 outputs the control signal Vpga to increase the current of the PGA 110 to increase the bandwidth, so that the output bandwidth of the PGA 110 is greater than the input bandwidth required by the buffer 120. Then, after the gain and the bandwidth of the PGA 110 are determined, the bandwidth control circuit 150 automatically generates corresponding control signals Ve and VB according to the gain and the bandwidth of the PGA 110. The control signal Ve is used to enable or disable the buffer 120, and the control signal VB is used to control the switch SB to be on or off. Therefore, the bandwidth control circuit 150 can determine whether to skip the buffer 120 in the signal processing process through the control signals Ve and VB.

[0041] Figure 3A 、 Figure 3B The following are examples of the PGA 110 that can be implemented according to the embodiments described in the present disclosure. It should be noted that any circuit suitable for implementing a PGA can be used to implement the PGA 110, and the present disclosure is not limited thereto. Figure 3AThe first type of differential amplifier has a pair of differential input terminals, a pair of differential output terminals, resistors R1 and R2, and an operational amplifier 22. The differential input terminals are configured to receive a positive input signal Vin_p and a negative input signal Vin_n, and the differential output terminals are configured to output a positive output signal Vout_p and a negative output signal Vout_n. The differential input signals of the first type of differential amplifier are separated from the input terminals of the operational amplifier by resistor R1, and thus are suitable for applications in which the positive input signal Vin_p and the negative input signal Vin_n have a certain voltage potential (i.e., a voltage potential that overcomes the resistance value of resistor R1). Assuming an open-loop gain of A, a closed-loop gain of G0, and an open-loop bandwidth of Ft, the following relationships can be derived:

[0042]

[0043] Figure 3B The second type of differential amplifier has a pair of differential input terminals, a pair of differential output terminals, resistors R1 and R2, and operational amplifiers 24 and 26. The second type of differential amplifier uses operational amplifier 24 to receive the positive input signal Vin_p and output the positive output signal Vout_p, and uses operational amplifier 26 to receive the negative input signal Vin_n and output the negative output signal Vout_n. Since the second type of differential amplifier receives the input signals directly through operational amplifiers 24 and 26, it is suitable for applications in which the input signals have a relatively small voltage potential (e.g., sensor signals). Assuming an open-loop gain of A, a closed-loop gain of G0, and an open-loop bandwidth of Ft, the following relationships can be derived:

[0044]

[0045] As described above, the relationships of the first type of differential amplifier and the second type of differential amplifier show that the closed-loop gain G0 is affected by resistors R1 and R2, and the closed-loop bandwidth is affected by the closed-loop gain G0 (e.g., inversely proportional to the closed-loop gain G0). Thus, if the closed-loop gain G0 becomes large, the closed-loop bandwidth becomes small, and when the closed-loop gain G0 becomes too large (e.g., 64 times or 128 times), the closed-loop bandwidth can become too small to support oversampling by the differential ADC 130 (i.e., the closed-loop bandwidth is less than the input bandwidth of the differential ADC 130). At this time, the buffer 120 can be added between the PGA 110 and the differential ADC 130 to ensure that the input bandwidth of the differential ADC 130 is sufficient for sampling to proceed normally.

[0046] Figure 4An example of the buffer 120 according to the embodiments described herein. It should be noted that any circuit suitable for implementing a buffer can be used to implement the buffer 120, and the present disclosure is not limited thereto. Figure 4 The buffer shown has an operational amplifier 28 connected as a unity gain buffer (i.e., with the output fed back to the inverting input), and receives the amplified signal Vamp at the non-inverting input of the operational amplifier 28, and outputs the buffered signal Vbuff from the output of the operational amplifier 28 to the differential integrator ADC 130. Assuming an open loop gain of A, a closed loop gain of G0, and an open loop bandwidth of Ft, the following relationships can be derived:

[0047]

[0048] Furthermore, if the resistances R1 and R2 of the first type differential amplifier are set to be equal, the relationship can be modified as follows: Figure 3A

[0049] That is, the first type differential amplifier of

[0050] Figure 3A may also achieve the effect of a unity gain buffer after adjusting the resistance relationship of the resistances R1 and R2.

[0051] As described above, the relationship of the buffer shown by Figure 4 may be derived that when connected as a unity gain buffer, the closed loop gain G0 is 1 (or approximately equal to 1), so that the closed loop bandwidth is equal to the open loop bandwidth Ft. Therefore, when the buffer 120 is added between the PGA 110 and the differential integrator ADC 130, the input bandwidth of the differential integrator ADC 130 is the output bandwidth of the buffer 120, rather than the closed loop bandwidth of the PGA 110, which varies with the gain. That is, the buffer 120 separates the PGA 110 and the differential integrator ADC 130, and provides the output bandwidth of the buffer 120 itself as the input bandwidth of the differential integrator ADC 130. In this way, the user can set the buffer 120 with sufficient output bandwidth (e.g., not less than the input bandwidth of the differential integrator ADC 130) according to the requirements of the differential integrator ADC 130. Furthermore, since the buffer 120 is connected as a unity gain buffer, it does not significantly affect the high gain provided by the PGA 110.

[0052] Please refer again to Figure 2 ​When the PGA 110 has a low gain (e.g., a gain less than 8), the effect on the close loop bandwidth is also low. Therefore, after determining the gain of the PGA 110, the bandwidth control circuit 150 judges that the amplified signal Vamp can be directly output to the differential integration ADC 130, and thus outputs the control signal VB to turn on the switch SB, and outputs the control signal Ve to disable the buffer 120. Since the two ends of the switch SB are respectively coupled to the input end and the output end of the buffer 120, disabling the buffer 120 and turning on the switch SB will make the amplified signal Vamp directly pass through the switch SB to be output to the differential integration ADC 130 without passing through the buffer 120. Such an operation can not only reduce the power consumption of the enabled buffer 120, but also eliminate the noise caused by the buffer 120, so that the noise performance of the digital signal Vadc output by the differential integration ADC 130 is better.

[0053] On the contrary, when the PGA 110 has a high gain (e.g., a gain greater than or equal to 8), the effect on the close loop bandwidth is also large. Therefore, after determining the gain of the PGA 110, the bandwidth control circuit 150 judges that the amplified signal Vamp needs to pass through the buffer 120 before being output to the differential integration ADC 130, and thus outputs the control signal VB to turn off the switch SB, and outputs the control signal Ve to enable the buffer 120, so that the amplified signal Vamp passes through the buffer 120 to generate the buffer signal Vbuff before being output to the differential integration ADC 130. For the differential integration ADC 130, the input bandwidth at this time is the output bandwidth of the buffer 120, so the required input bandwidth of the differential integration ADC 130 can be ensured, and thus the differential integration ADC 130 can successfully sample while the PGA 110 has a high gain.

[0054] For example, if the differential integrator ADC 130 has a sampling bandwidth of 1 MHz, the input signal (e.g., the input signal Vinl or the buffered signal Vbuff) is usually required to have an input bandwidth of at least 10 times (e.g., 10 MHz). If the PGA 110 has a high gain (e.g., a gain of no less than 8) at this time, directly inputting the amplified signal Vamp to the differential integrator ADC 130 can cause the input bandwidth to be less than 10 MHz due to the excessively high gain, and thus the digital signal Vadc output by the differential integrator ADC 130 can be distorted due to insufficient sampling. At this time, the bandwidth control circuit 150 outputs the control signals Ve and VB to disable the buffer 120 and turn off the switch SB, so that the differential integrator ADC 130 receives the buffered signal Vbuff instead of the amplified signal Vamp. The user only needs to adjust the output bandwidth of the buffer 120 to be no less than the input bandwidth of the differential integrator ADC 130 (e.g., at least 10 MHz in this example), so as to ensure that the digital signal Vadc output by the differential integrator ADC 130 is not distorted due to insufficient sampling while the PGA 110 has a high gain.

[0055] On the contrary, if the PGA 110 has a low gain (e.g., a gain of 1 or 2), the PGA 110 can provide a bandwidth that is no less than the input bandwidth required by the differential integrator ADC 130 (e.g., at least 10 MHz in this example). At this time, the bandwidth control circuit 150 outputs the control signals Ve and VB to disable the buffer 120 and turn on the switch SB, so that the amplified signal Vamp is directly output to the differential integrator ADC 130 through the turned-on switch SB. In this way, the differential integrator ADC 130 can operate normally while reducing the power consumption and noise of the buffer 120.

[0056] The following Table 1 shows an example of the current, gain, bandwidth, and other parameters of the PGA 110, the buffer 120, and the differential integrator ADC 130 controlled by the bandwidth control circuit 150 according to the present disclosure, where Ft_PGA is the closed-loop bandwidth of the PGA 110, I is the bias current of the PGA 110 at a gain of 1, G0 is the closed-loop gain of the PGA 110, and Ft_Buffer is the bandwidth of the buffer 120.

[0057] Table 1

[0058]

[0059] Generally speaking, the frequency bandwidth of the PGA is related to the bias current, and the greater the bias current, the greater the frequency bandwidth of the PGA. For example, as shown in Table 1, when the gain of the PGA 110 is changed to be 32 times or more than 32 times the original gain, the frequency bandwidth control circuit 150 can adjust the bias current of the PGA 110 (e.g., to be 2 times the original bias current) via the control signal Vpga to control the frequency bandwidth of the PGA 110. Assuming that the closed loop gain is G0and the open loop frequency bandwidth is Ft, the bias current I and the closed loop frequency bandwidth of the PGA 110 can be expressed by the following relationships:

[0060] When the bias current = I and the open loop frequency bandwidth = Ft, then

[0061] When the bias current = 2 I and the open loop frequency bandwidth = 2 Ft, then

[0062] That is, if the bias current I is adjusted to be 2 times the original bias current, then the open loop frequency bandwidth is also 2 times the original open loop frequency bandwidth, and the closed loop frequency bandwidth is also 2 times the original closed loop frequency bandwidth, without affecting the closed loop gain G0, to achieve the purpose of increasing the frequency bandwidth of the PGA 110. However, it should be noted that although adjusting the bias current I can increase the frequency bandwidth without affecting the gain of the PGA 110, if the bias current I is increased, the power consumption will also increase, so it is appropriate to adjust the size of the bias current I to increase the frequency bandwidth while maintaining the power consumption similar to that before the bias current I is adjusted.

[0063] In addition, as shown in Table 1, when the PGA 110 has a low gain (e.g., a gain of 1, 2, or 4), since the buffer 120 is disabled, the amplified signal Vamp received by the differential integration ADC 130 has a frequency bandwidth corresponding to the gain multiple of the PGA 110. For example, if the gain of the PGA 110 is 2, then the frequency bandwidth of the amplified signal Vamp is Ft_PGA / 2. In other words, the frequency bandwidth of the PGA 110 at this time is smaller (i.e., is adjusted lower) than when the gain is 1. Conversely, when the PGA 110 has a high gain (e.g., a gain of not less than 8), since the buffer 120 is enabled, the buffered signal Vbuff received by the differential integration ADC 130 has a frequency bandwidth of the buffer 120. Since the frequency bandwidth of the buffer 120 is greater than the frequency bandwidth of the PGA 110 when the PGA 110 has a high gain, and the buffer 120 does not affect the gain of the PGA 110, it can be considered that the frequency bandwidth of the PGA 110 is adjusted higher. Furthermore, when the PGA 110 has a higher gain (e.g., a gain of not less than 32), the frequency bandwidth control circuit 150 also adjusts the bias current I of the PGA 110 via the control signal Vpga to increase the frequency bandwidth of the PGA 110.

[0064] The present disclosure provides an ADC circuit capable of controlling the frequency bandwidth of a PGA. Through a frequency bandwidth control circuit, a user can determine the gain and frequency bandwidth of the PGA and let the frequency bandwidth control circuit automatically control the state of a buffer between the PGA and a differential-integral ADC according to the gain and frequency bandwidth of the PGA. If the PGA can provide an input frequency bandwidth no less than that required by the differential-integral ADC due to a low gain, the frequency bandwidth control circuit will automatically disable the buffer so that the PGA can directly output an amplified signal to the differential-integral ADC, thereby reducing power consumption caused by enabling the buffer for a long time and making the output signal of the differential-integral ADC less affected by noise. If the PGA causes the frequency bandwidth to be less than the input frequency bandwidth required by the differential-integral ADC due to a high gain, the frequency bandwidth control circuit will automatically enable the buffer so that the ADC circuit, while having the high gain of the PGA, provides an input frequency bandwidth no less than that required by the differential-integral ADC through the buffer to avoid the output signal of the differential-integral ADC from being increased in noise or completely distorted due to insufficient sampling. In addition, if the user considers that the frequency bandwidth of the PGA is insufficient for the normal operation of the buffer, the user can also appropriately change the current of the PGA through the frequency bandwidth control circuit to further improve the frequency bandwidth of the PGA while having the PGA with a high gain.

Claims

1. An analog-to-digital converter circuit, characterized by The application comprises: a programmable gain amplifier configured to receive and amplify an input signal to generate an amplified signal; a buffer configured to receive the amplified signal and output a corresponding buffered signal; a differential integrator analog-to-digital converter configured to receive the amplified signal or the buffered signal and output a corresponding digital signal; and a bandwidth control circuit configured to generate a first control signal and a second control signal, wherein the first control signal is output to the programmable gain amplifier to control a bandwidth of the programmable gain amplifier, and the second control signal determines whether to enable or disable the buffer.

2. The analog-to-digital converter circuit of claim 1, wherein, The bandwidth control circuit outputs the first control signal according to a gain of the programmable gain amplifier to control the bandwidth of the programmable gain amplifier.

3. The analog-to-digital converter circuit of claim 2, wherein, The first control signal increases a bias current of the programmable gain amplifier to increase the bandwidth of the programmable gain amplifier.

4. The analog-to-digital converter circuit of claim 1, wherein, The application further comprises: a switch having a first end and a second end, the first end coupled to an input of the buffer, and the second end coupled to an output of the buffer, wherein the bandwidth control circuit generates a third control signal to control the switch to be turned on or turned off.

5. The analog-to-digital converter circuit of claim 4, wherein, When the bandwidth of the programmable gain amplifier is not less than an input bandwidth required by the differential integrator analog-to-digital converter, the bandwidth control circuit outputs the second control signal to disable the buffer, and outputs the third control signal to turn on the switch, so that the programmable gain amplifier outputs the amplified signal to the differential integrator analog-to-digital converter through the turned-on switch.

6. The analog-to-digital converter circuit of claim 4, wherein, When the bandwidth of the programmable gain amplifier is less than the input bandwidth required by the differential integrator analog-to-digital converter, the bandwidth control circuit outputs the second control signal to enable the buffer, and outputs the third control signal to turn off the switch, so that the programmable gain amplifier outputs the amplified signal to the buffer, and the buffer outputs the buffered signal to the differential integrator analog-to-digital converter.

7. The analog-to-digital converter circuit of claim 6, wherein, The bandwidth of the programmable gain amplifier is not less than an input bandwidth required by the buffer.

8. The analog-to-digital converter circuit of claim 6, wherein, The bandwidth control circuit outputs the first control signal to the programmable gain amplifier according to the gain of the programmable gain amplifier to control the bandwidth of the programmable gain amplifier.

9. The analog-to-digital converter circuit of claim 1, wherein, The programmable gain amplifier is a differential amplifier, and the buffer is a unity gain buffer.

10. An analog-to-digital converter circuit, characterized by The application comprises: a programmable gain amplifier configured to receive and amplify an input signal to generate an amplified signal; a buffer configured to receive the amplified signal and output a corresponding buffered signal; a differential integrator analog-to-digital converter configured to receive the amplified signal or the buffered signal and output a corresponding digital signal; and a bandwidth control circuit configured to lower a bandwidth of the programmable gain amplifier when the programmable gain amplifier has a low gain, and to increase the bandwidth of the programmable gain amplifier when the programmable gain amplifier has a high gain.

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