Wafer array test system in integrated circuit manufacturing process

Abstract

The invention discloses a wafer array test system in an integrated circuit manufacturing process, which relates to the technical field of wafer arrays and comprises a wafer electrical property detection module, a wafer electrical property judgment module, a wafer electrical signal difference analysis module and a chip test module. The wafer electrical performance detection value of each chip in each link before subsequent packaging in the integrated circuit manufacturing process is analyzed, whether the chip in the abnormal link exists or not is judged, the speed of positioning to the corresponding manufacturing process link is increased, the troubleshooting period is shortened, the process efficiency is improved, the abnormal process is terminated in time, the linkage risk is reduced, and the personal error is reduced. The wafer micro electrical signal difference value of each chip in each link before subsequent packaging in the integrated circuit manufacturing process is evaluated, each defective chip is screened, classification is carried out, fine defects are captured, the detection precision is improved, the misjudgment rate is reduced, and the problems of missing detection and false detection are reduced.

Description

Technical Field

[0001] This invention relates to the field of wafer array technology, and more specifically to a wafer array testing system in integrated circuit manufacturing processes. Background Technology

[0002] With the rapid development of integrated circuit technology, the integration density of chips continues to rise. On the one hand, the number of contact pads or solder pads on a single chip continues to increase, while their size and spacing continue to shrink. On the other hand, the increased integration density of semiconductor components makes the demand for high-speed signal testing increasingly urgent, in order to meet the stringent requirements of high-precision applications such as 5G communication and artificial intelligence for the high-frequency and high-speed performance of chips. This series of technological evolutions has brought unprecedented challenges to wafer-level testing. Therefore, it is necessary to analyze wafer array test systems in integrated circuit manufacturing processes.

[0003] The prior art, such as the invention application patent with announcement number CN100397606C, discloses a three-dimensional process control monitor (PCM) structure and usage method, which is used to perform three-dimensional electrical testing and failure analysis of integrated circuit interconnects in the integrated circuit manufacturing process. This invention can identify and discover the conductivity defects of integrated circuits, and overcomes other shortcomings of existing technologies, thus making it more suitable for practical use.

[0004] While existing technologies can meet basic requirements for wafer array testing systems in integrated circuit manufacturing processes, they also present some potential defects and challenges, specifically in the following aspects: First, existing technologies do not adequately emphasize the analysis of wafer electrical performance test values ​​for each chip in each stage before back-end packaging in integrated circuit manufacturing processes. This affects the judgment of whether there are chips with abnormal processes, increases the risk of sending chips with performance defects into the packaging stage, increases resource waste caused by ineffective packaging, increases packaging costs, reduces the speed of locating the corresponding process stage, prolongs the problem investigation cycle, reduces process efficiency, affects the timely termination of abnormal processes, increases cascading risks, and increases human error.

[0005] Second, the existing technology is not accurate enough in assessing the differences in the minute electrical signals of each chip in each stage of the integrated circuit manufacturing process before packaging. This affects the screening and classification of defective chips, reduces the ability to detect minute defects, decreases the detection accuracy, increases the false positive rate, increases the occurrence of missed and false detections, and reduces the resource reuse rate and the overall wafer utilization rate. Summary of the Invention

[0006] The purpose of this invention is to provide a wafer array testing system for integrated circuit manufacturing processes, which solves the problems existing in the background art.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention provides a wafer array testing system in integrated circuit manufacturing process, including a wafer electrical performance detection module, a wafer electrical performance judgment module, a wafer electrical signal difference analysis module, and a chip testing module.

[0008] Wafer Electrical Performance Testing Module: By testing the electrical parameters of the wafer arrays of each chip in each stage of the integrated circuit manufacturing process before back-end packaging, the module obtains the chip electrical parameters and then analyzes the wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging.

[0009] Wafer electrical performance judgment module: Based on the obtained wafer electrical performance test values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, it determines whether there are chips in abnormal stages. If not, it proceeds to the next step.

[0010] Wafer Electrical Signal Difference Analysis Module: By contacting the test points on the wafer with the probe card, it captures the minute electrical signal difference parameters of each chip in each stage of the integrated circuit manufacturing process, and evaluates the minute electrical signal difference values ​​of each chip in each stage before packaging.

[0011] Chip testing module: Based on the obtained wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging and the wafer minute electrical signal difference values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging, defective chips are screened and classified.

[0012] Furthermore, the specific analysis method for the wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is as follows: based on the obtained electrical parameters of each chip, which include DC parameters, RF parameters, and memory parameters, the wafer DC compliance index of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is evaluated. Wafer RF compliance index And wafer storage conforms to the index This allows for the evaluation of the wafer electrical performance test values ​​of each chip at each stage of the integrated circuit manufacturing process, before back-end packaging. The specific calculation formula is as follows: ,in, This is represented by the number of each stage. , This is expressed as the number of steps. This is represented by the chip's serial number. , This is expressed as the number of chips. Represented by the logical symbol NOT. Represented as the logical symbol OR, This represents the wafer DC compliance exponent threshold for each stage in the integrated circuit manufacturing process before back-end packaging. This represents the wafer radio frequency compliance index threshold for each stage in the integrated circuit manufacturing process before back-end packaging. This represents the wafer storage compliance threshold for each stage in the integrated circuit manufacturing process before back-end packaging.

[0013] Furthermore, the specific analysis method for the wafer DC compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is as follows: Based on the obtained DC parameters, including the leakage current value and critical voltage value of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the leakage current value and critical voltage value of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process are compared with the safe range of leakage current value and safe range of critical voltage value of the wafer array of each stage before back-end packaging in the integrated circuit manufacturing process stored in the database. If the leakage current value of the wafer array of a certain chip in a certain stage before back-end packaging in the integrated circuit manufacturing process is within the safe range of leakage current value and the critical voltage value is within the safe range of critical voltage value, then the wafer DC compliance index of that chip in that stage before back-end packaging in the integrated circuit manufacturing process is recorded as 1, otherwise it is recorded as -1, thereby obtaining the wafer DC compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process. ,in, The values ​​include 1 and -1.

[0014] Furthermore, the specific analysis method for the wafer radio frequency compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is as follows: Based on the obtained radio frequency parameters, including the frequency delay duration, setup duration, and hold duration of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, and extracting the frequency delay duration compliance interval, setup duration compliance interval, and hold duration compliance interval of the wafer array in each stage before back-end packaging in the integrated circuit manufacturing process from the database, the wafer radio frequency compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is analyzed, and the specific calculation formula is as follows: , This refers to the first stage before back-end packaging in the integrated circuit manufacturing process. The first step of the process The first chip One radio frequency parameter, This refers to the first stage before back-end packaging in the integrated circuit manufacturing process. The first step of the process The first chip Each radio frequency parameter conforms to the range. .

[0015] Furthermore, the specific analysis method for the wafer storage compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is as follows: Based on the obtained storage parameters, including the number of erase / write cycles and data retention time of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the number of erase / write cycles and data retention time of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process are compared with the erase / write cycle compliance intervals and data retention time compliance intervals of the wafer array of each stage before back-end packaging in the integrated circuit manufacturing process stored in the database. If the number of erase / write cycles of the wafer array of a certain chip in a certain stage before back-end packaging in the integrated circuit manufacturing process is within the erase / write cycle compliance interval and the data retention time is within the data retention time compliance interval, then the wafer storage compliance index of that chip in that stage before back-end packaging in the integrated circuit manufacturing process is recorded as 1; otherwise, it is recorded as -1. Thus, the wafer storage compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is obtained. ,in, The values ​​include 1 and -1.

[0016] Furthermore, the specific analysis method for determining whether there is an abnormal chip is as follows: based on the obtained wafer electrical performance test values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, when the wafer electrical performance test value is 1, it indicates that the chip in that stage is in a normal state; when the wafer electrical performance test value is -1, it indicates that there is an abnormal chip, and a warning is issued.

[0017] Furthermore, the specific analysis method for capturing the minute electrical signal difference parameters of each chip in each stage of the wafer array is as follows: according to the test point distribution of the chips on the wafer, the probe positions are arranged and adjusted to correspond to the test points. A laser calibration system is used to perform three-dimensional positioning of the probe card. The contact force between the probe and the test point is monitored in real time by a pressure sensor to obtain the minute electrical signal difference parameters of each chip in each stage of the wafer array. Among them, the minute electrical signal difference parameters of each chip in each stage of the wafer array include: ion implantation deviation, focal length offset distance, return loss and gain flatness of each chip in each stage before back-end packaging in the integrated circuit manufacturing process.

[0018] Furthermore, the specific analysis method for evaluating the wafer micro-electrical signal differences of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is as follows: Based on the obtained ion implantation deviation, focal length offset distance, return loss value, and gain flatness of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the ion implantation deviation, focal length offset distance, return loss value, and gain flatness of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process are compared with the ion implantation deviation safety range and focal length offset of the wafer array in each stage before back-end packaging in the integrated circuit manufacturing process stored in the database. By comparing the safe ranges for shift distance, return loss, and gain flatness, if the ion implantation deviation of a chip in a certain stage before back-end packaging in the integrated circuit manufacturing process is within the safe ranges for ion implantation deviation, focal length shift, return loss, and gain flatness, then the wafer micro-electrical signal difference value of that chip in that stage before back-end packaging is recorded as 1; otherwise, it is recorded as -1. This allows us to obtain the wafer micro-electrical signal difference values ​​for each chip in each stage before back-end packaging in the integrated circuit manufacturing process. ,in, The values ​​include 1 and -1.

[0019] Furthermore, the specific analysis method for screening each defective chip is as follows: based on the obtained wafer electrical performance test values ​​and wafer micro-electrical signal difference values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, when the wafer electrical performance test value or wafer micro-electrical signal difference value of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is 1, the defective chip prediction value is recorded as 1, indicating that chip screening is not required; when the wafer electrical performance test value or wafer micro-electrical signal difference value of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is -1, the defective chip prediction value is recorded as -1, indicating that chip screening is required.

[0020] Furthermore, the classification includes: if The chip in this stage is recorded as having a minor defect, the frequency of monitoring is increased, and a process warning is triggered.

[0021] like The chip in this stage was classified as having a moderate defect, and multiple tests and recalibrations were performed to repair it.

[0022] like The chip in this stage is marked as a critical defect type, and the critical defective chip is separately marked from the wafer batch, discarded to stop losses and prevent it from flowing into the packaging stage.

[0023] If multiple chips in the same stage before packaging in the integrated circuit manufacturing process have the same type of defect, it is judged as a batch defect, and the chip detection scope is expanded; if only a single chip has an isolated parameter abnormality, it is classified as an individual defect, and the real-time monitoring of this stage is strengthened, and the sampling frequency of key parameters is increased.

[0024] The beneficial effects of this invention are as follows: In the wafer electrical performance testing module and the wafer electrical performance judgment module: by performing electrical parameter testing on the wafer arrays of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the chip electrical parameters are obtained. Then, the wafer electrical performance test values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process are analyzed to determine whether there are chips in abnormal stages. If not, the next step is performed, avoiding sending chips with performance defects into the packaging stage. Early detection reduces resource waste caused by invalid packaging, reduces packaging costs, increases the speed of locating the corresponding process stage, shortens the problem investigation cycle, improves process efficiency, terminates abnormal processes in a timely manner, reduces chain risks, and reduces human error.

[0025] In the wafer electrical signal difference analysis module and chip testing module: by contacting the test points on the wafer with the probe card, the minute electrical signal difference parameters of each chip in each stage are captured. The minute electrical signal difference values ​​of each chip in each stage before packaging in the integrated circuit manufacturing process are evaluated, defective chips are screened and classified, and minute defects are captured, thereby improving detection accuracy, reducing false positive rate, reducing the occurrence of missed and false detections, and improving resource reuse rate and overall wafer utilization rate. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the system structure connection of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Reference Figure 1As shown, the present invention provides a wafer array testing system for integrated circuit manufacturing processes, including: a wafer electrical performance testing module, a wafer electrical performance judgment module, a wafer electrical signal difference analysis module, and a chip testing module.

[0030] It should be noted that the wafer electrical performance testing module is connected to the wafer electrical performance judgment module, the wafer electrical performance judgment module is connected to the wafer electrical signal difference analysis module, and the wafer electrical signal difference analysis module is connected to the chip testing module.

[0031] It should be noted that this also includes a database, which stores the following data for each stage of the integrated circuit manufacturing process before back-end packaging: wafer DC compliance index threshold, wafer RF compliance index threshold, wafer storage compliance index threshold, safe range of leakage current and critical voltage values ​​for the wafer array, frequency delay compliance range, setup time compliance range, and hold time compliance range for the wafer array, erase / write cycles compliance range, data hold time compliance range, ion implantation deviation safety range, focal length offset distance safety range, return loss value safety range, and gain flatness safety range.

[0032] It should be noted that the following safety parameters are specified by technical personnel for each stage of the integrated circuit manufacturing process before back-end packaging: wafer DC compliance index threshold, wafer RF compliance index threshold, wafer storage compliance index threshold, safe range of leakage current and critical voltage values ​​for the wafer array, frequency delay compliance range, setup time compliance range, and hold time compliance range for the wafer array, erase / write cycles compliance range, data hold time compliance range, ion implantation deviation safety range, focal length offset distance safety range, return loss value safety range, and gain flatness safety range.

[0033] It should be noted that the wafer electrical performance testing module, wafer electrical performance judgment module, wafer electrical signal difference analysis module, and chip testing module are all connected to the database.

[0034] Wafer Electrical Performance Testing Module: By testing the electrical parameters of the wafer arrays of each chip in each stage of the integrated circuit manufacturing process before back-end packaging, the module obtains the chip electrical parameters and then analyzes the wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging.

[0035] In the above embodiments, the specific analysis method for analyzing the wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is as follows: based on the obtained electrical parameters of each chip, wherein each chip electrical parameter includes DC parameters, radio frequency parameters, and storage parameters, the wafer DC compliance index of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is evaluated. Wafer RF compliance index And wafer storage conforms to the index This allows for the evaluation of the wafer electrical performance test values ​​of each chip at each stage of the integrated circuit manufacturing process, before back-end packaging. The specific calculation formula is as follows: ,in, This is represented by the number of each stage. , This is expressed as the number of steps. This is represented by the chip's serial number. , This is expressed as the number of chips. Represented by the logical symbol NOT. Represented as the logical symbol OR, This represents the wafer DC compliance exponent threshold for each stage in the integrated circuit manufacturing process before back-end packaging. This represents the wafer radio frequency compliance index threshold for each stage in the integrated circuit manufacturing process before back-end packaging. This represents the wafer storage compliance threshold for each stage in the integrated circuit manufacturing process before back-end packaging.

[0036] It should be noted that the DC compliance index, RF compliance index, and memory compliance index, as core dimensions for evaluating the electrical performance of chips before packaging in the later stages of integrated circuit manufacturing, together constitute a comprehensive and accurate performance evaluation system. These are obtained through monitoring and analysis using a semiconductor parameter analyzer, an RF network analyzer, and a memory tester, respectively. The DC compliance index focuses on the chip's fundamental electrical characteristics; its compliance directly determines whether the chip can operate stably under rated conditions. An abnormal DC compliance index indicates fundamental problems such as leakage current or excessive power consumption, directly leading to unqualified overall electrical performance test values ​​and rendering the chip meaningless for further evaluation. The RF compliance index addresses high-frequency signal processing capabilities, reflecting the chip's dynamic performance in wireless communication and signal transmission scenarios; its fluctuations will... The impact of electrical performance test values ​​on the judgment of chip high-frequency adaptability: When the RF compliance index is low, even if the DC parameters meet the standards, it indicates that the chip is difficult to meet the high-frequency application requirements of 5G, IoT, etc., which limits the application scenario adaptability assessment of electrical performance test values. The storage compliance index is for the core function of storage chips, and its level is directly related to the evaluation of data storage reliability in electrical performance test values. If the storage compliance index is insufficient, it indicates that the chip has problems such as data loss and short erase / write life, which will cause the electrical performance test value to drop sharply in the storage function dimension and fail to pass the quality screening before packaging. Therefore, it is necessary to analyze the DC compliance index, RF compliance index and storage compliance index of each chip in each stage of the integrated circuit manufacturing process before packaging.

[0037] In the above embodiments, the specific analysis method for the wafer DC compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is as follows: Based on the obtained DC parameters, which include the leakage current value and critical voltage value of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the leakage current value and critical voltage value of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process are compared with the safe range of leakage current value and safe range of critical voltage value of the wafer array of each stage before back-end packaging in the integrated circuit manufacturing process stored in the database. If the leakage current value of the wafer array of a certain chip in a certain stage before back-end packaging in the integrated circuit manufacturing process is within the safe range of leakage current value and the critical voltage value is within the safe range of critical voltage value, then the wafer DC compliance index of that chip in that stage before back-end packaging in the integrated circuit manufacturing process is recorded as 1, otherwise it is recorded as -1, thereby obtaining the wafer DC compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process. ,in, The values ​​include 1 and -1.

[0038] It should be noted that the leakage current value of the wafer array of each chip in each stage before packaging in the circuit assembly process directly affects the power consumption. The critical voltage value reflects the switching characteristics of the transistor. Excessive deviation will lead to abnormal chip speed. Therefore, the wafer leakage current value of each chip in each stage before packaging in the circuit assembly process is analyzed.

[0039] In the above embodiments, the wafer radio frequency compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is specifically analyzed as follows: Based on the obtained radio frequency parameters, including the frequency delay duration, setup duration, and hold duration of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the frequency delay duration compliance interval, setup duration compliance interval, and hold duration compliance interval of the wafer array in each stage before back-end packaging in the integrated circuit manufacturing process are extracted from the database, and the wafer radio frequency compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is analyzed. The specific calculation formula is as follows: , This refers to the first stage before back-end packaging in the integrated circuit manufacturing process. The first step of the process The first chip One radio frequency parameter, This refers to the first stage before back-end packaging in the integrated circuit manufacturing process. The first step of the process The first chip Each radio frequency parameter conforms to the range. .

[0040] It should be noted that the frequency delay, setup time, and hold time of the wafer arrays of each chip in each stage of the integrated circuit manufacturing process before back-end packaging reflect the wireless signal transmission and reception capabilities. Frequency delay reflects the lag in the transmission of radio frequency signals within the chip. If it exceeds the design threshold, it will lead to signal synchronization imbalance, reduce the response speed of the radio frequency link, and directly lower the radio frequency compliance index. Especially in high-frequency communication scenarios, excessive delay can cause signal distortion or data transmission errors. Setup time refers to the time it takes for the input signal to stabilize to meet the normal operating requirements of the circuit. Its stability determines the signal convergence capability of the radio frequency module when it starts up. If the setup time fluctuates too much or is too long, it indicates that there are process deviations in the chip's internal oscillation circuit and filter network, which will lead to instability in the initial stage of the RF signal and thus affect the RF compliance index's evaluation of the chip's dynamic performance. The hold time reflects the ability of the RF signal to maintain a stable state during transmission. If the hold time is insufficient, the signal is easily affected by noise interference or environmental factors and will attenuate, indicating that there are defects in the chip's anti-interference design, making it difficult for the RF compliance index to meet the design standard. Therefore, it is necessary to analyze the frequency delay time, setup time, and hold time of each chip in each stage of the integrated circuit manufacturing process before packaging.

[0041] In the above embodiments, the wafer storage compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is specifically analyzed as follows: Based on the obtained storage parameters, including the number of erase / write cycles and data retention time of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the number of erase / write cycles and data retention time of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process are compared with the erase / write cycle compliance intervals and data retention time compliance intervals of the wafer array of each stage before back-end packaging in the integrated circuit manufacturing process stored in the database. If the number of erase / write cycles of the wafer array of a certain chip in a certain stage before back-end packaging in the integrated circuit manufacturing process is within the erase / write cycle compliance interval and the data retention time is within the data retention time compliance interval, then the wafer storage compliance index of that chip in that stage before back-end packaging in the integrated circuit manufacturing process is recorded as 1; otherwise, it is recorded as -1, thereby obtaining the wafer storage compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process. ,in, The values ​​include 1 and -1.

[0042] It should be noted that the wafer erase / write cycles and data retention time of each chip in each stage of the integrated circuit manufacturing process before back-end packaging are core performance indicators of memory chips. They play a crucial role and have a direct impact on evaluating the wafer memory compliance index of chips in each stage before back-end packaging of the integrated circuit manufacturing process. The erase / write cycles directly reflect the durability of the memory cell, and the degree of matching between the test results and the design threshold is an important dimension for measuring the memory compliance index. If the actual erase / write cycles are significantly lower than the design standard, it indicates that the memory cell may have process problems such as oxide layer defects or insufficient charge trapping ability, which will directly lower the memory compliance index and indicate that the chip is difficult to meet the long-term use requirements. A stable and compliant write / erase cycle count provides a fundamental basis for the storage compliance index, proving that the physical structure and material performance of the storage cell meet the process requirements. Data retention time reflects the charge retention capability of the storage cell and is another core criterion for evaluating the storage compliance index. When the data retention time is lower than the design specifications, it means that the storage cell has a problem of excessively rapid charge leakage, such as insulation layer defects or poor tunnel oxide layer quality, which will lead to an increased risk of lost stored information and directly cause the storage compliance index to drop. Conversely, if the data retention time is stable within a reasonable range, it indicates that the insulation performance and charge retention capability of the storage cell meet the standards, which is an important guarantee for meeting the storage compliance index.

[0043] Wafer electrical performance judgment module: Based on the obtained wafer electrical performance test values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, it determines whether there are chips in abnormal stages. If not, it proceeds to the next step.

[0044] In the above embodiments, the specific analysis method for determining whether there is an abnormal chip is as follows: based on the obtained wafer electrical performance test values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, when the wafer electrical performance test value is 1, it indicates that the chip in that stage is in a normal state; when the wafer electrical performance test value is -1, it indicates that there is an abnormal chip, and a warning is issued.

[0045] Wafer Electrical Signal Difference Analysis Module: By contacting the test points on the wafer with the probe card, it captures the minute electrical signal difference parameters of each chip in each stage of the integrated circuit manufacturing process, and evaluates the minute electrical signal difference values ​​of each chip in each stage before packaging.

[0046] In the above embodiments, the specific analysis method for capturing the minute electrical signal difference parameters of each chip in each stage of the wafer array is as follows: according to the distribution of test points on the chip on the wafer, the probe positions are arranged and adjusted to correspond to the test points. A laser calibration system is used to perform three-dimensional positioning of the probe card. The contact force between the probe and the test point is monitored in real time by a pressure sensor to obtain the minute electrical signal difference parameters of each chip in each stage of the wafer array. The minute electrical signal difference parameters of each chip in each stage of the wafer array include: ion implantation deviation, focal length offset distance, return loss and gain flatness of each chip in each stage of the integrated circuit manufacturing process before back-end packaging.

[0047] In the above embodiments, the specific analysis method for evaluating the wafer micro-electrical signal differences of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is as follows: Based on the obtained ion implantation deviation, focal length offset distance, return loss value, and gain flatness of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the ion implantation deviation, focal length offset distance, return loss value, and gain flatness of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process are compared with the ion implantation deviation safety range and focal length of the wafer array in each stage before back-end packaging in the integrated circuit manufacturing process stored in the database. By comparing the safe ranges for offset distance, return loss, and gain flatness, if the ion implantation deviation of a chip in a certain stage before back-end packaging in the integrated circuit manufacturing process is within the safe ranges for ion implantation deviation, focal length offset, return loss, and gain flatness, then the wafer micro-electrical signal difference value of that chip in that stage before back-end packaging is recorded as 1; otherwise, it is recorded as -1. This allows us to obtain the wafer micro-electrical signal difference values ​​for each chip in each stage before back-end packaging in the integrated circuit manufacturing process. ,in, The values ​​include 1 and -1.

[0048] Chip testing module: Based on the obtained wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging and the wafer minute electrical signal difference values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging, defective chips are screened and classified.

[0049] In the above embodiments, the specific analysis method for screening each defective chip is as follows: based on the obtained wafer electrical performance test values ​​and wafer micro-electrical signal difference values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, when the wafer electrical performance test value or wafer micro-electrical signal difference value of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is 1, the defective chip prediction value is recorded as 1, indicating that chip screening is not required; when the wafer electrical performance test value or wafer micro-electrical signal difference value of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is -1, the defective chip prediction value is recorded as -1, indicating that chip screening is required.

[0050] In the above embodiments, the classification includes: if The chip in this stage is recorded as having a minor defect, the frequency of monitoring is increased, and a process warning is triggered.

[0051] like The chip in this stage was classified as having a moderate defect, and multiple tests and recalibrations were performed to repair it.

[0052] like The chip in this stage is marked as a critical defect type, and the critical defective chip is separately marked from the wafer batch, discarded to stop losses and prevent it from flowing into the packaging stage.

[0053] If multiple chips in the same stage before packaging in the integrated circuit manufacturing process have the same type of defect, it is judged as a batch defect, and the chip detection scope is expanded; if only a single chip has an isolated parameter abnormality, it is classified as an individual defect, and the real-time monitoring of this stage is strengthened, and the sampling frequency of key parameters is increased.

[0054] The above content is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described, or use similar methods to replace them, as long as they do not deviate from the concept of the invention or exceed the scope defined by the present invention, and all such modifications and additions should fall within the protection scope of the present invention.

Claims

1. A wafer array testing system for integrated circuit manufacturing processes, characterized in that, include: Wafer Electrical Performance Testing Module: By testing the electrical parameters of the wafer array of each chip in each stage of the integrated circuit manufacturing process before back-end packaging, the module obtains the chip electrical parameters and then analyzes the wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging. Wafer electrical performance judgment module: Based on the obtained wafer electrical performance test values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, determine whether there are chips in abnormal stages. If not, proceed to the next step. Wafer Electrical Signal Difference Analysis Module: By contacting the test points on the wafer with the probe card, it captures the minute electrical signal difference parameters of each chip in each stage of the process, and evaluates the minute electrical signal difference values ​​of each chip in each stage before packaging in the integrated circuit manufacturing process. Chip testing module: Based on the obtained wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging and the wafer minute electrical signal difference values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging, defective chips are screened and classified.

2. The wafer array testing system for integrated circuit manufacturing process according to claim 1, characterized in that, The analysis method for the wafer electrical performance test values ​​of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is as follows: Based on the obtained electrical parameters of each chip, including DC parameters, RF parameters, and memory parameters, the wafer DC compliance index of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is evaluated. Wafer RF compliance index And wafer storage conforms to the index This allows for the evaluation of the wafer electrical performance test values ​​of each chip at each stage of the integrated circuit manufacturing process, before back-end packaging. The specific calculation formula is as follows: ,in, This is represented by the number of each stage. , This is expressed as the number of steps. This is represented by the chip's serial number. , This is expressed as the number of chips. Represented by the logical symbol NOT. Represented as the logical symbol OR, This represents the wafer DC compliance exponent threshold for each stage in the integrated circuit manufacturing process before back-end packaging. This represents the wafer radio frequency compliance index threshold for each stage in the integrated circuit manufacturing process before back-end packaging. This represents the wafer storage compliance threshold for each stage in the integrated circuit manufacturing process before back-end packaging.

3. The wafer array testing system in integrated circuit manufacturing process according to claim 2, characterized in that, The specific analysis method for the wafer DC compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is as follows: Based on the obtained DC parameters, including the leakage current and critical voltage values ​​of the wafer arrays of each chip in each stage of the integrated circuit manufacturing process before back-end packaging, the leakage current and critical voltage values ​​of the wafer arrays of each chip in each stage of the integrated circuit manufacturing process before back-end packaging are compared with the safe ranges of leakage current and critical voltage values ​​of the wafer arrays in each stage of the integrated circuit manufacturing process before back-end packaging stored in the database. If the leakage current value of a certain chip in a certain stage of the integrated circuit manufacturing process before back-end packaging is within the safe range of leakage current and critical voltage values, then the wafer DC compliance index of that chip in that stage of the integrated circuit manufacturing process before back-end packaging is recorded as 1; otherwise, it is recorded as -1. Thus, the wafer DC compliance index of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is obtained. ,in, The values ​​include 1 and -1.

4. The wafer array testing system in integrated circuit manufacturing process according to claim 2, characterized in that, The specific analysis method for the wafer radio frequency compliance index of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is as follows: Based on the obtained radio frequency (RF) parameters, which include the frequency delay, setup time, and hold time of the wafer arrays of each chip in each stage of the integrated circuit manufacturing process before back-end packaging, and by extracting the frequency delay, setup time, and hold time compliance intervals of the wafer arrays in each stage of the integrated circuit manufacturing process before back-end packaging from the database, the wafer RF compliance index of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is analyzed. The specific calculation formula is as follows: , This refers to the first stage before back-end packaging in the integrated circuit manufacturing process. The first step of the process The first chip One radio frequency parameter, This refers to the first stage before back-end packaging in the integrated circuit manufacturing process. The first step of the process The first chip Each radio frequency parameter conforms to the range. .

5. The wafer array testing system for integrated circuit manufacturing process according to claim 2, characterized in that, The wafer storage compliance index of each chip in each stage of the integrated circuit manufacturing process before back-end packaging is analyzed using the following method: Based on the obtained storage parameters, including the erase / write counts and data retention duration of the wafer arrays of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, the erase / write counts and data retention durations of the wafer arrays of each chip in each stage before back-end packaging in the integrated circuit manufacturing process are compared with the erase / write count and data retention duration compliance intervals of the wafer arrays in each stage before back-end packaging in the integrated circuit manufacturing process stored in the database. If the erase / write counts of a certain chip in a certain stage before back-end packaging in the integrated circuit manufacturing process are within the erase / write count compliance interval and the data retention duration is within the data retention duration compliance interval, then the wafer storage compliance index of that chip in that stage before back-end packaging in the integrated circuit manufacturing process is recorded as 1; otherwise, it is recorded as -1. Thus, the wafer storage compliance index of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is obtained. ,in, The values ​​include 1 and -1.

6. The wafer array testing system in integrated circuit manufacturing process according to claim 2, characterized in that, The specific analysis method for determining whether an abnormal component exists in the chip is as follows: Based on the obtained wafer electrical performance test values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, when the wafer electrical performance test value is 1, it indicates that the chip in that stage is in a normal state. When the wafer electrical performance test value is -1, it indicates that there is an abnormal chip in that stage, and a warning is issued.

7. The wafer array testing system for integrated circuit manufacturing process according to claim 6, characterized in that, The specific analysis method for capturing the minute electrical signal differences in the wafer array of each chip in each stage is as follows: Based on the distribution of test points on the wafer, the probe positions are arranged and adjusted to correspond to the test points. A laser calibration system is used to perform three-dimensional positioning of the probe card. The contact force between the probe and the test point is monitored in real time by a pressure sensor to obtain the minute electrical signal difference parameters of the wafer array of each chip in each stage. Among them, the minute electrical signal difference parameters of the wafer array of each chip in each stage include: ion implantation deviation, focal length offset distance, return loss and gain flatness of the wafer array of each chip in each stage before back-end packaging in the integrated circuit manufacturing process.

8. The wafer array testing system in integrated circuit manufacturing process according to claim 7, characterized in that, The specific analysis method for evaluating the minute electrical signal differences between each chip in each stage of the integrated circuit manufacturing process before back-end packaging is as follows: Based on the obtained ion implantation deviation, focal length offset, return loss value, and gain flatness of the wafer arrays of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, these parameters are compared with the safe intervals for ion implantation deviation, focal length offset, return loss value, and gain flatness of the wafer arrays in each stage before back-end packaging in the integrated circuit manufacturing process stored in the database. If the ion implantation deviation of a certain chip in a certain stage before back-end packaging is within the safe intervals for ion implantation deviation, focal length offset, return loss value, and gain flatness, then the wafer micro-electrical signal difference value of that chip in that stage before back-end packaging is recorded as 1; otherwise, it is recorded as -1. This yields the wafer micro-electrical signal difference values ​​for each chip in each stage before back-end packaging in the integrated circuit manufacturing process. ,in, The values ​​include 1 and -1.

9. The wafer array testing system for integrated circuit manufacturing process according to claim 8, characterized in that, The specific analysis method for screening each defective chip is as follows: Based on the obtained wafer electrical performance test values ​​and wafer micro-electrical signal difference values ​​of each chip in each stage before back-end packaging in the integrated circuit manufacturing process, when the wafer electrical performance test value or wafer micro-electrical signal difference value of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is 1, the defective chip prediction value is recorded as 1, indicating that chip screening is not required. When the wafer electrical performance test value or wafer micro-electrical signal difference value of each chip in each stage before back-end packaging in the integrated circuit manufacturing process is -1, the defective chip prediction value is recorded as -1, indicating that chip screening is required.

10. The wafer array testing system in integrated circuit manufacturing process according to claim 9, characterized in that, The classification includes: like The chip in this stage is recorded as having a minor defect, the frequency of monitoring is increased, and a process warning is triggered. like The chip in this stage is classified as having a moderate defect, and multiple tests and recalibration repairs are performed. like The chip in this stage is marked as a critical defect type. The critically defective chip is separately marked from the wafer batch and discarded to stop losses and prevent it from flowing into the packaging stage. If multiple chips in the same stage before packaging in the integrated circuit manufacturing process have the same type of defect, it is judged as a batch defect, and the chip detection scope is expanded; if only a single chip has an isolated parameter abnormality, it is classified as an individual defect, and the real-time monitoring of this stage is strengthened, and the sampling frequency of key parameters is increased.

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