Process corner self-adjusting circuit and method for controlling overshoot voltage existence duration

Abstract

The invention belongs to the field of radio frequency circuits, and particularly relates to a process angle self-adjusting circuit and method for controlling overshoot voltage existence duration, and the circuit comprises a judgment voltage generation circuit which is used for generating judgment voltage and outputting the judgment voltage to the positive input end of an upper limit comparator and the positive input end of a lower limit comparator; the window voltage generation circuit is used for generating a window voltage comprising an upper limit window voltage and a lower limit window voltage, outputting the upper limit window voltage to the negative input end of the upper limit comparator, and outputting the lower limit window voltage to the negative input end of the lower limit comparator; the upper limit comparator is used for comparing the judgment voltage with the upper limit window voltage and outputting a high level or a low level; and the lower limit comparator is used for comparing the judgment voltage with the lower limit window voltage and outputting a high level or a low level. By controlling the access number of the time control devices of the overshoot voltage generation module, the process corner control of the overshoot voltage on the existence time performance is successfully realized.

Description

Technical Field

[0001] This application belongs to the field of radio frequency circuits, and particularly relates to a process angle self-adjustment circuit and method for controlling the duration of overshoot voltage. Background Technology

[0002] In radio frequency circuits, such as power amplifiers, power fluctuations are difficult to adjust. A common solution is to introduce an overshoot voltage that persists for a certain duration into the power supply module (LDO), which can solve this problem with minimal cost. This relies on an overshoot voltage generation module, but traditional overshoot voltage generation modules typically have poor process corner resistance, making it difficult to achieve similar overshoot voltage duration across the entire process corner.

[0003] Therefore, how to make the overshoot voltage exist for a similar duration at different process corners has become an urgent technical problem to be solved. Summary of the Invention

[0004] The first aspect of this application provides a process angle self-adjusting circuit for controlling the duration of overshoot voltage, which solves the problem that traditional overshoot voltage generation modules usually have poor process angle resistance and it is difficult to achieve similar performance across the entire process angle overshoot voltage duration.

[0005] The first aspect of this application provides a method for controlling the duration of overshoot voltage.

[0006] A process angle self-adjustment circuit for controlling the duration of overshoot voltage according to a first aspect embodiment of this application includes: a decision voltage generation circuit, a window voltage generation circuit, an upper limit comparator, a lower limit comparator, and two MOS transistor switches; The decision voltage generation circuit is used to generate a decision voltage and output it to the positive input terminals of the upper limit comparator and the lower limit comparator; The window voltage generation circuit is used to generate a window voltage including an upper window voltage and a lower window voltage, output the upper window voltage to the negative input terminal of the upper window comparator, and output the lower window voltage to the negative input terminal of the lower window comparator. The upper limit comparator compares the decision voltage and the upper limit window voltage, and outputs a high level or a low level to control the closing or opening of one of the MOSFET switches; The lower limit comparator compares the decision voltage and the lower limit window voltage, and outputs a high level or a low level to control the closing or opening of another MOSFET switch.

[0007] Furthermore, when the decision voltage is lower than the lower limit window voltage, both the upper limit comparator and the lower limit comparator output a high level, controlling both MOSFET switches to close completely.

[0008] Furthermore, when the decision voltage is within the voltage window, the upper limit comparator outputs a high level, the lower limit comparator outputs a low level, and one MOSFET switch is turned off.

[0009] Furthermore, when the decision voltage is higher than the upper limit window voltage, both the upper limit comparator and the lower limit comparator output a low level, and all MOSFET switches are turned off.

[0010] A method for controlling the duration of overshoot voltage according to a second aspect of this application includes: Generate a decision voltage; Generate a window voltage that includes an upper window voltage and a lower window voltage; The decision voltage is compared with the window voltage, and two control levels for the MOSFET switches are generated based on the comparison result to control the state of the two MOSFET switches, including both closed, both open, or one closed and one open. The connection of the delay control device in the overshoot voltage generation circuit is controlled according to the state of the two MOSFET switches.

[0011] Further, the comparison of the decision voltage with the window voltage, and the generation of two control levels for the closing or opening of the MOSFET switches based on the comparison result, for controlling the state of the two MOSFET switches, includes: When the decision voltage is lower than the lower limit window voltage, two high levels are output to control both MOSFET switches to be closed. When the decision voltage is within the voltage window, output a high level and a low level to disconnect a MOSFET switch. When the decision voltage is higher than the upper limit window voltage, two low levels are output, and all MOSFET switches are turned off.

[0012] Compared with the prior art, the advantages of this application are as follows: This application introduces logic control into the existing overshoot voltage generation module, and by controlling the number of time control devices (such as resistors and capacitors) connected to the overshoot voltage generation module, it successfully achieves process angle control of the overshoot voltage in terms of its existence time performance. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a process angle self-adjustment circuit for controlling the duration of overshoot voltage provided in an embodiment of this application; Figure 2 This is a schematic diagram of the overshoot voltage waveform of a conventional overshoot voltage generation circuit provided in the embodiments of this application; Figure 3 This is a schematic diagram of the overshoot voltage waveform after the application of the process angle self-adjustment circuit for controlling the duration of overshoot voltage provided in the embodiments of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0015] Given that power amplifiers and other circuits in the prior art suffer from power fluctuations that are difficult to adjust, solving this problem in analog LDOs (low dropout linear regulators) used for power supply is easier than solving it in power amplifiers. However, traditional overshoot voltage generation modules typically have poor process corner resistance, making it difficult to achieve similar delay performance across the entire process corner. This application provides a process corner self-adjustment circuit for controlling the duration of overshoot voltage. Through a decision voltage generation circuit, a window voltage generation circuit, a comparator, and a MOSFET switch connected in sequence, it achieves automatic adjustment of the process corner duration of overshoot voltage. Using the overshoot duration of the TT (Typical-Typical) process corner as a reference, the duration of the overshoot voltage is adjusted to be approximately the same as the duration of the TT process corner. TT process corner refers to the typical values ​​of process parameters for both NMOS and PMOS transistors during chip manufacturing; FS process corner indicates that NMOS transistor parameters are at fast values ​​while PMOS transistor parameters are at slow values; SF process corner indicates that NMOS transistor parameters are at slow values ​​while PMOS transistor parameters are at fast values; FF process corner indicates that both NMOS and PMOS transistors are at their fastest values. The parameters of an NMOS or PMOS transistor refer to various physical and electrical characteristics that affect transistor performance, including mobility, threshold voltage, leakage current, transconductance, output impedance, saturation current, and parasitic capacitance.

[0016] Please refer to Figure 1 This application provides a process angle self-adjusting circuit for controlling the duration of overshoot voltage. It includes a decision voltage generation circuit, a window voltage generation circuit, an upper limit comparator, a lower limit comparator, and two MOSFET switches.

[0017] The main function of the decision voltage generation circuit is to generate a stable reference voltage. It can be generated by dividing a stable power supply through a resistor divider to generate a stable reference voltage as the decision voltage, or by using other existing circuits that can generate a stable reference voltage. In this embodiment, no limitation is made.

[0018] The window voltage generation circuit defines a voltage window by generating two stable reference voltages, including an upper limit window voltage and a lower limit window voltage. It can be generated by a voltage divider with two resistors, or by other existing circuits that can generate two stable reference voltages. In this embodiment, no limitation is made.

[0019] By adjusting the decision voltage, the decision voltage is made to be within the voltage window, higher than the upper limit window voltage, or lower than the lower limit window voltage.

[0020] A comparator compares two input voltages and outputs a high or low level, which is then connected to the control terminal of a MOSFET switch to control the MOSFET switch's on / off state.

[0021] The output of the decision voltage generation circuit is connected to the positive input of the upper limit comparator and the lower limit comparator. The window voltage generation circuit has two outputs, which output two voltages of different magnitudes respectively. The output of the upper limit window voltage is connected to the negative input of the upper limit comparator, and the output of the lower limit window voltage is connected to the negative input of the lower limit comparator.

[0022] The upper limit comparator compares the decision voltage and the upper limit window voltage, and outputs a high level or a low level to control the closing or opening of one of the MOSFET switches. In this embodiment, the upper limit comparator compares the decision voltage and the upper limit window voltage. When the decision voltage is less than the upper limit window voltage, it outputs a high level, which can control the closing of the MOSFET switch. When the decision voltage is higher than the upper limit window voltage, the upper limit comparator outputs a low level, which can control the opening of the MOSFET switch.

[0023] The lower limit comparator compares the decision voltage with the lower limit window voltage and outputs a high or low level to control the opening or closing of another MOSFET switch. When the decision voltage is less than the lower limit window voltage, the lower limit comparator outputs a high level, which can control the MOSFET switch to close; when the decision voltage is higher than the lower limit window voltage, the lower limit comparator outputs a low level, which can control the MOSFET switch to open.

[0024] Since the overshoot duration is longest in the SS process corner, the control process includes: when the decision voltage is lower than the lower limit window voltage, the upper limit comparator and the lower limit comparator output a high level, all MOSFET switches are closed, and the number of delay control devices connected is reduced by two sets. The delay control device refers to the time control device that controls the overshoot voltage generation module, such as a resistor, capacitor, or a combination of resistor and capacitor. The delay control device is connected or disconnected by the MOSFET switch. When the MOSFET switch is closed, the delay control device is not connected to the circuit. When the MOSFET switch is open, the delay control device is connected to the circuit. The overshoot duration of the SS process corner (slow-slow process corner) is shortened to the duration of the TT process corner. When the decision voltage is within the voltage window, the upper limit comparator outputs a high level, the lower limit comparator outputs a low level, one MOSFET switch is disconnected, and only one set of delay control devices is added to the number of connected devices. The overshoot duration of the TT, FS (Fast-Slow), and SF (Slow-Fast) process corners is maintained at the standard of the TT process corner. When the decision voltage is higher than the upper limit window voltage, both the upper limit comparator and the lower limit comparator output a low level, all MOSFET switches are turned off, the number of two sets of delay control devices is increased, and the delay time of the FF process corner is extended to the duration standard of the TT process corner.

[0025] On the other hand, this application provides a method for controlling the duration of overshoot voltage, comprising: A decision voltage is generated; this is achieved through a circuit that can generate an output voltage, and the output voltage can be adjusted.

[0026] Generate a window voltage that includes an upper limit window voltage and a lower limit window voltage; the magnitudes of the upper limit window voltage and the lower limit window voltage need to be combined with the decision voltage so that when the decision voltage is adjusted, it is between the window voltages, or greater than the upper limit window voltage or less than the lower limit window voltage.

[0027] The decision voltage is compared with the window voltage, and two control levels for the MOSFET switches are generated based on the comparison result. These levels are used to control the state of the two MOSFET switches, which can be either all closed, all open, or one closed and one open. The connection of the delay control device in the overshoot voltage generation circuit is controlled according to the state of the two MOSFET switches.

[0028] In one embodiment, a decision voltage is compared with a window voltage, and two control levels for the MOSFET switches are generated based on the comparison result to control the state of the two MOSFET switches, including: When the judgment voltage is lower than the lower limit window voltage, two high levels are output, controlling both MOSFET switches to close completely. The number of delayed control devices connected is reduced by two sets. Delay control devices refer to the time control devices that control the overshoot voltage generation module, such as resistors, capacitors, or combinations of resistors and capacitors. The delayed control devices are connected or disconnected by the MOSFET switches. When the MOSFET switches are closed, the delayed control devices are not connected to the circuit. When the MOSFET switches are open, the delayed control devices are connected to the circuit. The overshoot existence time of the SS process corner (slow-slow process corner) is shortened to the existence time under the TT process corner. When the decision voltage is within the voltage window, output a high level and a low level, disconnect a MOSFET switch, and only increase the number of connected delay control devices. The overshoot duration of the TT, FS (Fast-Slow), and SF (Slow-Fast) process corners is maintained at the standard of the TT process corner. When the decision voltage is higher than the upper limit window voltage, two low levels are output, all MOSFET switches are turned off, the number of two sets of delay control devices is increased, and the delay time of the FF process corner is extended to the duration standard of the TT process corner.

[0029] Figure 2 This is a waveform diagram of a traditional overshoot voltage generation module. The waveform shown is the output voltage VOUT of the overshoot voltage generation module.

[0030] Figure 3 This is a schematic diagram of the output voltage waveform after applying a process angle self-adjustment circuit to control the duration of overshoot voltage to the overshoot voltage generation module.

[0031] Please refer to Figure 2 and Figure 3 Tests were conducted at temperatures of 25℃, -40℃, and 95℃. Without process angle adjustment, the overshoot duration at process angles SS and FF differed significantly from that at process angle TT, while the overshoot duration at process angles FS and SF was similar to that at process angle TT. After applying the process angle self-adjustment circuit, as... Figure 3 As shown, the overshoot duration of all five process corners has been adjusted to be approximately equal.

[0032] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A process angle self-adjusting circuit for controlling the duration of overshoot voltage, characterized in that, include: The circuit consists of a decision voltage generation circuit, a window voltage generation circuit, an upper limit comparator, a lower limit comparator, and two MOSFET switches. The decision voltage generation circuit is used to generate a decision voltage and output it to the positive input terminals of the upper limit comparator and the lower limit comparator; The window voltage generation circuit is used to generate a window voltage including an upper window voltage and a lower window voltage, output the upper window voltage to the negative input terminal of the upper window comparator, and output the lower window voltage to the negative input terminal of the lower window comparator. The upper limit comparator compares the decision voltage and the upper limit window voltage, and outputs a high level or a low level to control the closing or opening of one of the MOSFET switches; The lower limit comparator compares the decision voltage and the lower limit window voltage, and outputs a high level or a low level to control the closing or opening of another MOSFET switch.

2. The process angle self-adjustment circuit for controlling the duration of overshoot voltage according to claim 1, characterized in that, When the decision voltage is lower than the lower limit window voltage, both the upper limit comparator and the lower limit comparator output a high level, controlling both MOSFET switches to close completely.

3. The process angle self-adjustment circuit for controlling the duration of overshoot voltage according to claim 1, characterized in that, When the decision voltage is within the voltage window, the upper limit comparator outputs a high level and the lower limit comparator outputs a low level, thus disconnecting one MOSFET switch.

4. The process angle self-adjustment circuit for controlling the duration of overshoot voltage according to claim 1, characterized in that, When the decision voltage is higher than the upper limit window voltage, both the upper limit comparator and the lower limit comparator output a low level, and all MOSFET switches are turned off.

5. A method for controlling the duration of overshoot voltage, characterized in that, include: Generate a decision voltage; Generate a window voltage that includes an upper window voltage and a lower window voltage; The decision voltage is compared with the window voltage, and two control levels for the MOSFET switches are generated based on the comparison result to control the state of the two MOSFET switches, including both closed, both open, or one closed and one open. The connection of the delay control device in the overshoot voltage generation circuit is controlled according to the state of the two MOSFET switches.

6. The method for controlling the duration of overshoot voltage according to claim 5, characterized in that, The comparison of the decision voltage with the window voltage, and the generation of two control levels for the closing or opening of the MOSFET switches based on the comparison result, are used to control the state of the two MOSFET switches, including: When the decision voltage is lower than the lower limit window voltage, two high levels are output to control both MOSFET switches to be closed. When the decision voltage is within the voltage window, output a high level and a low level to disconnect a MOSFET switch. When the decision voltage is higher than the upper limit window voltage, two low levels are output, and all MOSFET switches are turned off.

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