SRAM (Static Random Access Memory) storage unit, static random access memory and preparation method thereof

Abstract

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors and relates to a memory technology, specifically to an SRAM memory cell, a static random access memory, and a method for fabricating the same. Background Technology

[0002] Static Random-Access Memory (SRAM) has advantages such as high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics products (smart cards, digital cameras, multimedia players) and other fields.

[0003] The basic structure of static random access memory (SRAM) is fixed, such as... Figure 1 As shown, taking 6T as an example, the SRAM cell includes transfer gate transistors PG1 and PG2, pull-up transistors PU1 and PU2, and pull-down transistors PD1 and PD2. Pull-up transistors PU1 and PU2 are P-type metal-oxide-semiconductor transistors (PMOS), pull-down transistors PD1 and PD2 are N-type metal-oxide-semiconductor transistors (NMOS), and transfer gate transistors PG1 and PG2 are N-type metal-oxide-semiconductor transistors (NMOS). The gates of transfer gate transistors PG1 and PG2 are connected to and controlled by the word line WL that determines whether to select the SRAM cell. A latch formed by pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2 stores bits, where the complementary values ​​of the bits are stored in the left storage node SNL and the right storage node SNR. Transfer gate transistors PG1 and PG2 are connected to bit line BL and anti-phase line BLB, respectively. Stored bits can be written to or read from the SRAM cell via bit line BL and anti-phase line BLB.

[0004] The sources of pull-up transistors PU1 and PU2 are connected to the power supply voltage / node Vdd; the sources of pull-down transistors PD1 and PD2 are connected to ground Vss. The gates of pull-up transistors PU1 and PD1 are connected to the drains of pull-up transistors PU2 and PD2, with the connection node being the right memory node SNR. The gates of pull-up transistors PU2 and PD2 are connected to the drains of pull-up transistors PU1 and PD1, with the connection node being the left memory node SNL. The source region of the transfer gate transistor PG1 is connected to the bit line BL at the bit line node, and the drain region of the transfer gate transistor PG1 is connected to the left memory node SNL. The source region of the transfer gate transistor PG2 is connected to the anti-phase line BLB (complementary bit line) at the anti-phase line node, and the drain region of the transfer gate transistor PG2 is connected to the right memory node SNR.

[0005] The basic structure and principle of the above SRAM cell have been determined, but because 6 MOS tubes (transistors) constitute a highly concentrated storage unit and are connected to each other, different layout designs can bring completely different performance. As shown in Figure 2 The channels of the 6 MOS tubes are arranged in 4 columns in the vertical direction, the transmission gate transistor PG1 and the pull-down transistor PD1 share the source / drain and are arranged in the first column, the channel of the pull-up transistor PU1 is arranged in the vertical direction and constitutes the second column alone; the channel of the pull-up transistor PU2 is arranged in the vertical direction and constitutes the third column alone; the transmission gate transistor PG2 and the pull-down transistor PD2 share the source / drain and are arranged in the fourth column. This version is easy to manufacture, but as the semiconductor process improves and the physical size of the SRAM cell shrinks, this version exposes some defects, such as space waste, all channels arranged in one direction, the need to improve channel carrier mobility through stress silicon technology, poor heat dissipation, low device density leading to limited storage capacity, etc.

[0006] There have been many studies on the layout design of SRAM in the prior art. Chinese patent application CN118714839A discloses an SRAM layout, which arranges the active regions of the transmission gate transistor PG1, the pull-down transistor PD1, the pull-down transistor PD2, and the transmission gate transistor PG2 on a straight line to share the source / drain, and arranges the pull-up transistor PU1 and the pull-up transistor PU2 on another straight line to share the source / drain, thereby saving area. However, all the active regions are in the same direction, and complex stress silicon technology is still needed to improve the channel carrier mobility.

[0007] Chinese patent application CN105788628A discloses an SRAM layout, which shares the source / drain of the pull-up transistor PU1 and the pull-up transistor PU2, shares the source / drain of the pull-down transistor PD1 and the pull-down transistor PD2, and separately arranges the transmission gate transistors PG1 and PG2, thereby further saving area and improving the storage capacity per unit area. However, the active regions are still in one direction, and complex stress silicon technology is still needed to improve the channel carrier mobility, and the device heat dissipation problem is not considered.

[0008] Chinese patent application CN101345214A discloses an SRAM layout design, which arranges the NMOS devices in the SRAM cell in a first direction (110 crystal orientation) and the PMOS devices in a second direction (100 crystal orientation), and the included angle between the first direction and the second direction is 45 degrees. The MOS tube connection is in the common way in the prior art. This technology improves the channel carrier mobility by arranging different crystal orientations respectively, and can save stress silicon technology. However, this technology does not consider heat dissipation, and the layout design is not compact, resulting in low layout density.

[0009] In summary, the prior art SRAM layout design is improved in some aspects, and there is still much room for improvement in version design, therefore, it is necessary to redesign the SRAM layout to provide a layout with better comprehensive performance. SUMMARY

[0010] One of the purposes of the present application is to provide an SRAM memory cell, by setting the active region of NMOS at (100) crystal orientation or the same family of (010) crystal orientation, (001) crystal orientation, and setting the active region of PMOS at (110) crystal orientation, by setting different crystal orientations respectively to improve the carrier mobility of the channel region, and the channels of NMOS and PMOS are set staggered in the thickness direction; solve the problem of mutual restriction of SRAM storage density and heat dissipation and low carrier mobility in the prior art.

[0011] Another purpose of the present application is to provide a preparation method of an SRAM memory cell, to realize the manufacture of the above-mentioned special structure NMOS and PMOS, and also to ensure a lower contact resistance, thereby improving the performance of the device.

[0012] In order to solve the above technical problems, the technical scheme adopted by the present application is as follows: On the one hand, the present application improves an SRAM memory cell, the SRAM memory cell at least includes 6 transistors, the 6 transistors are two transfer gate transistors, two pull-up transistors and two pull-down transistors respectively, the gate of the pull-up transistor and the source or drain of the transfer gate transistor are connected to form a storage node; The channel direction of the two transfer gate transistors is set to a first direction, the channel direction of the two pull-up transistors is set to a second direction, and the channel direction of the two pull-down transistors is set to a third direction, the third direction and the first direction are the same family of crystal orientation, and the two pull-up transistors are set to sink.

[0013] Further, the included angle between the first direction and the second direction ranges from 30 to 60 degrees.

[0014] Further, the first direction is (100) crystal orientation, the second direction is (110) crystal orientation, and the third direction is (010) crystal orientation or (001) crystal orientation.

[0015] Further, the two pull-down transistors share a source.

[0016] Further, the two pull-up transistors share a drain.

[0017] Further, the gate of the pull-up transistor is directly connected to the source or drain of the corresponding transfer gate transistor through metal silicide technology.

[0018] Further, the two transfer gate transistors share the same gate line.

[0019] Further, the gate width of the pull-up transistor and the pull-down transistor is the same, and the gate width of the transfer gate transistor is greater than the gate width of the pull-up transistor.

[0020] Further, the active region width of the pull-down transistor, the active region width of the transfer gate transistor, and the active region width of the pull-up transistor decrease in turn.

[0021] Further, the two pull-up transistors are arranged between the two transfer gate transistors and the two pull-down transistors.

[0022] Further, the sinking amount is not less than the channel depth of the transfer gate transistor or the pull-down transistor.

[0023] In another aspect, the application provides a static random access memory, comprising a semiconductor substrate and a plurality of SRAM memory cells formed on the semiconductor substrate, wherein each of the SRAM memory cells comprises at least six transistors, i.e., two transfer gate transistors, two pull-up transistors, and two pull-down transistors, and the gate of the pull-up transistor and the source or the drain of the transfer gate transistor are connected to form a storage node. The channel direction of the two transfer gate transistors is set to (100) crystal orientation, the channel direction of the two pull-up transistors is set to (110) crystal orientation, the channel direction of the two pull-down transistors is set to (010) crystal orientation or (001) crystal orientation, and the two pull-up transistors are arranged in a sinking manner.

[0024] In another aspect, the application provides a preparation method of a static random access memory, comprising the following steps: providing a semiconductor substrate; isolating the active region of each transistor by an isolation structure; sinking etching the region where the two pull-up transistors are arranged by an etching process to form a sinking groove; injecting ions of corresponding types into the active region of each transistor by an ion injection process to form the well region of NMOS and PMOS respectively; preparing a bare gate of each transistor, and performing a step etching process on the bare gate of the pull-up transistor so that the height of the bare gate at the storage node is the same as that of the active region of the transfer gate transistor; performing sidewall fabrication on the bare gate to obtain a gate electrode; preparing a source electrode and a drain electrode; metallically silicifying the active region at the storage node and the top surface of the gate electrode to obtain a metallic silicide layer; preparing a metal interconnection layer, and connecting the six transistors to form an SRAM memory cell.

[0025] Further, the isolation structure adopts a vertical sidewall isolation structure.

[0026] Further, when forming the sunken groove, the active region of the two pull-up transistors and the isolation structure around the same are sunken together.

[0027] Further, the bare gate of each transistor is prepared, and the bare gate of the pull-up transistor is stepped by an etching process, so that the height of the bare gate at the storage node is the same as that of the active region of the transfer gate transistor, including the following steps: Coating photoresist, using exposure and development technology to obtain a photoresist pattern in the shape of a gate electrode; Etching the gate material outside the photoresist coverage; Coating photoresist again, using exposure and development technology to obtain a photoresist pattern exposing the storage node area; Etching the gate material in the storage node area so that the height of the gate material layer at the storage node is the same as that of the transfer gate transistor.

[0028] Further, the active region at the storage node and the top surface of the gate are metal silicided to obtain a metal silicide layer, including the following steps: Pre-cleaning, etching part of the silicon layer at the top of the active region and the gate in the storage node area; Depositing a nickel-platinum alloy layer on the surface of the pre-cleaned silicon layer; Depositing a cap layer on the nickel-platinum alloy layer; Performing a first rapid thermal annealing to form a high-resistance metal silicide; Performing a second rapid thermal annealing to form a low-resistance metal silicide layer.

[0029] Further, during the preparation of the metal interconnection layer, the left storage node SNL is connected to the source of the second pull-up transistor and the drain of the second pull-down transistor through a metal line, and the right storage node SNR is connected to the source of the first pull-up transistor and the drain of the first pull-down transistor through a metal line.

[0030] Compared with the prior art, the present application has the following advantages: The application creatively sets the NMOS and PMOS in the direction of the best carrier migration rate (for example, sets the active region of the NMOS in the (100) crystal direction or the (010) crystal direction of the same family, and sets the active region of the PMOS in the (110) crystal direction), so that each can reach the best migration rate, and excellent device electrical performance can be obtained without using stress silicon technology; on the basis of the above, the application sets the pull-up transistor of the PMOS to be sunken, so that the channel region of the PMOS is set to be staggered in height with the channel region of the NMOS; the unexpected effect is that excellent heat dissipation capacity is obtained. In addition, since there are four NMOS and two PMOS, when the common drain of the two PMOS is set in the middle of the four NMOS, the minimum distance between the active regions can be increased by setting the NMOS and PMOS in different directions through the geometric effect, in other words, the minimum distance between the four NMOS can be further reduced, so as to further improve the transistor setting density, and a high-density static random access memory is designed; and on the basis of the above, the application sets the channels to be staggered, so that the main heat points are dispersed in space, excellent heat dissipation capacity is obtained, the heat dissipation problem of the high-density memory device is solved, the influence of device heating on electrical performance is avoided, and the distance between the transistors can be further shortened, so that more SRAM memory units can be set in a unit area to obtain a larger-capacity memory.

[0031] The application sets the channel direction of the pass-gate transistor in a first direction with the best carrier migration rate, and sets the channel direction of the pull-down transistor in a third direction which is a crystal face of the same family as the first direction, and the unexpected effect is that the application ensures the carrier migration rate of the pull-down transistor, and also sets the pull-down transistor and the pass-gate transistor in different directions, can reduce the area occupied by the SRAM memory unit, and can also set two pull-down transistors to share a source or a drain, so as to save the active region area, further reduce the area occupied by the SRAM memory unit, and reduce the number of contact holes.

[0032] The application saves the area by setting two pull-up transistors to share a drain, reduces the number of contact holes, reduces the cost, and improves the storage density.

[0033] The application reduces the use of the word line WL by setting two pass-gate transistors to share a gate, since the word line WL needs to be powered on in the reading and writing process, and therefore reducing the use of the word line WL can reduce the reading and writing power consumption.

[0034] In order to make the SRAM storage unit with the special structure, the application creatively isolates the active region through the isolation structure, then performs the etching process on the region where the pull-up transistor is located, and then forms the P well and the N well through the ion implantation process; then the bare gate is formed through the etching process, and the bare gate is stepped in the process of forming the bare gate through twice etching, so that the height of the bare gate at the storage node is the same as that of the active region of the transfer gate transistor; thus the basic conditions are provided for connecting the gate of the pull-up transistor and the active region of the transfer gate transistor through the metal silicide, then the sidewall is made and the metal silicide treatment is performed on the storage node region, then the source and the drain are made, finally the metal interconnection layer is prepared, and the preparation of the SRAM device is completed; the unexpected effect is that the preparation of the SRAM device with the special structure is completed through the ingenious combination of the simple and mature process, and in the preparation process, the connection resistance between the gate of the pull-up transistor and the active region of the transfer gate transistor is reduced through the metal silicide technology, so that the storage node can efficiently and stably store and read and write data, and a relatively low heating resistance can also be ensured, and unexpected technical effects are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 It is a SRAM storage unit circuit schematic diagram in the prior art.

[0036] Figure 2 It is a layout of the SRAM storage unit in the prior art.

[0037] Figure 3 It is a cubic crystal system crystal face schematic diagram in the prior art.

[0038] Figure 4 It is a SRAM storage unit circuit schematic diagram in embodiment 1 of the application.

[0039] Figure 5 It is a basic layout of the SRAM storage unit in embodiment 1 of the application.

[0040] Figure 6 It is a layout of the SRAM storage unit in embodiment 1 of the application.

[0041] Figure 7 It is a flow chart of the preparation method of the static random access memory in embodiment 3 of the application.

[0042] Figure 8 It is a schematic diagram of providing the semiconductor substrate in step S100 of embodiment 3 of the application.

[0043] Figure 9 It is a schematic diagram of forming the first photoresist pattern in step S200 of embodiment 3 of the application.

[0044] Figure 10 A schematic diagram of forming the isolation groove in step S200 of the embodiment 3 of the present application.

[0045] Figure 11 A schematic diagram of forming the shallow trench isolation structure in step S200 of the embodiment 3 of the present application.

[0046] Figure 12 A schematic diagram of forming the second photoresist pattern in step S300 of the embodiment 3 of the present application.

[0047] Figure 13 A top view of forming the second photoresist pattern in step S300 of the embodiment 3 of the present application.

[0048] Figure 14 A schematic diagram of forming the sunken groove in step S300 of the embodiment 3 of the present application.

[0049] Figure 15 A schematic diagram of forming the N-well in step S400 of the embodiment 3 of the present application.

[0050] Figure 16 A schematic diagram of removing the first hard mask in step S400 of the embodiment 3 of the present application.

[0051] Figure 17 A schematic diagram of forming the P-well in step S400 of the embodiment 3 of the present application.

[0052] Figure 18 A schematic diagram of forming the gate material layer in step S500 of the embodiment 3 of the present application.

[0053] Figure 19 A schematic diagram of forming the anti-reflective coating in step S500 of the embodiment 3 of the present application.

[0054] Figure 20 A schematic diagram of forming the fourth photoresist pattern in step S500 of the embodiment 3 of the present application.

[0055] Figure 21A A schematic diagram of forming the bare gate in step S500 of the embodiment 3 of the present application.

[0056] Figure 21B A top view of forming the bare gate in step S500 of the embodiment 3 of the present application.

[0057] Figure 22A A schematic diagram of forming the stepped bare gate in step S500 of the embodiment 3 of the present application.

[0058] Figure 22B A top view of forming the stepped bare gate in step S500 of the embodiment 3 of the present application.

[0059] Figure 23Schematic diagram for removing the second hard mask on the top of the gate in step S600 of the embodiment 3 of the present application.

[0060] Figure 24 Schematic diagram for forming the first gate sidewall in step S600 of the embodiment 3 of the present application.

[0061] Figure 25 Schematic diagram for forming the NLDD region in step S600 of the embodiment 3 of the present application.

[0062] Figure 26 Schematic diagram for forming the gate with double sidewalls in step S600 of the embodiment 3 of the present application.

[0063] Figure 27 Schematic diagram for forming the source and drain in step S700 of the embodiment 3 of the present application.

[0064] Figure 28 Schematic diagram for forming the metal silicide layer in step S800 of the embodiment 3 of the present application.

[0065] Figure 29 Schematic diagram for forming the barrier layer in step S900 of the embodiment 3 of the present application.

[0066] Figure 30 Schematic diagram for forming the interlayer dielectric layer in step S900 of the embodiment 3 of the present application.

[0067] Figure 31 Schematic diagram for forming the contact hole in step S900 of the embodiment 3 of the present application.

[0068] Figure 32 Schematic diagram for filling the contact hole in step S900 of the embodiment 3 of the present application.

[0069] wherein, Figures 8 to 12 , Figures 14 to 21A , Figure 22A , Figures 23 to 32 are all Figure 5 A1-A2 broken line direction sectional view in the middle.

[0070] 100-P type silicon substrate, 110-deep N well, 120-first buffer oxide layer, 101-first hard mask, 102-first photoresist pattern, 103-isolation groove, 104-shallow trench isolation structure, 105-second photoresist pattern, 106-sunken groove, 107-N well, 108-third photoresist pattern, 109-P well; 111-NLDD region, 112-N + region; 200-SRAM memory cell, 201-first pass-gate transistor, 202-second pass-gate transistor, 203-first pull-up transistor, 204-second pull-up transistor, 205-first pull-down transistor, 206-second pull-down transistor, 220-metal silicide layer; 300-metal interconnection layer, 301-barrier layer, 310-metal line; 320-interlayer dielectric layer, 321-first layer of ILD film, 322-second layer of ILD film, 323-covering layer; 330-via hole; 331-contact barrier layer, 332-metal connection layer; 410-gate material layer; 411-second buffer oxide layer, 412-second hard mask, 413-bottom anti-reflective coating, 414-fourth photoresist pattern, 415-top anti-reflective coating, 416-silicon oxide; 420-gate oxide layer, 421-gate oxide material layer; 430-memory node region; 440-bare gate; 450-first gate sidewall, 460-second gate sidewall. DETAILED DESCRIPTION

[0071] The embodiments of the present application will be further described below in conjunction with the drawings and examples. The following examples are used to illustrate the present application, but cannot be used to limit the scope of the present application.

[0072] In the description of the present application, it should be noted that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0073] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0074] Before describing the technical solutions of the present application, the prior art related to the present application will be introduced, such as Figure 3As shown, it is a schematic diagram of cubic crystal system common for silicon-based semiconductor substrate, establish XYZ coordinate system with some end point of cubic crystal, the origin is O, the plane ABCD surrounded by cubic vertex A, B, C, D is (100) crystal face, the plane ABEF surrounded by cubic vertex A, B, E, F is (110) crystal direction, the plane CEFD surrounded by cubic vertex C, E, F, D is (001) crystal direction, and the plane DFGA surrounded by cubic vertex D, F, G, A is (010) crystal direction; due to the symmetry of semiconductor crystal, there are equivalent directions and plane family. Therefore, (100) crystal direction is (100) crystal face and all equivalent planes, for example, (100) direction, (010) direction and (001) direction crystal face. (110) crystal direction includes (110) crystal face and its equivalent crystal face, for example, (011) direction, (101) direction, (-1-10) direction, (0-1-1) direction, (-10-1) direction, (-110) direction, (0-11) direction and (10-1) direction crystal face; it can be seen from the above that the angle between (100) crystal face and (110) crystal face is 45 degrees. Figure 3

[0075] The above crystal direction is only an example of silicon-based semiconductor substrate, when other types of substrates are used, different crystal forms have different crystal directions, but in general, the carrier migration rate of NMOS and PMOS is different in different crystal directions, and often has a respective optimal crystal direction, and the crystal direction of the optimal carrier migration rate of NMOS and PMOS generally does not coincide.

[0076] Taking silicon-based semiconductor substrate as an example, the electron mobility in silicon crystal is highly related to the crystal direction, in (100) crystal direction, the effective mass of electron is minimum (about 0.19m0, m0 is the mass of free electron), resulting in the highest mobility (up to ~1500 cm² / (Vs) in bulk silicon); this direction can significantly improve the drive current and switching speed of NMOS. The hole mobility reaches the peak value (about ~500 cm² / (Vs) in bulk silicon) in (110) crystal direction, because the effective mass of hole is minimum (about 0.49m0) in this direction. Selecting this direction can optimize the on-state capability and response speed of PMOS.

[0077] The prior art also has a setting of saving area by sharing the source and drain of the pull-up transistor or the pull-down transistor, but this area-saving manner can cause the active area design of SRAM to be too compact, resulting in high heat generation, which affects the performance of the device; the present application improves the heat dissipation capacity by staggering the active area based on the advantages of the prior art, thereby maintaining the design of high-density and high-performance SRAM device, and also provides a corresponding preparation process.

[0078] Embodiment 1: The present embodiment provides an SRAM memory cell, as shown in the following figure: Figure 4 ​The circuit diagram of the SRAM memory unit provided by the application comprises six transistors, which are two transfer gate transistors, two pull-up transistors and two pull-down transistors respectively, and the gate of the pull-up transistor is connected with the source or the drain of the transfer gate transistor to form a storage node; Specifically, the six transistors are a first transfer gate transistor 201, a second transfer gate transistor 202, a first pull-up transistor 203, a second pull-up transistor 204, a first pull-down transistor 205 and a second pull-down transistor 206 respectively. The source region of the first transfer gate transistor 201 is connected to a bit line BL at a bit line node, the source region of the second transfer gate transistor 202 is connected to an inverted bit line BLB (complementary bit line) at an inverted bit line node, the two transfer gate transistors share a gate line, and the gate line is connected to a word line WL. Referring to FIGS. 1 and 2, Figure 5 and Figure 6 in the figures, Figure 5 and Figure 6 wherein D represents a drain, S represents a source, the first pull-up transistor 203 and the second pull-up transistor 204 share a drain, and the drain is connected to a power supply voltage / node Vdd; the first pull-down transistor 205 and the second pull-down transistor 206 share a source, and the source is connected to ground Vss (GND); the gate of the first pull-up transistor 203 and the gate of the first pull-down transistor 205 are connected to the drain of the first transfer gate transistor 201, a left storage node SNL is formed at the connection point, and the left storage node SNL is connected to the source of the second pull-up transistor 204 and the drain of the second pull-down transistor 206 through a metal line 310 of a metal interconnection layer 300. The gate of the second pull-up transistor 204 and the gate of the second pull-down transistor 206 are connected to the drain of the second transfer gate transistor 202, a right storage node SNR is formed at the connection point, and the right storage node SNR is connected to the source of the first pull-up transistor 203 and the drain of the first pull-down transistor 205 through the metal line 310 of the metal interconnection layer 300; the six transistors are connected in the above manner to form a latch storage bit.

[0079] The read operation of the SRAM memory unit 200 relies on the voltage signal difference of two bit lines (BL and BLB). Assuming that the SRAM memory unit stores data 0, at this time, SNL=0 and SNR=1, and the test conditions are: BL=BLB=1 and WL=1.

[0080] Under the conditions, 1. Since SNL=0 is at a low potential and SNR=1 is at a high potential, the first pull-up transistor 203 is turned on, the first pull-down transistor 205 is turned off, the second pull-up transistor 204 is turned off, and the second pull-down transistor 206 is turned on. 2. The complementary bit line BLB potential is maintained, but the second pull-down transistor 206 is opened, causing the current of the bit line BL to flow to the ground GND, resulting in the potential of the bit line BL to drop; Initially, BL=BLB=1, after the potential of BL drops, a voltage difference between BL and BLB occurs, and this signal is output through a peripheral amplification circuit, and thus the signal reading of the SRAM memory cell 200 is completed.

[0081] The write operation of the SRAM memory cell 200 relies on the inversion of the potentials of SNL and SNR. Suppose that the SRAM memory data is 0, at this time, SNL=0 and SNR=1.

[0082] The test conditions are as follows: BL=1, BLB=0, WL=1 Under these conditions: 1. Since SNL=0 is at a low potential and SNR=1 is at a high potential, the first pull-up transistor 203 is opened, the first pull-down transistor 205 is closed, the second pull-up transistor 204 is closed, and the second pull-down transistor 206 is opened. 2. Since BLB=0 and WL=1, the second transfer gate transistor 202 is opened, and the potential of the right storage node SNR gradually decreases. 3. The potential of the right storage node SNR decreases, causing the second pull-up transistor 204 to open and the second pull-down transistor 206 to close, and under the power supply of the power supply Vdd, the potential of the left storage node SNL is pulled up. 4. The potential of the left storage node SNL is pulled up, causing the first pull-down transistor 205 to open and the first pull-up transistor 203 to close, and the data is flipped.

[0083] The holding operation of the SRAM memory cell 200: the first transfer gate transistor 201 and the second transfer gate transistor 202 are closed, and the internal circuit is not modified.

[0084] The test conditions are as follows: BL=BLB=1, WL=0; Under these conditions, The first transfer gate transistor 201 and the second transfer gate transistor 202 are closed, and the bit line BL and the complementary bit line BLB cannot modify the data held in the storage node.

[0085] The present application designs the layout of the above-mentioned SRAM memory cell, as shown in Figure 5 , and Figure 5In the embodiment, the active regions of all the transistors are divided into three types according to the channel directions of the transistors; the channel directions of the two pass-gate transistors (the first pass-gate transistor 201 and the second pass-gate transistor 202) are set as the first direction, the channel directions of the two pull-up transistors (the first pull-up transistor 203 and the second pull-up transistor 204) are set as the second direction, and the channel directions of the two pull-down transistors (the first pull-down transistor 205 and the second pull-down transistor 206) are set as the third direction; the third direction is the same type direction as the first direction, and the channels of the two pull-up transistors (the first pull-up transistor 203 and the second pull-up transistor 204) are set to be sunken.

[0086] For example, the two pass-gate transistors and the two pull-down transistors are NMOS (N-type metal-oxide-semiconductor), and the two pull-up transistors are PMOS (P-type metal-oxide-semiconductor); taking a silicon-based semiconductor as an example, the carriers of the NMOS are electrons, and the NMOS has the best migration rate in the (100) direction; the carriers of the PMOS are holes, and the PMOS has the best migration rate in the (110) direction; therefore, the first direction is set as the (100) direction, the second direction is set as the (110) direction, and the third direction is set as the (010) direction or the (001) direction which is the same type direction as the first direction; in a silicon crystal, the angle between the (100) direction and the (110) direction is 45 degrees; in the layout design, taking the (100) direction as the horizontal direction as an example, the first direction is set as the horizontal direction, the second direction is set as the direction with an angle of 45 degrees with the horizontal direction, and the third direction is set as the vertical direction (the direction in the paper).

[0087] The application creatively sets the channel regions of the pass-gate transistors, the pull-down transistors and the pull-up transistors in different directions, so that the migration rates of the carriers of the active regions (channels) of the transistors are maximized, and excellent electrical performance of the device can be obtained without using stress silicon technology; on this basis, the application sets the pull-up transistors to be sunken, so that the channel regions of the PMOS are set to be staggered in height with the channel regions of the NMOS; the unexpected effect is that the application disperses the main heat points in space by setting the channels to be staggered, thereby achieving excellent heat dissipation capacity, avoiding the influence of device heating on electrical performance, and further shortening the spacing of the transistors, so that more SRAM memory cells can be set in a unit area, thereby obtaining a larger-capacity memory.

[0088] It should be noted that the angle between the first direction and the second direction is not fixed as 45 degrees, and can be changed in the range of 30-60 degrees; for different types of substrates, the crystal type can be different, the best crystal direction can be different, and therefore the angle between the first direction and the second direction can be different; specifically, the first direction and the second direction need to be determined according to the substrate type and the crystal direction; the third direction is the same type direction as the first direction, and therefore the third direction needs to be set accordingly.

[0089] The present invention sets the channel direction of the pull-down transistor to a third direction, which is offset from the first direction. In particular, when the third direction is perpendicular to the first direction, compared with setting the channel direction of the pull-down transistor to the first direction, the active area can be further saved and the size of the SRAM memory cell can be reduced. Furthermore, in this direction, the two pull-down transistors can share the source or drain, which can further save the active area and reduce heat generation.

[0090] In some embodiments, the two pull-up transistors share a common drain and are connected to the power supply Vdd through the common drain. For example, in the above embodiment, the first pull-up transistor 203 and the second pull-up transistor 204 share a common drain, which can further reduce the PMOS area, thereby making more SRAM memory cells 200 in a unit area of ​​substrate. At the same time, by sharing the drain, one contact hole and corresponding metal line are reduced, which reduces the process difficulty.

[0091] In some embodiments, such as Figure 5 As shown, the two pull-down transistors share a common source, which is connected to ground. For example, in the above embodiment, the first pull-down transistor 205 and the second pull-down transistor 206 share a common source, which can further reduce the active area, thereby making more SRAM memory cells in a unit area of ​​substrate. At the same time, by sharing the source, one contact hole and corresponding metal line are reduced, which reduces the process difficulty.

[0092] In some embodiments, such as Figure 5 As shown, two transfer gate transistors are located on the left, two pull-down transistors are located on the right, forming a quadrilateral area, and two pull-up transistors are located within the quadrilateral area. This relative positioning allows the six transistors to be distributed more compactly within the SRAM memory cell. Under the same process technology, the transistor density can be increased, which means the storage capacity per unit area can be increased.

[0093] Since there are four NMOS and two PMOS (two pull-up transistors), when the common drain of the two PMOS is arranged in the middle of the four NMOS, the minimum spacing between the active regions can be increased by arranging the NMOS and PMOS in different directions, in other words, the minimum spacing between the four NMOS can be further reduced, thereby further increasing the transistor arrangement density and designing a high-density static random access memory; however, when designing a high-density static random access memory, since the two PMOS are arranged in the middle of the four NMOS and are highly concentrated, heat dissipation is difficult, so although the storage density is increased, the heat dissipation capacity is poor, resulting in poor long-term operation stability of the device; the PMOS is arranged in a sunken manner, so that the channels of the PMOS and the NMOS are arranged staggeredly, avoiding the heat source (mainly the channel) of the NMOS from wrapping the heat source of the PMOS, thereby improving the heat dissipation capacity of the PMOS, and the unexpected effect is that the application achieves good actual heat dissipation effect, and simulation verification shows that the temperature is greatly reduced during use, thereby obtaining a high-density static random access memory with high stability.

[0094] In some embodiments, as shown in FIG. Figure 6 The gate of the pull-up transistor is directly connected to the source or drain of the corresponding transmission gate transistor by a metal silicide technology, and the gate of the pull-up transistor and the active region of the transmission gate transistor form a storage node, which is defined as a storage node region 430; for example, the gate of the pull-up transistor is arranged in a stepped manner with different heights, so that the gate of the pull-up transistor is the same height as the source or drain of the transmission gate transistor near the source or drain, so that the two can be connected by a metal silicide layer 220; for example, the gate of the first pull-up transistor 203 is connected to the drain of the first transmission gate transistor 201 by a metal silicide layer 220, and the gate of the second pull-up transistor 204 is connected to the drain of the second transmission gate transistor 202 by a metal silicide layer 220, which can greatly reduce the contact resistance by the metal silicide technology; through actual measurement, the contact resistance of the contact hole connection technology in the prior art is generally 10 -4 The above; and the application directly connects by a metal silicide layer, and the contact resistance is generally 10 -7 -10 -8 Therefore, the contact resistance of the application is 3-4 orders of magnitude lower, which can greatly reduce heat generation and improve device performance.

[0095] In some embodiments, the gates of the pull-up transistors and the pull-down transistors are connected by gate lines to reduce transmission resistance. For example, the gate of the first pull-up transistor 203 and the gate of the first pull-down transistor 205 are connected by the same gate line; the gate of the second pull-up transistor 204 and the gate of the second pull-down transistor 206 are connected by the same gate line; to reduce the heat generated during the reading and writing and storage of the SRAM memory cell 200.

[0096] In some embodiments, the two transmission gate transistors share the same gate line, and the two transmission gate transistors are controlled by the same gate line, which can reduce the use of word lines WL, thereby saving area and reducing process difficulty.

[0097] In some embodiments, as shown in Figure 5 , the gate width L3 of the pull-up transistor and the gate width L2 of the pull-down transistor are the same, and the gate width L1 of the transmission gate transistor is greater than the gate width L3 of the pull-up transistor, i.e. L1>L2=L3. By setting the gate width L3 of the pull-up transistor and the gate width L2 of the pull-down transistor to be the same, the change speed of the left storage node SNL and the right storage node SNR during the storage data change process of the SRAM memory cell is consistent, thereby improving the storage efficiency. Since the word line WL is in a high potential state during reading and accessing, the gate of the transmission gate transistor is in a powered-on state most of the time during the use of the SRAM. By setting the gate width L1 of the transmission gate transistor to be greater than the gate width L3 of the pull-up transistor, the heat generated by the gate of the transmission gate transistor during reading and accessing is reduced, thereby greatly reducing the operating temperature of the SRAM memory. Generally, L1 is 10-30% greater than L2, and the value within this range is a balance between electrical performance and area occupied.

[0098] In some embodiments, as shown in Figure 5 , the active region width W2 of the pull-down transistor, the active region width W1 of the transmission gate transistor, and the active region width W3 of the pull-up transistor decrease in turn, i.e. W2>W1>W3. By setting the active region width W3 of the pull-up transistor to be less than the active region width W1 of the transmission gate transistor, the current of the pull-up transistor is less than the current of the transmission gate transistor during data storage, thereby ensuring that the potential of the right storage node SNR decreases smoothly and data is efficiently stored. By setting the active region width W2 of the pull-down transistor to be greater than the active region width W1 of the transmission gate transistor, the current of the pull-down transistor is greater than the current of the transmission gate transistor during signal reading, thereby ensuring that the potential difference between BL and BLB is large enough to be accurately read.

[0099] Generally speaking, W2 should be about 10-40% larger than W1, and W1 should be about 10-40% larger than W3. This ratio range represents a balance between the overall device performance and area of ​​the SRAM memory cell.

[0100] In some embodiments, the pull-up transistor (or pull-down transistor) has a sink depth not less than the channel depth of the transmission gate transistor. More preferably, the pull-up transistor has a sink depth exactly equal to the channel depth of the transmission gate transistor (or pull-down transistor), which satisfies heat dissipation requirements and reduces manufacturing difficulty.

[0101] In some embodiments, such as Figure 6 As shown, the left memory node SNL is connected to the drain of the second pull-down transistor 206 and the source of the second pull-up transistor 204 through the metal interconnect 310 of the metal interconnect layer; the right memory node SNR is connected to the drain of the first pull-down transistor 205 and the source of the first pull-up transistor 203 through another metal interconnect 310 of the metal interconnect layer; the complete connection of the SRAM memory cell 200 is achieved through the metal interconnect layer 300. The present invention minimizes the connection of the metal interconnect layer through the above design, thereby reducing the heat generation of the entire device and improving the device's operational stability and electrical performance.

[0102] Example 2: This example provides a static random access memory (SRAM). The SRAM memory cell 200 from Example 1 is fabricated on a semiconductor substrate. Common semiconductor substrates include silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, gallium oxide, etc. Substrates are also divided into P-type substrates and N-type substrates, such as P-type silicon substrates and N-type silicon substrates. They can also be bulk silicon substrates or silicon-on-insulator (SOI) substrates; the appropriate selection is made according to the specific needs.

[0103] Example 3: As Figure 7 As shown, this embodiment provides a method for fabricating a static random access memory (SRAM), including the following steps: S100, provides semiconductor substrates; S200: The active region of each transistor is isolated by an isolation structure; S300: The area where the two pull-up transistors are located is etched using an etching process to form a recessed groove. S400: Ion implantation process is used to implant the corresponding type of ions into the active region of each transistor to form the well region of NMOS and PMOS respectively. S500: Prepare the bare gate of each transistor, and use an etching process to step up the bare gate of the pull-up transistor so that the height of the bare gate at the memory node is the same as the height of the active region of the transfer gate transistor. S600, a sidewall is made on the bare gate to obtain a gate; S700, a source and a drain are prepared; S800, the active region and the top surface of the gate are metal silicided to obtain a metal silicide layer; S900, a metal interconnection layer is prepared to connect the six transistors to form an SRAM memory cell.

[0104] In step S100, the silicon substrate can adopt a common substrate in the prior art. In the embodiment, the semiconductor substrate is a P-type silicon substrate 100, and a deep N well 110 (DWN) is prepared in the P-type silicon substrate 100, as shown in FIG. 1. Figure 8 The specific method is as follows: S110, a first buffer oxide layer 120 is prepared on the P-type silicon substrate 100.

[0105] For example, the first buffer oxide layer 120 with a certain thickness is formed on the P-type silicon substrate 100 by a furnace tube process. The first buffer oxide layer 120 is located between the silicon substrate and the hard mask layer, and is used to relieve the high tensile stress of silicon nitride and optimize the shallow trench isolation structure. The thickness is generally related to the process node. The actual thickness is determined by stress model simulation + defect detection data, and balance between protecting the silicon interface and process controllability is required. According to the prior art, the thickness can be 15-30 nm in a mature process, and the thickness can be 5-10 nm in an advanced node (28 nm and below). For example, the material of the first buffer oxide layer 120 is silicon oxide.

[0106] S120, a deep N well 110 is formed by ion implantation process; First, photoresist is coated on the P-type silicon substrate 100, and then photolithography exposure is performed using a mask plate (defining the deep N well region).

[0107] After development, the photoresist window is left in the region where the deep N well 110 is to be formed, and the other regions are covered with photoresist.

[0108] Through the photoresist window, high-energy N-type dopant ions (usually phosphorus or arsenic) are implanted into the silicon substrate. During the implantation process, the energy, dose, angle and depth can be selected to obtain a deep N well 110 that meets the requirements, as shown in FIG. 2. Figure 8 As shown in FIG. 3, Figure 8 As shown in FIG. 4, Figure 5 A1-A2 in FIG. 5 is a cross-sectional view in the direction of the fold line, Figure 8 The dashed line in FIG. 6 is Figure 5 The gate line of the first pull-up transistor 203 intersects with the active region junction line of the first transfer gate transistor 201.

[0109] For example, the implanted ions are P, the implantation energy is 3.0 MeV, and the implantation dose is 1.60E12 cm-2 The implant angle scheme is 2 / 0 / 1, and the implant depth is determined according to the structure size and process level of the SRAM cell, and can be 2000 angstroms for example.

[0110] Preferably, the ion implantation distribution obeys a Gaussian distribution, and multi-energy and multi-dose fractionation implantation can make the ion distribution more uniform, and annealing treatment can be performed after implantation to improve the quality of the obtained deep N well.

[0111] In step S200, the active area corresponding to each transistor is isolated by the isolation structure, which can be isolated by a shallow trench isolation structure 104 (STI), and the specific method is as follows: S210, depositing a first hard mask 101 on the first buffer oxide layer 120, and the first hard mask 101 is commonly made of Si3N4, TiN, TaN, W, etc.

[0112] S220, coating photoresist, then exposing and developing to obtain a first photoresist pattern 102, as shown in Figure 9 The window of the first photoresist pattern 102 is a shallow trench isolation structure 104; S230, etching by dry etching to obtain an isolation groove 103 (the groove of STI), and after removing the first photoresist pattern 102, as shown in Figure 10 In some embodiments, after the isolation trench is prepared, the isolation trench is also treated by an RTP process (rapid thermal annealing process), which on the one hand performs corner rounding treatment (corner rounding), reduces the concentration of electric field by rounding the sharp corners on both sides of the STI, and on the other hand can repair the damage of the dry etching to the active area (AA) of the side wall of the isolation trench.

[0113] In some embodiments, reactive ion etching (RIE) technology or atomic layer etching (ALE) is used to obtain an isolation trench with vertical side walls, which is beneficial to subsequent process preparation, especially to the sinking process of the pull-up transistor.

[0114] S240, filling the isolation material in the isolation trench and planarizing to stay on the first hard mask 101 to obtain a shallow trench isolation structure 104, as shown in Figure 11 The isolation material can be common isolation materials such as silicon dioxide, and for example, TEOS (tetraethoxysilane) is deposited by a high aspect ratio process (HARP) to fill the isolation trench to a height higher than that of the first hard mask 101.

[0115] An annealing process (RTP) is used to treat the porous TEOS into dense SiO2 to form an isolation material layer; ​​The isolation material layer is planarized by a CMP process, and stays on the first hard mask 101 to obtain a shallow trench isolation structure 104 (STI), as shown in Figure 11 .

[0116] In step S300, the area where the two pull-up transistors are located is etched by an etching process to form a sunken groove 106, including the following steps: S310, coating photoresist, then exposing and developing to obtain a second photoresist pattern 105, as shown in Figure 12 , the window of the second photoresist pattern 105 is the area where the two pull-up transistors are located, including the pull-up transistors and the shallow trench isolation structure 104 around them, as shown in Figure 13 , a plan view; S320, etching by an etching process to form a sunken groove 106, as shown in Figure 14 after removing the second photoresist pattern 105; during the etching process, the etching rate of the first hard mask 101, the first buffer oxide layer 120, the shallow trench isolation structure 104 and the deep N well 110 can be made the same by selecting the etching liquid and etching parameters, so that the area where the two pull-up transistors are located can basically maintain the same height drop; in order to further improve the etching quality, the first hard mask 101 and the first buffer oxide layer 120 can also be etched first, and then the shallow trench isolation structure 104 and the deep N well 110 are etched synchronously, so that the area where the two pull-up transistors are located is etched synchronously, and the etching depth of the sunken groove 106 is greater than or equal to the channel design depth of the transmission gate transistor (or the pull-down transistor), that is, greater than or equal to the depth of the NMOS channel. In actual process, the depth can be selected as 200-500 angstroms.

[0117] In S400, ions of corresponding types are implanted in the active area of each transistor by an ion implantation process, including the following steps: S410, directly implanting N-type ions in the area where the two pull-up transistors are located to obtain an N well 107, forming the active area of the pull-up transistor, as shown in Figure 15 ; since other areas are blocked by the shallow trench isolation structure 104 or the first hard mask 101 at this time, only N-type ions can be implanted in the active area of the pull-up transistor, without any yellow light process. The ions are generally selected from phosphorus (P) or arsenic ions (As), which can be implanted in three steps with different depths.

[0118] S420, removing the remaining first hard mask 101 by an etching process (such as wet etching), as shown in Figure 16 ; S430, coating photoresist, then exposing and developing to obtain a third photoresist pattern 108, the window of the third photoresist pattern 108 is the area where the active area of the transmission gate transistor and the pull-down transistor is located. S440, P-type ions are implanted in the active regions of the pass-gate transistor and the pull-down transistor to obtain a P-well 109, forming the active regions of the pass-gate transistor and the pull-down transistor, as shown in FIG. 4C, and then the third photoresist pattern 108 and the first buffer oxide layer 120 are removed, completing the definition of the active regions of the NMOS and the PMOS. Figure 17

[0119] S500, a bare gate 440 of each transistor is prepared, and the bare gate 440 of the pull-up transistor is stepped by an etching process, so that the bare gate 440 at the storage node is the same in height as the active region of the pass-gate transistor, as shown in FIG. 5C, and the process specifically includes the following steps: Figure 22A S510, a gate material is deposited and planarized to obtain a gate material layer 410, as shown in FIG. 6A, and the process specifically includes the following steps: Figure 18 S511, a gate oxide material layer 421 is deposited. The material of the gate oxide material layer 421 can be silicon dioxide, silicon oxynitride, high-k dielectric (such as HfO2), etc., and in the embodiment, is silicon dioxide, formed by a thermal oxidation process, and has a thickness of 20-30 angstroms.

[0120] S512, a gate material is deposited, which is a common gate material in the prior art, such as polysilicon, metal gate, work function layer, etc., and in the embodiment, is polysilicon; and after planarization, a gate material layer 410 is obtained, as shown in FIG. 6B. Figure 18

[0121] S520, a hard mask layer is prepared on the gate material layer 410. A second buffer oxide layer 411 is deposited on the gate material layer 410, and the material of the second buffer oxide layer 411 and the material of the first buffer oxide layer 120 are of the same type and have basically the same function. A second hard mask 412 is deposited on the second buffer oxide layer 411 to obtain the hard mask layer; and the material of the second hard mask 412 and the first hard mask 101 are of the same type and have basically the same function.

[0122] S530, an etching process is used to etch the gate shape of the pass-gate transistor, the pull-down transistor and the pull-up transistor, and the process specifically includes the following steps: S531, an anti-reflective coating is deposited on the second hard mask 412. For example, a bottom anti-reflective coating 413 (BARC) is deposited on the second hard mask 412. S532, photoresist is coated and a top anti-reflective coating 415 (TARC) is deposited, as shown in FIG. 7B. Figure 19 ​​​​​S533, then exposure and development, to get the fourth photoresist pattern 414, the fourth photoresist pattern 414 just covers all the transistor gate, that is, the window is the area outside all the transistor gate, as shown in Figure 20 ; Using etching process for etching, using high selectivity etching liquid, so that when the gate oxide material layer 421 outside the gate region of the transmission gate transistor and pull-down transistor is just etched completely, the gate material layer 410 outside the gate region of the pull-up transistor is etched completely, the specific formula of the etching liquid is determined according to the selectivity, which is a common technology in the prior art, the selectivity of the gate material layer 410 and the gate oxide material layer 421 can be 10-50:1, and the specific selectivity is determined according to the respective thickness of the gate material layer 410 and the gate oxide material layer 421, for example, the thickness of the gate oxide material layer 421 is 20 angstroms, and the thickness of the gate material layer 410 of the pull-up transistor is 200 angstroms, so the etching ratio needs to be selected as 10:1, and the etching liquid formula is selected according to the etching ratio and the respective material type for etching; after etching, the gate oxide layer 420 is formed just below the gate material layer 410 of the transmission gate transistor (or the pull-down transistor), and after removing the fourth photoresist pattern 414 and the bottom anti-reflective coating 413, the shape is as shown in Figure 21A , it can be seen that the gate of the pull-up transistor is stepped at the junction with the transmission gate transistor (at the storage node), and the top view is as shown in Figure 21B .

[0123] In another embodiment, if the gate oxide material layer 421 outside the gate region of the transmission gate transistor and pull-down transistor is just etched completely, and the gate material layer 410 outside the gate region of the pull-up transistor is not etched completely, the photoetching process can be used again to cover the area where the transmission gate transistor and pull-down transistor are located by using photoresist to protect the area, and the gate material layer 410 and the gate oxide material layer 421 outside the gate region of the pull-up transistor are continuously etched.

[0124] S540, the photoresist is coated again, then exposed and developed, to get the fifth photoresist pattern (not shown in the figure), and the window of the fifth photoresist pattern is part of the gate of the pull-up transistor at the junction with the transmission gate transistor (at the storage node); The gate height is reduced by the etching process, so that the height of the part of the gate of the pull-up transistor is flush with the height of the active area of the transmission gate transistor (or the pull-down transistor), and the storage node area 430 is formed, the fifth photoresist pattern is removed by ashing, and the residues, the second hard mask 412 and the second buffer oxide layer 411 are removed by wet cleaning, to get the bare gate 440, as shown in Figure 22A , the top view is as shown in Figure 22B .

[0125] S600, side wall manufacturing is performed on the bare gate 440 to obtain a gate electrode, including the following steps: S610, a first gate side wall 450 is prepared on both sides of the bare gate 440, as shown in Figure 24 .

[0126] Exemplarily, the following steps are included. S611, a ROX process (Recessed Oxide Isolation) is adopted to generate silicon oxide 416 on the sidewall of the bare gate 440; S612, the second hard mask 412 on the top of the gate electrode is removed, as shown in Figure 23 . In this embodiment, a hot phosphoric acid wet etching process is adopted to accurately remove the second hard mask 412 on the top of the gate electrode.

[0127] S613, a side wall material layer is deposited, the side wall material layer including any one of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride, and exemplarily, the application preferably is silicon nitride; S614, an anisotropic etching process is adopted to remove the side wall material layer and the second buffer oxide layer 411 on the top and surrounding area of the gate electrode to obtain the first gate side wall 450, as shown in Figure 24 . Specifically, a dry etching (plasma etching) is adopted to realize the anisotropic etching; the etching gas for etching Si3N4 is a mixed gas of CF4 / CHF3 / O2 (the selection ratio of Si3N4:SiO2 is greater than or equal to 10:1); and the etching gas for etching SiO2 is a mixed gas of C4F8 / CHF3 / Ar (the selection ratio of SiO2:Si is greater than or equal to 20:1).

[0128] S620, NMOS tube interfaces and PMOS tube interfaces are respectively prepared by an ion implantation process, the NMOS tube interfaces being required to be prepared for a transmission gate transistor and a pull-down transistor, and the PMOS tube interfaces being required to be prepared for a pull-up transistor; Exemplarily, the NMOS tube interfaces and the PMOS tube interfaces are prepared by adopting an LDD process, and the specific method is as follows: S621, an NMOS photoresist is coated, and an active area of the transmission gate transistor and the pull-down transistor is exposed by exposure and development; S622, ion implantation is performed to form an NLDD area 111 (N-type light-doped drain), to obtain the NMOS tube interface, as shown in Figure 25 . The application provides an injection mode, in which Ge, C, In, B (pockect, pocket ion implantation), N, P, and AS elements are sequentially implanted to a certain depth to form the NLDD area.

[0129] This embodiment provides an exemplary injection parameter as follows: Ge element ion implantation parameters: energy 15 keV, dose 3.0E14, implantation angle scheme 0 / 0 / 4 (tilt angle / rotation angle / dose coefficient, the same applies below), implantation depth 131 angstroms; C element ion implantation parameters: energy 10 keV, dose 3.0E14, implantation angle scheme 0 / 0 / 4, implantation depth 260 angstroms; The implantation of Ge and C ions breaks up the silicon in the substrate, allowing for better control of the implantation depth; In ion implantation parameters: energy 65 keV, dose 6.0E12, implantation angle scheme 37 / 90 / 2, implantation depth 480 angstroms; Boolean ion implantation parameters: energy 9 keV, dose 3.4E13, implantation angle scheme 37 / 90 / 2, implantation depth 362 angstroms; Pocket ion implantation, where the ion junction is deeper than the channel, prevents source-drain interconnection.

[0130] Nitrogen ion implantation parameters: energy 8 keV, dose 10E15, implantation angle scheme 0 / 0 / 4, implantation depth 200 angstroms; nitrogen implantation can improve the reliability of time-dependent dielectric breakdown (TDDB) for NMOS.

[0131] P element ion implantation parameters: 2 keV, dose 7.74E13, implantation angle scheme 0 / 0 / 4, implantation depth 28 angstroms; As ion implantation parameters: energy 2 keV, concentration 8.69E14, implantation angle scheme 0 / 0 / 4, implantation depth 20 angstroms. The junction depth in the NLDD region is shallower than the channel to prevent the HCI effect (hot carrier injection effect).

[0132] It should be noted that the above parameters are for illustrative purposes only and can be adjusted according to the actual application of the device and the level of advancement in the manufacturing process.

[0133] S623. Coat with PMOS photoresist and expose the active region of the pull-up transistor by exposure and development; S624, Ion implantation is performed to form a PLDD region ( Figure 25 (Not shown in the image), the PMOS transistor connection is obtained.

[0134] This invention provides an injection method in which Ge, AS (pockect, pocket ion implantation), and BF2 are sequentially injected to a certain depth to form a PLDD region.

[0135] This embodiment provides an exemplary injection parameter as follows: Ge element ion implantation parameters: energy 15keV, dose 3.0E14, implant angle scheme 0 / 0 / 4, implant depth 131 angstroms; implant Ge ions, which disperse silicon in the substrate, and better control the implant depth.

[0136] As element ion implantation parameters: energy 50KeV, dose 1.8E13, implant angle scheme 30 / 0 / 4, implant depth 322 angstroms; pocket ion implantation, ion junction depth is deeper than the channel, preventing source-drain penetration.

[0137] BF2 implantation parameters: dose 1.6KeV, dose 1.01E15, implant angle scheme 0 / 0 / 4, implant depth 80 angstroms; PLDD region junction depth is shallower than the channel, preventing HCI effect (hot carrier injection effect).

[0138] It should be noted that the above parameters are only for illustration, and can be adjusted according to the actual device purpose and process advanced degree.

[0139] In other embodiments, a second gate spacer can also be prepared on both sides of the gate, and the present application provides an example as follows: S630, a second gate spacer 460 is prepared on both sides of the first gate spacer 450; as Figure 26 shown.

[0140] S631, a ROX process (Recessed Oxide Isolation) is used to deposit silicon oxide; S632, a side wall material layer is deposited, the side wall material layer comprising any one of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, and an exemplary, the present application preferably is silicon nitride; S633, an anisotropic etching process is used to remove the side wall material layer and silicon oxide on the top and surrounding area of the gate, to obtain the second gate spacer 460, and to obtain a gate with a dual spacer, as Figure 26 shown. Specifically, dry etching (plasma etching) is used to realize anisotropic etching; the etching gas for etching Si3N4 is CF4 / CHF3 / O2 mixed gas (the selection ratio of Si3N4:SiO2 is ≥ 10:1). The etching gas for etching SiO2 is C4F8 / CHF3 / Ar (the selection ratio of SiO2:Si is ≥ 20:1).

[0141] In S700, the preparation of the source and drain includes the following steps: Through an ion heavy doping process, the source and drain regions of the NMOS are heavily doped to obtain an N + region 112, and the source and drain regions of the PMOS are heavily doped to obtain a P+ area( Figure 27 (not shown in the image), to obtain the corresponding source and drain electrodes, and use photolithography to cover the areas that do not need to be doped.

[0142] In some embodiments, N + The region is mainly injected with P, GE, P, As, and F at a certain depth in sequence. + The region is mainly injected with Ge, B, and BF2 to a certain depth, and then subjected to peak annealing at a certain temperature, such as around 1050℃, mainly to fix the injected ions within a certain region.

[0143] In S800, the active region and the top surface of the gate are metallized to obtain a metallized layer, as shown in the figure. Figure 28 As shown, the main steps are as follows: S810. Remove the photoresist left from the previous process, and then deposit a barrier layer to cover the areas where metal silicide does not need to be formed. The barrier layer can be a combination of silicon oxide and silicon nitride, and can be formed by first depositing and then etching. The areas where metal silicide needs to be formed are the exposed active area and the top of the gate. S820, pre-cleaning, etching away part of the silicon layer at the top of the active region and the gate (the substrate silicon of the active region and the polysilicon exposed at the top of the gate are collectively referred to as the silicon layer). For example, SiCoNi (typically a vapor phase etching technique based on HF / ethanol or other formulations) is used to remove the native oxide layer on the silicon (Si) surface; approximately 60 angstroms (6 nanometers) thick silicon layer is etched away, and the etching thickness can be 20-800 angstroms, depending on the actual needs; S830, Deposit a nickel-platinum alloy layer on the pre-cleaned silicon layer surface; Physical vapor deposition (PVD, such as sputtering) is typically used. The thickness is approximately 120 Å (12 nanometers), and can range from 40 to 1600 angstroms. The specific thickness can be selected based on actual needs.

[0144] The main functions of platinum are as follows: Lower the temperature at which disilicides form; Suppressing nickel diffusion into polysilicon gates and source / drain areas; Improve the morphological stability of nickel silicides on narrow lines to prevent junction leakage and contact resistance degradation; Reduce bridging issues in nickel silicides.

[0145] S840, depositing a capping layer on a nickel-platinum alloy layer; For example, the cap layer is TiN with a thickness of about 500 Angstrom (5 nm). The cap layer functions as follows: Prevent nickel from being oxidized during subsequent thermal processes. As a diffusion barrier, limit the diffusion of metal atoms (especially nickel) into the silicon or the overlying media.

[0146] Help maintain the stress state of the film and improve thermal stability.

[0147] Provide a relatively inert surface for subsequent process handling.

[0148] S850, first rapid thermal annealing (RTP) to form a high-resistance metal silicide; For example, the first rapid thermal annealing conditions are 290°C for 30 seconds. At this lower temperature, the NiPt alloy begins to react with the underlying silicon (Si) in a solid-state reaction; a nickel-rich silicide Ni2PtSi (Ni-rich phase) is formed, which has a high resistivity, so a second rapid thermal annealing is needed. S860, second rapid thermal annealing (RTP) to form a low-resistance metal silicide layer, connecting the gate of the pull-up transistor to the active area of the transmission transistor in the storage node.

[0149] Convert the nickel-rich phase silicide Ni2PtSi formed in the previous step to a silicon-rich phase NiPtSi2 (Si-rich phase).

[0150] For example, the formed NiPtSi2 has a thickness of about 2000 Angstrom (20 nm), which is a typical target thickness. The actual thickness depends on the initial metal thickness and the reaction conditions, and generally can vary between 100-300 Angstrom.

[0151] The silicon-rich phase NiPtSi2 is the final desired low-resistance phase (C54 crystal structure) with good thermal stability and contact performance.

[0152] The temperature (usually in the range of 650°C - 850°C, the specific temperature depends on the process node, material system and design target) and time of the second rapid thermal annealing are critical. Too low a temperature cannot complete the phase transition, and too high a temperature can cause excessive growth of the silicide or increase the junction depth.

[0153] S870, selectively remove the residual nickel platinum alloy (NiPt), cap layer and barrier layer that did not participate in the silicide reaction, complete the preparation of the metal silicide, and obtain a metal silicide layer 220, as shown in Figure 28 .

[0154] The residual nickel platinum alloy (NiPt), cap layer and barrier layer are etched using wet chemical etching (Wet Etch), usually using a mixed acid solution (such as SPM / HPM, or a specific formula based on HNO3 / HCl / HF, also known as Selective Nickel Etch).

[0155] The NiPt alloy, TiN cap layer and barrier layer are etched in a specific etching solution, while the silicide NiPtSi 2 formed on the silicon surface and the exposed medium layer such as silicon dioxide (SiO2) or silicon nitride (SiN) have high etching resistance.

[0156] In S900, a metal interconnection layer 300 is prepared by a metal interconnection process, the left storage node SNL is connected to the drain of the second pull-down transistor 206 and the source of the second pull-up transistor 204 through the metal line 310 of the metal interconnection layer 300; the right storage node SNR is connected to the drain of the first pull-down transistor 205 and the source of the first pull-up transistor 203 through the metal line 310 of the metal interconnection layer 300; the complete connection of the SRAM storage unit 200 is realized through the metal interconnection layer 300, and the connection of the metal interconnection layer 300 is minimized by the above design method, thereby reducing the heating capacity of the entire device and improving the operation stability and electrical performance of the device.

[0157] Meanwhile, the six transistors also need to be led out through the metal interconnection process, which can be realized by using the prior art and has no influence on the implementation of the present application, therefore, the present application will not be described in detail.

[0158] The specific steps in S900 are as follows: S910, a barrier layer 301 is deposited by a CVD process to a certain thickness, for example, Figure 29 The material of the barrier layer 301 can be SiN, and the thickness can be selected in the range of 200-330 angstroms.

[0159] S920, an interlayer dielectric layer 320 (ILD) is deposited, and the deposition is performed in multiple times, and an exemplary process is as follows: Step 1, a HARP (High Aspect Ratio Process) process technology is used to deposit a certain thickness of TEOS (Tetraethylorthosilicate, tetraethyl orthosilicate)-based silicon dioxide (SiO2) to obtain a first layer of ILD thin film 321, and the thickness can be selected in the range of 200-2000 angstroms, and an exemplary selection is 1100 angstroms.

[0160] HARP (High Aspect Ratio Process) has excellent gap-filling ability; HARP TEOS (typically O3-based sub-atmospheric pressure chemical vapor deposition, SA-CVD) is specifically designed to fill narrow and deep high aspect ratio structures, effectively filling gaps without creating voids or seams.

[0161] The HARP process exhibits conformality, providing excellent step coverage.

[0162] The HARP process can perform substrate coverage, serving as the base layer of the ILD, covering and electrically isolating the underlying active devices and wiring structures (including the NiPtSi silicide formed above).

[0163] Step 2: Deposit PE TEOS (Plasma Enhanced TEOS) as a thicker second ILD film 322 using CD CVD (Chemical Deposition Chemical Vapor Deposition) technology, with a thickness of 2000 angstroms-4000 angstroms, for example, 3600 angstroms.

[0164] CD CVD technology enables high-speed deposition, with a deposition rate significantly higher than that of HARP (SA-CVD) technology, making it suitable for rapidly constructing thick dielectric layers.

[0165] CD CVD process has better density; PE TEOS is denser than O3-based SA-CVD TEOS.

[0166] The ILD film deposited by the CD CVD process is the basis for planarization. This thicker PE TEOS layer is the host layer that provides the main material for subsequent chemical mechanical polishing (CMP) planarization.

[0167] Step 3: Grind the ILD flat using chemical mechanical polishing (CMP); By utilizing the synergistic effect of chemical etching and mechanical polishing, the raised areas on the wafer surface are ground away, ultimately resulting in a very flat surface, creating conditions for photolithography.

[0168] Step 4: Deposit a capping layer 323 on the planarized ILD surface to obtain an interlayer dielectric layer 320, such as... Figure 30 As shown; TEOS SiO2 was deposited using PECVD TEOS; the thickness was approximately 600 angstroms (60 nanometers), typically 400-800 angstroms.

[0169] Protect the just planarized, clean ILD surface from contamination or slight scratches that can be caused by subsequent processes (such as storage, transportation).

[0170] S930, etching the contact hole 330 First, coat photoresist, define the position of the contact hole 330 by exposure and development; Then, open the contact hole 330 using dry etching process, as shown in Figure 31 ; S940, fill the contact hole 330; Use wet (WET) cleaning process to clean the residual material left during etching the contact hole, then deposit a titanium metal layer and a titanium nitride metal layer as the contact barrier layer 331 in sequence; The titanium metal layer serves as an adhesion layer / contact layer, increasing the adhesion of the titanium nitride metal layer, preventing peeling, and reducing the contact resistance; the thickness is 80-120 angstroms, and an exemplary thickness is 100 angstroms; The titanium nitride metal layer serves as a diffusion barrier layer 301 / adhesion layer; TiN has very good adhesion with tungsten (W), which is conducive to the nucleation and deposition of W, and avoids the reaction between WF6 and Ti during W deposition to form defects; the thickness of the titanium nitride metal layer is 30-70 angstroms, and an exemplary thickness is 50 angstroms.

[0171] Continue to deposit a tungsten metal layer as a metal connection layer 332, which needs to fill the entire contact hole 330; Use CMP process to planarize, complete the lead preparation of the contact hole 330, as shown in Figure 32 .

[0172] S950, perform line production on the metal layer to obtain the metal interconnection layer 300; the existing metal interconnection process is used for production, which has no impact on the technical problems solved by the present application, and the present application will not be described in detail.

[0173] The application isolates the active region through the isolation structure firstly, then performs the sinking etching on the area where the pull-up transistor is located through the etching process; then forms the active region of the transfer gate transistor, the pull-down transistor and the pull-up transistor through the ion implantation process; then forms the bare gate through the etching process, and the bare gate is stepped through twice etching in the process of forming the bare gate, so that the height of the bare gate at the storage node is same with that of the active region of the transfer gate transistor; thereby providing the basic condition for connecting the gate of the pull-up transistor and the active region of the transfer gate transistor through the metal silicide, then makes the side wall and performs the metal silicide treatment on the storage node area, then performs the source and drain manufacturing, and finally prepares the metal interconnection layer to complete the preparation of the static random access memory; the unexpected effect is that the preparation of the above special structure static random access memory is completed through the simple and mature process, and in the preparation process, the connection resistance between the gate of the pull-up transistor and the active region of the transfer gate transistor is reduced through the metal silicide technology, so that the storage node can store and read and write data efficiently and stably, and can also ensure the relatively low heating resistance, and the unexpected technical effect is achieved.

[0174] The above embodiments are only used for describing the present application, but not limiting the present application. Although the present application is described in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications or equivalent replacements of the technical solutions of the present application do not deviate from the spirit and scope of the present application, and should be covered in the scope of the claims of the present application.

Claims

1. An SRAM memory cell, comprising: The SRAM memory unit comprises at least six transistors, which are two transfer gate transistors, two pull-up transistors and two pull-down transistors respectively, and the gate of the pull-up transistor and the source or drain of the transfer gate transistor are connected to form a storage node; The channel direction of the two transfer gate transistors is set as a first direction, the channel direction of the two pull-up transistors is set as a second direction, and the channel direction of the two pull-down transistors is set as a third direction, the third direction and the first direction are the same family crystal direction, and the two pull-up transistors are set to sink.

2. The SRAM cell of claim 1, wherein, The first direction is (100) crystal direction, the second direction is (110) crystal direction, and the third direction is (010) crystal direction or (001) crystal direction.

3. The SRAM cell of claim 1, wherein, The two pull-down transistors share a source, the two pull-up transistors share a drain, and the two transfer gate transistors share the same gate line.

4. The SRAM cell of claim 3, wherein, The gate width of the pull-up transistor and the pull-down transistor is the same, and the gate width of the transfer gate transistor is greater than the gate width of the pull-up transistor.

5. The SRAM cell of claim 1, wherein, The active area width of the pull-down transistor, the active area width of the transfer gate transistor and the active area width of the pull-up transistor decrease in turn.

6. The SRAM cell of claim 1, wherein, The sinking amount of the pull-up transistor is not less than the channel depth of the transfer gate transistor or the pull-down transistor.

7. A static random access memory, comprising: The semiconductor substrate and a plurality of SRAM memory units formed on the semiconductor substrate, the SRAM memory unit comprises at least six transistors, which are two transfer gate transistors, two pull-up transistors and two pull-down transistors respectively, and the gate of the pull-up transistor and the source or drain of the transfer gate transistor are connected to form a storage node; The channel direction of the two transfer gate transistors is set as (100) crystal direction, the channel direction of the two pull-up transistors is set as (110) crystal direction, and the channel direction of the two pull-down transistors is set as (010) crystal direction or (001) crystal direction, and the two pull-up transistors are set to sink.

8. A method of manufacturing the static random access memory of claim 7, wherein, The steps include: Providing a semiconductor substrate; Isolating the active area of each transistor by an isolation structure; Sinking etching the area where the two pull-up transistors are located by an etching process to form a sinking groove; Ion implantation process is adopted to implant ions of corresponding types in the active area of each transistor to form the well area of NMOS and PMOS respectively; The bare gate of each transistor is prepared, and the bare gate of the pull-up transistor is stepped by an etching process, so that the height of the bare gate at the storage node is the same as that of the active area of the transfer gate transistor; The bare gate is made into a gate by side wall production; The source and the drain are prepared; The active area at the storage node and the top surface of the gate are metal silicified to obtain a metal silicide layer; A metal interconnection layer is prepared to connect the six transistors to form an SRAM memory unit.

9. The method for preparing a static random access memory according to claim 8, characterized in that, The isolation structure adopts a vertical side wall isolation structure.

10. The method of claim 8, wherein the method further comprises: When the sinking groove is formed, the active area of the two pull-up transistors and the isolation structure around them are sunk together.

11. The method of claim 8, wherein the method further comprises: The bare gate of each transistor is prepared, and the bare gate of the pull-up transistor is stepped by an etching process, so that the height of the bare gate at the storage node is the same as that of the active area of the transfer gate transistor, which includes the following steps: Coating photoresist, using exposure and development technology, to obtain a photoresist pattern in the shape of a gate electrode; Etching the gate electrode material outside the photoresist coverage; Recoating photoresist, using exposure and development technology, to obtain a photoresist pattern exposing the storage node region; Etching the gate electrode material in the storage node region to make the height of the gate electrode material layer at the storage node the same as the height of the transmission gate transistor.

12. The method of claim 8, wherein the method further comprises: Metallization of the active region at the storage node and the top surface of the gate electrode to obtain a metal silicide layer, including the following steps: Pre-cleaning, etching away part of the silicon layer at the top of the active region and the gate electrode in the storage node region; Depositing a nickel-platinum alloy layer on the surface of the pre-cleaned silicon layer; Depositing a cap layer on the nickel-platinum alloy layer; First rapid thermal annealing to form a high-resistance metal silicide; Second rapid thermal annealing to form a low-resistance metal silicide layer.

13. The method of claim 8, wherein the method further comprises: During the preparation of the metal interconnection layer, the left storage node SNL is connected to the source of the second pull-up transistor and the drain of the second pull-down transistor through a metal line, and the right storage node SNR is connected to the source of the first pull-up transistor and the drain of the first pull-down transistor through a metal line.

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