Back contact crystalline silicon solar cell and back contact photovoltaic module

Abstract

The embodiment of the invention provides a back contact crystalline silicon solar cell and a back contact photovoltaic module, the back contact crystalline silicon solar cell comprises a crystalline silicon substrate, the back surface of the crystalline silicon substrate is alternately provided with a first region and a second region, and the first region comprises a current collection region and a lamination region; in the collector region, the back surface of the crystalline silicon substrate is sequentially provided with a doped internal expansion layer, a first interface passivation layer, an N-type doped polycrystalline silicon layer, a transparent conductive oxide layer and a first back electrode, and a plurality of protruding structures are distributed on the surface of the N-type doped polycrystalline silicon layer. The contact area between the protruding structure and the first back electrode through the transparent conductive oxide layer is increased, so that the transmission resistance loss of carriers transported from the crystalline silicon substrate to the first back electrode is reduced, and the photoelectric conversion efficiency of the back contact crystalline silicon solar cell is improved.

Description

Technical Field

[0001] This application relates to the field of solar cells, and more particularly to a back-contact crystalline silicon solar cell and a back-contact photovoltaic module. Background Technology

[0002] HTBC (Heterojunction Tunnel Oxide Back Contact) solar cell technology is a high-efficiency crystalline silicon solar cell technology. It combines the technical features of TBC (Tunnel Oxide Back Contact) crystalline silicon solar cells and heterojunction crystalline silicon solar cells, and is a highly promising high-efficiency crystalline silicon solar cell. However, there is still considerable room for improvement in the contact performance of the back N-region electrode to the back contact crystalline silicon solar cell. Summary of the Invention

[0003] To address the aforementioned technical problems, this application discloses a back-contact crystalline silicon solar cell and a back-contact photovoltaic module, thereby improving the contact performance between the N-region electrode on the back side of the back-contact crystalline silicon solar cell and the back-contact crystalline silicon solar cell.

[0004] In a first aspect, this application provides a back-contact crystalline silicon solar cell, comprising: A crystalline silicon substrate, wherein a first region and a second region are alternately disposed on the back side of the crystalline silicon substrate, the first region including a current collection region, a stacked region, and an overlap region located between the current collection region and the stacked region; In the current collection region, the back side of the crystalline silicon substrate is sequentially provided with a doped inner expansion layer, a first interface passivation layer, an N-type doped polycrystalline silicon layer, a transparent conductive oxide layer, and a first back electrode, and the surface of the N-type doped polycrystalline silicon layer is distributed with multiple protruding structures.

[0005] In some embodiments of this application, the maximum height of the protruding structure is H. max 50nm≤H max ≤100nm.

[0006] In some embodiments of this application, the maximum width of the protruding structure is W. max 20nm≤W max ≤100nm.

[0007] In some embodiments of this application, the number of protruding structures in the target area of ​​the current collection region is 1 to 10, and the target area is any 200nm×200nm rectangular area in the current collection region.

[0008] In some embodiments of this application, the protruding structure has a hemispherical or near-hemispherical structure.

[0009] In some embodiments of this application, the transparent conductive oxide layer constitutes a first conductive path between the N-type doped polycrystalline silicon layer and the first back electrode.

[0010] In some embodiments of this application, in the stacked region, the back side of the crystalline silicon substrate is sequentially provided with a doped inner layer, a first interface passivation layer, an N-type doped polycrystalline silicon layer, a second interface passivation layer, and a P-type doped silicon layer.

[0011] In some embodiments of this application, in the second region, a second interface passivation layer, a P-type doped silicon layer, a transparent conductive oxide layer, and a second back electrode are sequentially disposed on the back side of the crystalline silicon substrate, and the back side of the crystalline silicon substrate has a back textured structure.

[0012] In some embodiments of this application, the material of the P-type doped silicon layer includes P-type doped amorphous silicon, P-type doped nanocrystalline silicon, and P-type doped silicon microcrystalline silicon.

[0013] Secondly, this application provides a back-contact photovoltaic module, the back-contact photovoltaic module comprising a back-contact crystalline silicon solar cell as described in the first aspect.

[0014] Compared with the prior art, this application has at least the following beneficial effects: This application provides a back-contact crystalline silicon solar cell and a back-contact photovoltaic module. The back-contact crystalline silicon solar cell includes a crystalline silicon substrate. The back side of the crystalline silicon substrate is alternately provided with a first region and a second region. The first region includes a current-collecting region, a stacked region, and an overlap region located between the current-collecting region and the stacked region. In the current-collecting region, the back side of the crystalline silicon substrate is sequentially provided with a doped inner expansion layer, a first interface passivation layer, an N-type doped polycrystalline silicon layer, a transparent conductive oxide layer, and a first back electrode. The surface of the N-type doped polycrystalline silicon layer has multiple protruding structures with sputtered transparent conductive oxide layers of high conductivity, which increases the contact area between the conductive metal particles in the electrode paste of the first region and the N-type doped polycrystalline silicon layer through the transparent conductive oxide layer, thereby reducing the transport resistance loss of charge carriers from the crystalline silicon substrate to the first back electrode, and thus improving the photoelectric conversion efficiency of the back-contact crystalline silicon solar cell. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a back-contact crystalline silicon solar cell according to one embodiment of this application; Figure 2 This is a schematic diagram of a protruding structure in one embodiment of this application; Figure 3 This is a schematic diagram of the protruding structure in another embodiment of this application; Figure 4 This is a schematic diagram of a conductive path in one embodiment of this application; Figure 5 This is a schematic diagram of the formation of a first interface passivation layer in one embodiment of this application; Figure 6 This is a schematic diagram of forming an N-type doped polysilicon layer in one embodiment of this application; Figure 7 This is a schematic diagram of the formation of a mask layer in one embodiment of this application; Figure 8 This is a schematic diagram illustrating the formation of a first region and a second region in one embodiment of this application; Figure 9 This is a schematic diagram of a velvet structure formed in one embodiment of this application; Figure 10 This is a schematic diagram illustrating the formation of a front passivation layer and a back alumina layer in one embodiment of this application; Figure 11 This is a schematic diagram of the formation of an antireflection layer in one embodiment of this application; Figure 12 This is a schematic diagram illustrating the removal of the back aluminum oxide layer in one embodiment of this application; Figure 13 This is a schematic diagram of the formation of a second interface passivation layer and a P-type doped amorphous silicon layer in one embodiment of this application; Figure 14 This is a schematic diagram of a protruding structure formed in one embodiment of this application; Figure 15 This is a schematic diagram of the deposition of a transparent conductive oxide layer in one embodiment of this application; Figure 16 This is a schematic diagram illustrating the formation of an isolation structure in one embodiment of this application; Figure 17 This is a schematic diagram of laser parameters in one embodiment of this application.

[0017] Explanation of reference numerals in the attached figures: 1-Crystal silicon substrate, 3-Protruding structure, 4-Doped inner extension layer, 5-First interface passivation layer, 6-N-type doped polycrystalline silicon layer, 7-Second interface passivation layer, 8-P-type doped amorphous silicon layer, 9-Transparent conductive oxide layer, 10-Isolation structure, 11-First back electrode, 12-Second back electrode, 13-Front passivation layer, 14-Antireflection layer, 21-First region, 22-Second region, 26-Back alumina layer, 31-Back textured structure, 32-Front textured structure, 101-PSG layer, 102-Mask layer, 111-First conductive path, 112-Second conductive path, 211-Current collector region, 212-Stacked region, 213-Overlapping region. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0020] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0021] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0022] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0023] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.

[0024] Firstly, embodiments of this application provide a back-contact crystalline silicon solar cell. (See reference...) Figure 1 The back-contact crystalline silicon solar cell includes a crystalline silicon substrate 1. A first region 21 and a second region 22 are alternately disposed on the back side of the crystalline silicon substrate 1. The first region 21 corresponds to an N-type region, and the second region 22 corresponds to a P-type region. The first region 21 includes a current-collecting region 211, a stacked region 212, and an overlap region 213 located between the current-collecting region 211 and the stacked region 212. The overlap region 213 is formed by a transparent conductive oxide layer 9. The current-collecting region 211 refers to the region in the first region 21 used for collecting current, and the stacked region 212 refers to the region in the first region 21 other than the current-collecting region 211 and the overlap region 213. In the current collection region 211, the back side of the crystalline silicon substrate 1 is sequentially provided with a doped inner expansion layer 4, a first interface passivation layer 5, an N-type doped polycrystalline silicon layer 6, a transparent conductive oxide layer 9, and a first back electrode 11. The surface of the N-type doped polycrystalline silicon layer 6 is distributed with multiple protruding structures 3 sputtered with transparent conductive oxide layers with high conductivity. That is, the surface of these protruding structures 3 is sputtered with a layer of transparent conductive oxide material, which has high conductivity. This increases the contact area between the conductive metal particles in the electrode paste of the first region and the N-type doped polycrystalline silicon layer through the transparent conductive oxide layer. This helps to reduce the transmission resistance loss of charge carriers transported from the crystalline silicon substrate to the first back electrode, thereby improving the photoelectric conversion efficiency of the back contact crystalline silicon solar cell.

[0025] In some embodiments of this application, reference is made to Figure 2 The maximum height of the protruding structure 3 is H max 50nm≤H max ≤100nm. For example, H max For 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm. H max Within the aforementioned range, it is beneficial to increase the contact area between the transparent conductive oxide layer 9 and the first back electrode 11 through more protruding structures, thereby further increasing the contact area between the conductive metal particles in the electrode paste of the first region and the transparent conductive oxide layer and the N-type doped polysilicon layer.

[0026] In this embodiment, the height of the protruding structure refers to the distance between the bottom and top of the protruding structure along the thickness direction of the back-contact crystalline silicon solar cell.

[0027] In this embodiment, the conductive metal particles include silver particles and silver-coated copper particles.

[0028] In some embodiments of this application, reference is made to Figure 2 The maximum width of the protruding structure is W max 20nm≤W max ≤100nm. For example, W max For 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm. W max Within the aforementioned range, it is beneficial to increase the contact area between the protruding structure and the first back electrode through the transparent conductive oxide layer, thereby helping to reduce the transport resistance loss of charge carriers from the crystalline silicon substrate to the first back electrode.

[0029] In some embodiments of this application, reference is made to Figure 3 , Figure 3 This is a schematic diagram of the protruding structure when viewed along the thickness direction of the back-contact crystalline silicon solar cell. Within the target region of the current collector, the number of protruding structures 3 ranges from 1 to 10. The target region refers to any 200nm × 200nm rectangular area within the current collector region when viewed along the thickness direction of the back-contact crystalline silicon solar cell. Having the number of protruding structures 3 within the above range within the target region helps increase the contact area between the protruding structure and the first back electrode through the transparent conductive oxide layer, thereby reducing the transport resistance loss of charge carriers from the crystalline silicon substrate to the first back electrode.

[0030] In some embodiments of this application, reference is made to Figure 4 The protruding structure 3 has a hemispherical or near-hemispherical structure. This shape structure further increases the contact area between the protruding structure and the first back electrode through the transparent conductive oxide layer, thereby helping to reduce the transport resistance loss of charge carriers from the crystalline silicon substrate to the first back electrode.

[0031] In some embodiments of this application, reference is made to Figure 4 The transparent conductive oxide layer 9 forms the first conductive path 111 between the N-type doped polycrystalline silicon layer 6 and the first back electrode 11.

[0032] In some embodiments of this application, reference is made to Figure 4The protruding structure 3 covering the transparent conductive oxide layer 9 forms a second conductive path 112 between the N-type doped polycrystalline silicon layer 6 and the first back electrode 11. By cooperating with the first conductive path 111 to transmit current, the transmission resistance loss of charge carriers transported from the crystalline silicon substrate to the first back electrode can be further reduced.

[0033] In some embodiments of this application, reference is made to Figure 1 In the stacked region 212, the back side of the crystalline silicon substrate 1 is sequentially provided with a doped inner extension layer 4, a first interface passivation layer 5, an N-type doped polycrystalline silicon layer 6, a second interface passivation layer 7, and a P-type doped amorphous silicon layer 8.

[0034] In some embodiments of this application, reference is made to Figure 1 The first region 21 has at least one isolation structure 10, thereby electrically insulating the transparent conductive oxide layers 9 on both sides of the isolation structure 10. The number of isolation structures in this embodiment can be flexibly set according to the structural design requirements of the back-contact crystalline silicon solar cell. For example, a corresponding isolation structure 10 can be provided between the first region 21 and the second region 22. The shape of the isolation structure in this embodiment includes, but is not limited to, a groove shape; for example, the isolation structure can be an isolation groove.

[0035] In some embodiments of this application, reference is made to Figure 1 In the second region 22, the back side of the crystalline silicon substrate 1 is sequentially provided with a second interface passivation layer 7, a P-type doped amorphous silicon layer 8, a transparent conductive oxide layer 9, and a second back electrode 12, and the back side of the crystalline silicon substrate 1 has a back textured structure 31.

[0036] In some embodiments of this application, reference is made to Figure 1 A passivation layer 13 and an antireflection layer 14 are sequentially disposed on the front side of the crystalline silicon substrate 1, and the front side of the crystalline silicon substrate 1 has a textured surface structure 32. The passivation layer, the antireflection layer and the textured surface structure can passivate the front side of the crystalline silicon substrate 1, reduce the reflection of sunlight and improve the utilization rate of sunlight.

[0037] In this embodiment, the material of the first interface passivation layer 5 may include at least one of various dielectric materials, such as silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the first interface passivation layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation performance, can minimize the recombination loss of minority carriers on the semiconductor substrate surface, and is a thin film with excellent durability for subsequent high-temperature processes. To better provide interface passivation for the substrate, the thickness of the first interface passivation layer can be 0.1 nm to 5 nm. For example, the thickness of the first interface passivation layer can be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc. However, this application is not limited to these values, and the thickness of the first interface passivation layer can have various values. The first interface passivation layer acts as a barrier for electrons and holes and can combine with the polycrystalline silicon layer to prevent minority carriers from passing through. The first interface passivation layer can also act as a pinhole channel, allowing charge carriers in the back contact crystalline silicon solar cell to move freely. The selective passage of majority charge carriers is generated by the heavily doped polycrystalline silicon, which helps to reduce the recombination loss of minority charge carriers.

[0038] In this embodiment, the thickness of the N-type doped polycrystalline silicon layer 6 is 30nm~500nm; the thickness of the P-type doped amorphous silicon layer 8 is 5nm~100nm; the transparent conductive oxide layer 9 is made of indium tin oxide (ITO) and has a thickness of 20nm~150nm; the electrode is made of silver; the front passivation layer 13 is made of aluminum oxide and has a thickness of 0.1nm~100nm; the antireflection layer 14 is made of materials including but not limited to silicon nitride, silicon oxynitride, and silicon oxide, and has a thickness of 30nm~180nm.

[0039] This application also provides a method for preparing a back-contact solar cell according to any of the above embodiments, comprising the following steps: Step A, Reference Figure 5 A clean crystalline silicon substrate 1 is provided, and a first interface passivation layer 5 is deposited on the back side of the crystalline silicon substrate 1; Step B, Reference Figure 6 A phosphorus-doped amorphous silicon layer is deposited on the back side of the first interface passivation layer 5, and then an N-type doped polycrystalline silicon layer 6 is formed after high-temperature crystallization; and a doped inner expansion layer 4 is formed between the crystalline silicon substrate 1 and the first interface passivation layer 5, and a PSG layer 101 is formed on the surface of the N-type doped polycrystalline silicon layer 6. Step C: Remove the PSG layer; Step D, Reference Figure 7 A mask layer 102 is formed on the surface of the N-type doped polysilicon layer 6; Step E, Reference Figure 8Laser is used to perform laser film opening on the second region 22 (i.e. the region to be texturized) on the back of the crystalline silicon cell, and the mask layer 102 in this region is removed. Step F, Reference Figure 9 After wet texturing, the first region 21 will not be etched under the protection of the mask layer 102, while a back textured structure 31 is formed in the second region 22, and a front textured structure 32 is formed on the front side of the crystalline silicon substrate 1. Step G, Reference Figure 10 Atomic layer deposition (ALD) process is used to simultaneously deposit aluminum oxide (Al2O3) on the front and back sides of the crystalline silicon substrate 1, thereby forming a front passivation layer 13 on the front side and a back aluminum oxide layer 26 on the back side. Step H, Reference Figure 11 An antireflection layer 14 is deposited on the surface of the front passivation layer 13 using a plasma-enhanced chemical vapor deposition (PECVD) process. Step I, Reference Figure 12 A chain wet cleaning machine was used to remove the silicon nitride winding plating and aluminum oxide layer on the back side; Step J, Reference Figure 13 Using PECVD process, a second interface passivation layer 7 and a P-type doped amorphous silicon layer 8 are sequentially deposited on the surfaces of the first region 21 and the second region 22. Step K, Reference Figure 14 The second interface passivation layer 7 and the P-type doped amorphous silicon layer 8 are patterned to form a current collection region 211 in the first region 21 and a protruding structure 3 at the same time. Step L, Reference Figure 15 A transparent conductive oxide layer 9 is deposited on the back side of the back-contact crystalline silicon cell; Step M, Reference Figure 16 The transparent conductive oxide layer 9 is subjected to isolation grooving treatment, the treatment area of ​​the isolation grooving treatment is located in the first region 21, thereby forming at least one isolation structure 10 in the first region 21, forming a stacked region 212, and forming an overlap region 213 between the current collection region 211 and the stacked region 212. Step N, Reference Figure 1 Metallization is performed on the back side of the back-contact crystalline silicon solar cell to form a first back electrode 11 and a second back electrode 12.

[0040] Before step A, the crystalline silicon substrate can be pre-cleaned, that is, the silicon wafer is immersed in a sodium hydroxide or potassium hydroxide solution with a concentration of 15wt%~25wt% to remove the lines, damage, dirt and particles on the surface of the silicon wafer, and obtain a clean and flat crystalline silicon substrate with a thickness of 100μm~220μm. In step A, a 1 nm to 2 nm thick SiO2 layer can be deposited on the crystalline silicon substrate 1 as a first interface passivation layer 5 by tubular low-pressure chemical vapor deposition (LPCVD). The first interface passivation layer has uniform small holes perpendicular to the direction of the crystalline silicon substrate, with a hole diameter of 0.5 nm to 2 nm. These small holes allow charge carriers to pass through.

[0041] In step B, the process of forming the N-type doped polycrystalline silicon layer includes: firstly, depositing a phosphorus-doped amorphous silicon layer on the back side of the first interface passivation layer using LPCVD; then, introducing a phosphorus source POCl3 for diffusion propagation, causing the phosphorus-doped amorphous silicon layer to crystallize at high temperature to form the N-type doped polycrystalline silicon layer; wherein, the POCl3 liquid temperature is 20℃~30℃, the N2 flow rate is 1L / min~2L / min, the O2 flow rate is 0.3L / min~1L / min, the propagation time is 15min~25min, the furnace temperature and deposition temperature are 830℃~870℃, the deposition time is 15min~25min, the diffusion junction depth is 200nm~300nm, the sheet resistance of the N-type doped polycrystalline silicon layer is 50Ω / sq~100Ω / sq, and the diffusion concentration is 5×10⁻⁶. 19 atoms / cm 3 ~6×10 20 atoms / cm 3 ; In step C, the PSG layer formed on the front side of the crystalline silicon substrate during the phosphorus diffusion process can be removed by a horizontal chain machine. The de-coating solution is a mixture of nitric acid and sulfuric acid, wherein the mass fraction of nitric acid is 20%~30% and the mass fraction of sulfuric acid is 10%~20%. The de-coating temperature is 25±3℃ and the de-coating time is 60s~120s.

[0042] In step D, a layer of silicon nitride (SiN) can be deposited on the back side of the N-type doped polycrystalline silicon layer using a PECVD process. x As a mask layer, its thickness is 20nm~120nm; In step E, the laser parameters are: wavelength 266nm~532nm, test power 40W~60W, frequency 800KHz~1500KHz, single pulse energy 50mJ~100mJ, and unit pulse energy density 200mJ / cm². 2 ~400mJ / cm 2 The line spacing is 90μm~150μm, the scanning speed is 20m / s~80m / s, and the overlap rate in the spacing direction is 10%~30%.

[0043] In this embodiment, the test power refers to the power automatically calculated by the laser device based on the current parameters; the spacing direction overlap rate refers to the percentage of the width of the overlapping area of ​​the laser spot along the grid line direction to the size of a single spot.

[0044] In step F, a wet texturing process is performed to form alternating first and second regions on the back side of the crystalline silicon substrate 1, and a front-side texturing structure is formed on the front side of the crystalline silicon substrate. In the second region, a back-side texturing structure is formed on the back side of the crystalline silicon substrate 1. The silicon nitride of the mask layer undergoes a wet texturing process, and after treatment with alkaline solution and hydrofluoric acid solution, this mask layer is finally removed. The texturing process can adopt a conventional wet texturing process for back-contact crystalline silicon solar cells, with appropriate texturing additives used; this application has no particular limitations.

[0045] In step G, the precursor of the Al2O3 layer can be trimethylaluminum (TMA) and O2, or TMA and N2O. The deposition temperature is 180℃~220℃, the TMA flow rate is 50sccm~200sccm, the TMA pulse time is 0.1s~0.3s, the O2 or N2O flow rate is 300sccm~1000sccm, the O2 or N2O pulse time is 0.2s~0.5s, the deposition pressure is 0.5Tor~2Tor, the purging time is 3s~8s, the number of cycles is 80~150, the deposition rate is 3nm / min~8nm / min, the Al2O3 film thickness is controlled to be 10nm~20nm, and the annealing temperature at the end of deposition is 380℃~420℃.

[0046] In step H, the PECVD process parameters are as follows: silane (SiH4) flow rate of 300 sccm~600 sccm, NH3 flow rate of 1000 sccm~2500 sccm, N2 flow rate of 2000 sccm~5000 sccm, deposition temperature of 400℃~450℃, deposition pressure of 0.2 Tor~1.5 Torr, RF power of 100W~300W, deposition time of 180s~300s, and antireflection layer thickness of 70nm~100nm. After the antireflection layer is deposited, it can be sintered at 730℃~750℃ for 30s~90s, and then photoimplanted at 600℃~700℃ for 10s~60s to improve passivation performance.

[0047] In step I, the wet cleaning process is as follows: acid washing 1 (hydrochloric acid: 1wt%~10wt%, HF: 0.1wt%~2wt%, time: 30s~90s), alkaline washing (sodium hydroxide: 1wt%~5wt%, hydrogen peroxide: 5wt%~10wt%, time: 120s~180s), O3 washing 1 (O3: 10ppm~50ppm, HCl: 0.1wt%, time: 120s~180s), acid washing 2 (hydrochloric acid: 5wt%~10wt%, hydrogen peroxide: 5wt%~15wt%, time: 120s~240s), O3 washing 2 (O3: 10ppm~50ppm, HCl: 0.1wt%, time: 120s~180s), and slow HF extraction (HF: 10wt%~20wt%, time: 30s~60s).

[0048] In step J, the second interface passivation layer and the P-type doped amorphous silicon layer can be formed using a plate-type PECVD equipment. The thickness of the second interface passivation layer is 1 nm to 10 nm, the thickness of the P-type doped amorphous silicon layer 8 is 2 nm to 15 nm, and the phosphorus doping concentration is 5 × 10⁻⁶. 19 atoms / cm 3 ~9×10 19 atoms / cm 3 .

[0049] In step K, the second interface passivation layer 7 and the P-type doped amorphous silicon layer 8 in the designed current collection region 211 can be initially removed using a laser, followed by wet cleaning to thoroughly remove the second interface passivation layer 7, the P-type doped amorphous silicon layer 8, and any remaining laser residue from the laser-opened region. (Reference) Figure 17 The laser parameters are as follows: the spot width D is 100μm~250μm, the longitudinal length H of the spot is 100μm~300μm, H∶D=1~1.3, and the width of the overlapping area of ​​the laser spot is W, which is 10μm~40μm. Within the range of H, D, H:D, W, there will be a double laser enhancement zone in the overlapping area of ​​the light spot. The local temperature in the overlapping area is higher than that in the non-overlapping area. In the N-type doped polycrystalline silicon layer in the local overlapping area, the polycrystalline silicon undergoes vaporization. The polycrystalline silicon that cannot vaporize and detach in time forms a protruding structure. The wet cleaning process is as follows: alkaline cleaning (sodium hydroxide 1~2%, hydrogen peroxide 5~10%, time 150~200s), O3 cleaning (O3: 10ppm~50ppm, HCl: 0.5wt%~1wt%, time: 100s~150s), acid cleaning 1 (HF: 1wt%~5wt%, hydrogen peroxide: 5wt%~15wt%, time: 120s~240s), acid cleaning 2 (HF: 1wt%~5wt%, time: 30s~90s).

[0050] In step L, a transparent conductive oxide layer can be deposited on the back film surface by PVD process with a power of 5kW~7kW, a deposition temperature of 160℃~190℃, a deposition pressure of 0.7pa~1.0pa, an oxygen content of 2.5%~3.0%, and a thickness of 50nm~100nm.

[0051] In step M, the isolation trenching can be performed using a wet etching process. For example, an acidic etching paste can be used for screen printing, followed by drying and cleaning to selectively etch away a portion of the transparent conductive oxide layer 9 in the first region 21, forming a patterned isolation structure 10 with a width of 50 μm to 200 μm. This application does not have any particular limitation on the acidic etching paste, as long as it can etch the transparent conductive oxide layer.

[0052] In step N, during the metallization process, electrode paste can be applied to the surface of the transparent conductive oxide layer 9 in the first region 21 and the second region 22, and after curing, a first back electrode 11 and a second back electrode 12 are formed. The electrode paste can be a silver-coated copper paste (silver content 10wt%~90wt%, balance copper). The curing and photoinjection processes can be performed using a chain furnace or a cassette furnace. The electrode grid line width is 5μm~15μm, and the height is 8μm~20μm.

[0053] This application also provides a back-contact photovoltaic module, the back-contact photovoltaic module comprising a back-contact crystalline silicon solar cell as described in the first aspect.

[0054] This application also provides a back-contact photovoltaic module, which is used to convert received light energy into electrical energy and transmit it to an external load. The back-contact photovoltaic module includes: at least one back-contact crystalline silicon solar cell string, which is formed by connecting multiple back-contact crystalline silicon solar cells; an encapsulating film for covering the surface of the back-contact crystalline silicon solar cell string; and a cover plate for covering the surface of the encapsulating film that faces away from the back-contact crystalline silicon solar cell string.

[0055] The foregoing has provided a detailed description of a back-contact crystalline silicon solar cell and a back-contact photovoltaic module disclosed in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core inventive points of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A back-contact crystalline silicon solar cell, characterized in that, include: A crystalline silicon substrate, wherein a first region and a second region are alternately disposed on the back side of the crystalline silicon substrate, the first region including a current collection region, a stacked region, and an overlap region located between the current collection region and the stacked region; In the current collection region, the back side of the crystalline silicon substrate is sequentially provided with a doped inner expansion layer, a first interface passivation layer, an N-type doped polycrystalline silicon layer, a transparent conductive oxide layer, and a first back electrode, and the surface of the N-type doped polycrystalline silicon layer is distributed with multiple protruding structures.

2. The back-contact crystalline silicon solar cell according to claim 1, characterized in that, The maximum height of the protruding structure is H. max 50nm≤H max ≤100nm.

3. The back-contact crystalline silicon solar cell according to claim 1, characterized in that, The maximum width of the protruding structure is W. max 20nm≤W max ≤100nm.

4. The back-contact crystalline silicon solar cell according to claim 1, characterized in that, Within the target area of ​​the current collection region, the number of protruding structures is 1 to 10, and the target area is any 200nm×200nm rectangular area within the current collection region.

5. The back-contact crystalline silicon solar cell according to claim 1, characterized in that, The protruding structure has a hemispherical or near-hemispherical structure.

6. The back-contact crystalline silicon solar cell according to claim 1, characterized in that, The transparent conductive oxide layer forms the first conductive path between the N-type doped polycrystalline silicon layer and the first back electrode.

7. The back-contact crystalline silicon solar cell according to claim 1, characterized in that, In the stacked region, the back side of the crystalline silicon substrate is sequentially provided with a doped inner extension layer, a first interface passivation layer, an N-type doped polycrystalline silicon layer, a second interface passivation layer, and a P-type doped silicon layer.

8. The back-contact crystalline silicon solar cell according to claim 1, characterized in that, In the second region, a second interface passivation layer, a P-type doped silicon layer, a transparent conductive oxide layer, and a second back electrode are sequentially disposed on the back side of the crystalline silicon substrate, and the back side of the crystalline silicon substrate has a back textured structure.

9. The back-contact crystalline silicon solar cell according to claim 7 or 8, characterized in that, The materials of the P-type doped silicon layer include P-type doped amorphous silicon, P-type doped nanocrystalline silicon, and P-type doped silicon microcrystalline silicon.

10. A back-contact photovoltaic module, characterized in that, The back-contact photovoltaic module includes the back-contact crystalline silicon solar cell as described in any one of claims 1 to 9.

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