Hardware architecture of multi-port memory

Abstract

The invention discloses a hardware architecture of a multi-port memory, and belongs to the technical field of computer memory hardware circuit design. The core comprises a plurality of input ports, a plurality of output ports, a plurality of linked list FIFOs (First In First Out), an input switch internet, a plurality of block memory units, a plurality of reordering queues and an output switch internet, wherein the input port is connected with the block memory unit through the linked list FIFO and the input switch internet, and the block memory unit is connected with the output port through the output switch internet and the reordering queue. By introducing an innovative hardware architecture and a network interconnection architecture, resource consumption is effectively reduced while efficient and large-scale ports are realized, and memory access efficiency and parallel processing capability are improved; the method can be widely applied to high-performance computing, heterogeneous computing, data center acceleration and other application scenes needing high concurrent access and high throughput of a large number of ports, and stable operation of the system can be ensured under the condition of high load.

Description

Technical Field

[0001] This invention belongs to the field of computer memory hardware circuit design technology, and specifically relates to a hardware architecture for multi-port memory. Background Technology

[0002] With the increasing demands of modern computer systems and digital circuit design applications, the requirements for the number of memory access ports and throughput are becoming increasingly stringent. In high-performance heterogeneous computing, multiple processing units often need to access memory concurrently to support efficient data processing and communication. However, existing multi-port memory design schemes have significant technical bottlenecks and defects in addressing these requirements. For example, multiplexing schemes obtain multiple ports through clock division, but sacrifice operating frequency, resulting in limited memory access speed and becoming a bottleneck for system performance, making it difficult to meet high throughput requirements. Memory copying schemes copy the entire memory for each access port, providing an independent access path, but the storage space is not scalable, storage resource utilization is low, and hardware resources are consumed enormously as the number of ports increases. LVT / XOR schemes use lookup tables or XOR logic to implement multi-port access. As the number of ports increases, the consumption of RAM blocks and logic resources increases quadratically, severely limiting the scalability of the scheme. Traditional memory bank partitioning schemes divide the address space into fixed segments and bind them to ports, resulting in a complex programming model, limiting data access flexibility, and failing to buffer requests, making it difficult to cope with sudden access traffic, further exacerbating conflicts and latency.

[0003] In addition, traditional multi-port memory designs are inadequate in handling port contention, data consistency, and out-of-order response, which affects system performance and stability. Summary of the Invention

[0004] In view of the above-mentioned technical problems and shortcomings, this invention aims to solve the problems of high hardware resource consumption, poor scalability, port access conflicts, and out-of-order response in traditional multi-port memory designs, and to achieve efficient large-scale port memory functionality while reducing resource consumption, meeting the requirements of high concurrency access and high throughput. This invention proposes a hardware architecture for multi-port memory, and the specific technical solution adopted is as follows: Its core includes multiple input ports and multiple output ports, multiple linked lists (FIFOs), an input switch interconnection network, multiple block memory units, multiple reordering queues, and an output switch interconnection network; among them, Multiple linked lists (FIFOs) are associated with and connected to the input ports to buffer port access requests and ensure that data is not lost according to the first-in-first-out principle. An input switch interconnection network, whose input end is connected to multiple linked FIFO lists and whose output end is connected to multiple block memory units, is used to realize dynamic routing between port requests and block memory units; Multiple block memory units are used to store data. The address space is divided in a non-segmented manner, and each port can access any block memory unit. The output switch interconnection network has its input end connected to multiple block memory units and its output end connected to multiple reordering queues, which is used to realize dynamic routing of read response data from block memory units; Multiple reordering queues are connected to the output ports one by one, and are used to sort the memory read response data to ensure that the read data is output in the correct order.

[0005] Preferably, the multiple input ports and multiple output ports include multiple write ports and multiple read ports. The input ports correspond to the access request input and data input of the write port and the access request input of the read port, and the output ports correspond to the data output read by the read port, for data interaction with external processing units.

[0006] Preferably, the linked list FIFO is implemented based on shared RAM blocks, uses a linked list structure to manage the request data of each port, and uses a free pointer to uniformly manage the allocation and reclamation of free storage space in the shared RAM blocks, and the depth of the linked list FIFO is greater than the number of input ports.

[0007] Preferably, both the input switch interconnection network and the output switch interconnection network are interconnection networks composed of multi-level Banyan switches. The switching status of each level of Banyan switch is dynamically controlled by a counter that increments every cycle to achieve balanced connection between the input port and the output port.

[0008] Preferably, the block memory unit is composed of a single-port RAM or a dual-port RAM, and the total memory space is divided by an interleaved striping method.

[0009] Preferably, the reordering queue tracks the status of read response data in each queue entry using a one-bit array. The status includes "existing" and "in transit". The returned response data is stored in the corresponding queue position according to the request ID and the response data status is updated. The data can only be output when the data status at the head of the queue is "existing" to ensure that the read response is output in the order of the request.

[0010] The beneficial effects of the above-mentioned technical solution adopted in this invention include at least the following: By implementing a linked list FIFO within a shared RAM block, combined with a relatively simple switch interconnect network, hardware resource consumption is effectively reduced, avoiding the quadratic resource consumption of traditional LVT / XOR schemes and lowering hardware costs. Simultaneously, the linked list FIFO buffers input requests, and with the dynamic routing selection of the input switch interconnect network, it reduces port contention, prevents lost or disordered port requests, and improves memory access efficiency and system reliability. The structure design, employing independent block memory units and interconnected switch networks, allows for convenient and flexible expansion of the number of ports and memory capacity, supporting port sizes from 4 to 256, meeting the needs of various complex applications requiring high concurrency and high throughput. Furthermore, by reordering the output port read responses using a queue, the out-of-order read response problem is solved, ensuring data consistency and correctness, further enhancing system stability and reliability. By partitioning the address space without segmentation, each port can access any block memory unit, improving memory utilization efficiency and flexibility. Through the above design, this invention achieves efficient large-scale ports while effectively reducing resource consumption, improving memory access efficiency and parallel processing capabilities, and meeting the high concurrency and high throughput requirements of complex systems for large-scale multi-port memory access. Attached Figure Description

[0011] Figure 1 This is an overall block diagram of the hardware architecture of a multi-port memory provided in one embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the data structure and working principle of a linked list FIFO provided in one embodiment of the present invention. Figure 3 This is a schematic diagram illustrating the principle and structure of a switch interconnection network according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a block memory unit address mapping structure provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of a multi-port memory structure implemented with dual-port block RAM according to an embodiment of the present invention. Figure 6 This is a schematic table illustrating the working principle and process of a reordering queue provided in one embodiment of the present invention. Detailed Implementation

[0012] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a multi-port memory hardware architecture proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0014] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0015] like Figure 1 This diagram illustrates an overall block diagram of a multi-port memory hardware architecture according to an embodiment of the present invention. Its core components include: multiple input ports and multiple output ports, multiple linked FIFO lists, an input switch interconnection network, multiple block memory units, multiple reordering queues, and an output switch interconnection network; wherein, Multiple linked lists (FIFOs) are associated with and connected to the input ports to buffer port access requests and ensure that data is not lost according to the first-in-first-out principle. An input switch interconnection network, whose input end is connected to multiple linked FIFO lists and whose output end is connected to multiple block memory units, is used to realize dynamic routing between port requests and block memory units; Multiple block memory units are used to store data. The address space is divided in a non-segmented manner, and each port can access any block memory unit. The output switch interconnection network has its input end connected to multiple block memory units and its output end connected to multiple reordering queues, which is used to realize dynamic routing of read response data from block memory units; Multiple reordering queues are connected to the output ports one by one, and are used to sort the memory read response data to ensure that the read data is output in the correct order.

[0016] Specifically, access requests issued by the external processing unit are buffered in the corresponding linked list FIFO through the input port. The requests output by the linked list FIFO are dynamically routed to the target block memory unit through the input switch interconnection network. After the block memory unit performs data read and write operations, the read response data is routed to the corresponding reordering queue through the output switch interconnection network. After the reordering queue sorts the out-of-order data, it returns the ordered data to the external processing unit through the output port. Figure 1It clearly demonstrates the connections and interactions between the various modules in the system, and clearly presents the data flow and overall system structure, which helps to understand the system architecture and working principle of this invention.

[0017] Furthermore, in one embodiment of the present invention, the plurality of input ports and the plurality of output ports include a plurality of write ports and a plurality of read ports. The input ports correspond to the access request input and data input of the write ports and the access request input of the read ports, and the output ports correspond to the data output read by the read ports, for data interaction with external processing units.

[0018] Specifically, each write port and read port has corresponding control signals and data buses. The write port is used to send requests and data to the corresponding memory unit, and the read port is used to send requests to the corresponding memory unit and receive data from the corresponding memory unit.

[0019] Furthermore, in one embodiment of the present invention, the linked list FIFO is implemented based on shared RAM blocks, uses a linked list structure to manage the request data of each port, and uses a free pointer to uniformly manage the allocation and reclamation of free storage space in the shared RAM blocks, and the depth of the linked list FIFO is greater than the number of input ports.

[0020] Specifically, the linked list FIFO is a linked list-based FIFO queue. It uses linked lists as the basic data storage structure and is implemented within a shared RAM block. The shared RAM block stores request data from all input ports, with each input port corresponding to an independent linked list FIFO. There are two types of linked lists: a port linked list, which has a head pointer and a tail pointer pointing to the head and tail of the port's linked list, respectively. The list pointers maintain the linked list structure and manage the list through enqueue and dequeue operations for request data; and a free linked list, which has a free pointer that always points to the beginning of the free list within the shared RAM block. This free pointer manages unused or released free storage space within the shared RAM block. With enqueue and dequeue operations for request data, the free pointer dynamically updates the free list, allocating and reclaiming free storage space within the shared RAM block to reflect the current free space status.

[0021] like Figure 2 This document illustrates the data structure and working principle of a linked list FIFO provided in one embodiment of the present invention. Taking the operation process of 3 ports and 3 clock cycles as an example, it demonstrates the enqueue and dequeue operations of the request information of the ports in the linked list FIFO, as well as the changes in the data linked list of different ports, intuitively presenting the working mechanism of the linked list FIFO.

[0022] like Figure 2In Figure A, in the initial state, the FIFO of port 0 has 3 request messages, the FIFO of port 1 has no request messages, and the FIFO of port 2 has 1 request message. Each port FIFO reserves an empty message space for the next incoming value to store the next incoming request message. This avoids insufficient space when enqueuing requests and ensures system stability. like Figure 2 In Figure B, during the first clock cycle, the linked list FIFO receives a push containing a port 0 request message 3. The new port 0 request message 3 is stored in the empty message space at the end of the port 0 linked list. An empty space is popped from the empty linked list. This space is pushed into the port 0 linked list to form a new port 0 empty message space; like Figure 2 In Figure C, during the second clock cycle, the linked list FIFO receives a pop message containing a port 0 request message and a push message containing a port 1 request message. In this case, the space for the popped port 0 request message is pushed onto the linked list of port 1. The available space linked list remains unchanged; like Figure 2 In Figure D, during the third clock cycle, the linked list FIFO receives a pop message containing a port 0 request message. The head of the port 0 linked list will pop port 0 request message 1. The newly freed space is pushed into the empty linked list.

[0023] In particular, as a preferred approach, the total depth of the linked list FIFO in the embodiments of the present invention is configured to be significantly greater than the number of input ports, which provides sufficient buffering capacity for handling short bursts of access, effectively smooths the traffic, avoids request loss or backpressure being prematurely transmitted to external processing units, and improves the overall robustness of the system.

[0024] Furthermore, in one embodiment of the present invention, both the input switch interconnection network and the output switch interconnection network are interconnection networks composed of multi-level Banyan switches. The switching states of each level of Banyan switches are dynamically controlled by a counter that increments every cycle to achieve balanced connection between the input ports and the output ports.

[0025] Specifically, the switch interconnection network is a multi-level interconnection network composed of multiple levels of Banyan switches. Each level contains N / 2 columns of Banyan switches, where N is the total number of ports. A Banyan switch is implemented by combining two multiplexers using a single control bit. It has two inputs and two outputs, and two states: in the ON state (control bit 1), the input port cross-transmits data to the opposite output port; in the OFF state (control bit 0), the input port directly transmits data to the corresponding output port. By controlling the switching state of each column of Banyan switches, the transmission path can be flexibly adjusted, effectively achieving specific routing from input ports to output ports.

[0026] like Figure 3 It illustrates the principle and structure of a switch interconnection network provided by an embodiment of the present invention. It shows in detail the arrangement of Banyan switches in the switch interconnection network and the principle of different signal routing through control bit settings, which can help understand the signal transmission path selection in the network.

[0027] like Figure 3 As shown, this is an 8x8 switch interconnection network, consisting of 8 inputs, 8 outputs, and three columns of Banyan switches. Only the second column of Banyan switches is ON (control bit 1); the first and third columns are OFF (control bit 0), meaning the total control bit for columns 1-3 is "010". Figure 3 In this example, because the control bit is "010", input port 1 will be routed to output port 3, and input port 3 will be routed to output port 1. Thus, it can be seen that by controlling the on / off state of each column of Banyan switches, the data transmission path can be flexibly adjusted. Specifically, as a preferred embodiment of the present invention, in the switch interconnection network, the Banyan switches of the network are controlled by a counter that increments every clock cycle, and each input port is periodically connected to various output ports, such as... Figure 3 As shown, if the control bits of the three Banyan switches increment sequentially from "000" to "111" each cycle, then input port 6 will be connected to output port 6, and then to ports 5, 8, 7, 2, 1, 4, 3, and so on. This periodic switching avoids continuous requests from a certain input port from always being routed to the same output port, ensuring the balance and fairness of port connections.

[0028] Furthermore, in one embodiment of the present invention, the block memory unit is composed of a single-port RAM or a dual-port RAM, and the total memory space is divided by an interleaved striping method.

[0029] Specifically, a block memory unit is mainly used to store data. Each block memory unit consists of a simple single-port RAM or a dual-port RAM. Each block RAM unit contains a unique segment of the total memory space. By dividing the address space without segmentation, each port can access any block memory unit. Furthermore, the total memory space is divided between block memory units using interleaved striped addresses.

[0030] like Figure 4 This illustration shows a schematic diagram of a block memory unit address mapping structure provided in an embodiment of the present invention. It is illustrated using three block memory units.

[0031] like Figure 4 Figure A illustrates a contiguous address allocation method, where the contiguous address space from 1 to N is allocated to block memory unit 1, the contiguous address space from N+1 to 2N is allocated to block memory unit 2, and the contiguous address space from 2N+1 to 3N is allocated to block memory unit 3. However, this method is prone to bottlenecks. If all processing elements start reading from the lowest address in memory unit 1 and continue reading sequentially in ascending order, all requests will be sent to memory unit 1, thus requiring multiple pauses.

[0032] like Figure 4 Figure B illustrates the interleaved striping address allocation method used in this invention. This method allocates memory to block memory unit 1 from the first address space (1), block memory unit 2 from the second address space (2), block memory unit 3 from the third address space (3), and so on, until block memory unit 1 is allocated to the (3n-2)th address space, block memory unit 2 is allocated to the (3n-1)th address space, and block memory unit 3 is allocated to the (3n)th address space. This interleaved memory address space reduces the likelihood of the aforementioned specific types of bottlenecks occurring.

[0033] In particular, in another embodiment of the present invention, if the block memory unit is constructed using dual-port RAM, multi-port memory is implemented by copying. For example... Figure 5 It illustrates a schematic diagram of a multi-port memory structure implemented with dual-port block RAM according to an embodiment of the present invention.

[0034] exist Figure 5 In this implementation, a shared two-port RAM is achieved by replicating the input switch interconnect network, the output switch interconnect network, the linked list FIFO, and the requeuing sequence. Figure 1 Compared to the single-port implementation of multi-port memory shown in the example, Figure 5 Using dual ports to implement multi-port memory can further reduce resources, increase throughput, and reduce latency.

[0035] It should be noted that, Figure 5The linked list FIFO and requeuing sequence are not shown in the figure. The main purpose is to illustrate how a dual-port RAM implements multi-port memory.

[0036] Furthermore, in one embodiment of the present invention, the reordering queue tracks the status of read response data in each queue entry through a one-bit array. The status includes "existing" and "in transit". The returned response data is stored in the corresponding queue position according to the request ID and the response data status is updated. The data at the head of the queue can only be output when the status is "existing" to ensure that the read response is output in the order of the request.

[0037] Specifically, each output port corresponds to a reordering queue, and each queue structure stores the read response data returned from the block memory unit by its corresponding output port. When a read request is issued from a port, the system assigns it a unique request ID. This ID directly corresponds to the storage slot in the reordering queue of its port. This ID is sent to the memory unit along with the request through the switch interconnection network. After the memory unit processes the read request, it returns the data and the attached request ID through the output switch interconnection network. The reordering queue writes the data to the corresponding storage slot in the queue according to the returned ID and updates the status bit of that slot from "in transit" to "existing". At the same time, the reordering queue is equipped with an output pointer that always points to the slot of the earliest request that is currently expected to be output, and continuously checks the status of the slot pointed to by the pointer. If the status is "existing", the data is immediately popped and sent to the output port, while the output pointer is incremented and the status of the slot is reset to "in transit". If the status is "in transit", the queue does not output and waits for the data to arrive.

[0038] like Figure 6 This document illustrates the working principle and flowchart of a reordering queue provided in an embodiment of the present invention. By tracing a sequence of read requests containing five consecutive addresses from 0 to 4 on port 0, where the data stored in block memory units from 0 to 4 are 5 to 9 respectively, and the assigned IDs are 0 to 4, and the addresses of the out-of-order read responses are 2, 0, 4, 1, and 3 respectively, the document clearly demonstrates how the port 0 reordering queue tracks message status and reorders read responses after a breakdown of 7 clock cycles. This allows readers to clearly understand the working principle of the reordering queue in ensuring the correct order of read responses.

[0039] like Figure 6 As shown, in the initial waiting state of the first clock cycle, since no response data has been read to the reorder queue, the data in the reorder queue is empty, the queue status is "in transit", the output pointer points to the position of the reorder queue with ID=0, and the reorder queue has no output data.

[0040] When the read response data of ID=2 arrives in the reordering queue during the second clock cycle, the queue status of ID=2 is updated to "existing". At the same time, the read response data 7 of ID=2 is inserted into the reordering queue position of ID=2. Since the output pointer points to the position of the reordering queue of ID=0 and the queue status of ID=0 is "in transit", the reordering queue still has no output data.

[0041] When the read response data with ID=0 arrives in the reordering queue during the third clock cycle, the queue status ID=0 is updated to "existing". At the same time, the read response data 5 with ID=0 is inserted into the reordering queue position with ID=0. Since the output pointer points to the position of the reordering queue with ID=0, and the queue status ID=0 has been updated to "existing", the data 5 at the ID=0 position of the reordering queue will be popped from the reordering sequence and output. Then the output pointer points to the position of the reordering queue with ID=1, and the queue status ID=0 is updated to "in transit" again.

[0042] When the read response data ID=4 arrives in the reordering queue in the fourth clock cycle, the queue status ID=4 is updated to "existing". At the same time, the read response data 9 ID=4 is inserted into the reordering queue position of ID=4. Since the output pointer points to the position of the reordering queue ID=1 and the queue status ID=1 is "in transit", no output data is output.

[0043] When the read response data with ID=1 arrives in the reordering queue during the fifth clock cycle, the queue status ID=1 is updated to "existing". Simultaneously, read response data 6 with ID=1 is inserted into the reordering queue position for ID=1. Since the output pointer points to the reordering queue position for ID=1, and the queue status ID=1 has already been updated to "existing", data 6 at position ID=1 in the reordering queue will be popped from the reordering sequence and output. Then, the output pointer points to the reordering queue position for ID=2, and the queue status ID=1 is updated to "in transit" again. Since the queue status ID=2 is already "existing", data 7 at position ID=2 in the reordering queue will also be popped from the reordering sequence and output. The output pointer points to the reordering queue position for ID=3, and the queue status ID=2 is updated to "in transit" again. Because the queue status ID=3 is "in transit", there will be no output.

[0044] When the read response data with ID=3 arrives in the reordering queue during the sixth clock cycle, the queue status ID=3 is updated to "existing". At the same time, the read response data 8 with ID=3 is inserted into the reordering queue position with ID=3. Since the output pointer points to the reordering queue position with ID=3 and the queue status ID=3 has been updated to "existing", the data 7 at the ID=3 position in the reordering queue will be popped from the reordering sequence and output. Then, the output pointer points to the reordering queue position with ID=4 and the queue status ID=3 is updated to "in transit" again. However, the queue status ID=4 is already "existing", so the data 9 at the ID=4 position in the reordering queue will also be popped from the reordering sequence and output. Then, the output pointer points to the reordering queue position with ID=0 and the queue status ID=4 is updated to "in transit" again.

[0045] At the end of the seventh clock cycle, since all read response data has been processed, the data in the reordering queue is empty, and the queue status is "in transit".

[0046] Through the above specific implementation methods, this invention realizes a hardware architecture for multi-port memory. This architecture effectively reduces hardware resource consumption through a linked list FIFO implemented in a shared RAM block and a simple switch interconnection network; it effectively reduces port access conflicts by using the linked list FIFO to buffer incoming requests and the dynamic routing of the switch interconnection network; it achieves flexible scalability by using the switch interconnection network and independent block memory unit interconnection; it ensures data consistency and correctness by sorting requests through a reordering queue; and it improves memory utilization efficiency and flexibility by performing segmented partitioning of the address space. Thus, it achieves efficient large-scale port access while effectively reducing resource consumption and improving memory access efficiency and parallel processing capabilities. It can be widely applied to application scenarios requiring a large number of ports, high concurrency access, and high throughput, such as high-performance computing, heterogeneous computing, and data center acceleration, and can ensure stable system operation under high load.

[0047] It should be noted that the above embodiments and accompanying drawings have provided a detailed description of the present invention. The above examples are merely preferred embodiments of the present invention and are only used to more clearly illustrate the system method and technical solution of the present invention. They should not be used to limit the scope of protection of the present invention. After reading the present invention, any person skilled in the art can make many possible changes and modifications, or equivalent changes, without departing from the technical solution of the present invention. This does not affect the substantive content of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall still fall within the protection scope defined by the appended claims of the present invention.

Claims

1. A hardware architecture for multi-port memory, characterized in that, The hardware architecture includes: multiple input ports and multiple output ports, multiple linked FIFO lists, an input switch interconnection network, multiple block memory units, multiple reordering queues, and an output switch interconnection network; wherein, Multiple linked lists (FIFOs) are associated with and connected to the input ports to buffer port access requests and ensure that data is not lost according to the first-in-first-out principle. An input switch interconnection network, whose input end is connected to multiple linked FIFO lists and whose output end is connected to multiple block memory units, is used to realize dynamic routing between port requests and block memory units; Multiple block memory units are used to store data. The address space is divided in a non-segmented manner, and each port can access any block memory unit. The output switch interconnection network has its input end connected to multiple block memory units and its output end connected to multiple reordering queues, which is used to realize dynamic routing of read response data from block memory units; Multiple reordering queues are connected to the output ports one by one, and are used to sort the memory read response data to ensure that the read data is output in the correct order.

2. The hardware architecture for a multi-port memory according to claim 1, characterized in that, The multiple input ports and multiple output ports include multiple write ports and multiple read ports. The input ports correspond to the access request input and data input of the write port and the access request input of the read port, and the output ports correspond to the data output read by the read port, which are used to interact with external processing units.

3. The hardware architecture for a multi-port memory according to claim 1, characterized in that, The linked list FIFO is implemented based on shared RAM blocks. It uses a linked list structure to manage the request data of each port and uses a free pointer to uniformly manage the allocation and reclamation of free storage space in the shared RAM blocks. The depth of the linked list FIFO is greater than the number of input ports.

4. The hardware architecture for a multi-port memory according to claim 1, characterized in that, Both the input switch interconnection network and the output switch interconnection network are interconnection networks composed of multi-level Banyan switches. The switching status of each level of Banyan switch is dynamically controlled by a counter that increments every cycle to achieve balanced connection between the input port and the output port.

5. The hardware architecture for a multi-port memory according to claim 1, characterized in that, The block memory unit consists of a single-port RAM or a dual-port RAM, and the total memory space is divided by an interleaved striping method.

6. The hardware architecture for a multi-port memory according to claim 1, characterized in that, The reordering queue tracks the status of read response data in each queue entry using a one-bit array. The status includes "existing" and "in transit". The returned response data is stored in the corresponding queue position according to the request ID and the response data status is updated. The data at the head of the queue can only be output when its status is "existing" to ensure that read responses are output in the order of requests.

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