Low-power-consumption reinforcement module capable of controlling clock edge time

Abstract

The invention relates to a low-power-consumption reinforcement module capable of controlling clock edge time. The module comprises a clock gating circuit, a reinforcement unit and a clock and power supply module, in the clock gating circuit, the substrates of the two PMOS transistors are connected with a variable direct-current power supply, so that the function of controlling the clock edge time is realized; the reinforcing unit stores synchronous data after clock gating at nodes X0 to X3 through a bistable latch module by adopting a cross-coupled CMOS bistable structure, and inputs the data to the nodes X0 to X3 through an input control module by adopting an input path; the voltage VDD is set to be 1V in the clock and power supply module, so that the overall power consumption is reduced, and the energy is saved; the module has the function of resisting six-node overturning, and is more stable and higher in safety.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and relates to a low-power reinforced module with controllable clock edge time. BACKGROUND

[0002] Polarity reinforcement technology, also known as anti-radiation reinforcement or single particle effect reinforcement technology, aims to improve the reliability and stability of integrated circuits in a radiation environment or under high-energy particle bombardment. Polarity reinforcement technology is mainly applied to fields with extremely high reliability requirements, such as aerospace, commercial flights in high-altitude regions, medical electronics, high-reliability industries, and automobiles.

[0003] When high-energy particles (such as protons and heavy ions in space, or alpha particles and neutrons on the ground) penetrate a semiconductor chip, a short-lived, local electron-hole pair is generated in the silicon material through ionization. If this charge packet is collected by a sensitive circuit node, the following consequences may occur: (1) Soft error: the logic state of the circuit is unexpectedly flipped (such as 0 to 1 or 1 to 0), but the hardware itself is not permanently damaged. This is the most common single particle effect. (2) Latch-up: triggering a parasitic silicon controlled rectifier structure, causing a low resistance path between the power supply and the ground, causing a large current, which may burn out the chip. (3) Gate oxide breakdown: high-energy particles directly cause permanent damage to the ultra-thin gate oxide layer. Polarity reinforcement technology is designed to suppress these effects.

[0004] In circuit design, NMOS or PMOS transistors can be used to completely surround the node, so that when the node is bombarded by particles, the voltage of the node will only change in a single direction. This transistor characteristic is called polarity. Specifically, after using all NMOS transistors to surround the node, the voltage of the node will only jump to a low level (the logic value changes from 1 to 0), and will not jump to a high level (the logic value changes from 0 to 1). Similarly, after using all PMOS transistors to surround the node, the voltage of the node will only jump to a high level (the logic value changes from 0 to 1), and will not jump to a low level (the logic value changes from 1 to 0). Therefore, by using this characteristic, the design idea of placing the node in a state of being completely surrounded by a certain type of transistor is called polarity reinforcement technology.

[0005] In order to weaken the sensitivity of PMOS transistor, the field of anti-radiation reinforcement technology has been widely studied, and some reinforcement technologies have been developed, and the commonly used one is shallow trench isolation (STI) technology, which is a commonly used transistor isolation technology used to reduce interference and crosstalk between transistors. The STI technology can help to reduce the degree of influence of PMOS transistor in the radiation environment, thereby improving its anti-radiation capability. In the circuit design, the source isolation layout reinforcement mode combined with the circuit design and isolation technology can effectively reduce the drain voltage of the sensitive PMOS transistor and reduce the influence of single particle effect.

[0006] However, the existing SEI reinforcement module designed by using polarity reinforcement technology has the following shortcomings: (1) As shown in Figure 1 When the input signal of X1 changes from low level to high level, the voltage of X1 does not change to VDD (power voltage) (1.2V), but rises to about 0.81V quickly, and then continues to rise at a very slow speed, which will cause logic level confusion and misjudgment, sharp decrease of noise margin, and increase of static power consumption.

[0007] (2) The clock edge time is uncontrollable, and the clock edge of the module almost depends on the clock edge time of CLK (clock) and D (input). As can be seen from Figure 1 , the clock edge time of the SEI module is very small and almost uncontrollable, which will cause overshoot and undershoot, ground bounce and power supply noise, electromagnetic compatibility problem, and more sensitive to crosstalk. SUMMARY

[0008] In view of the problems existing in the above-mentioned traditional method, the present application provides a low-power reinforcement module with controllable clock edge time.

[0009] In order to achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions: On the one hand, a low-power reinforcement module with controllable clock edge time is provided, which comprises: A clock gating circuit is used to transmit input data D and negative input data DN to nodes X1 and X2 through two PMOS tubes, and transmit input data D and negative input data DN to nodes X3 and X0 through two NMOS tubes.

[0010] A reinforcement unit comprises a bistable latch module and an input control module, the bistable latch module is used to store the synchronous data after clock gating in nodes X0 to X3 by adopting a cross-coupled CMOS bistable structure, and the input control module is used to receive the synchronous data after clock gating through nodes X0 to X3, and drive the synchronous data after clock gating through an input path.

[0011] A clock and power module is used to provide clock CLK and inverse clock for the clock gating circuit, and to provide variable DC voltage for the substrate of two PMOS tubes in the clock gating circuit to adjust clock edge time, and to provide working voltage for the low-power hardened module.

[0012] In one embodiment, the clock gating circuit includes two PMOS tubes P7 and P8, and two NMOS tubes N7 and N8.

[0013] The substrate of P7 and P8 is connected to the variable DC voltage output terminal VDD1 of the clock and power module, the gate of P7 and P8 is connected to the inverse clock output terminal of the clock and power module, the drain of P7 and P8 receives input data D and negative input data DN respectively, and the source of P7 and P8 is connected to node X1 and node X2 respectively.

[0014] The substrate of N7 and N8 is connected to ground GND, the gate of N7 and N8 is connected to the clock CLK output terminal of the clock and power module, the drain of N7 and N8 receives input data D and negative input data DN respectively, and the source of N7 and N8 is connected to node X3 and node X0 respectively.

[0015] In one embodiment, the bistable latch module includes two PMOS tubes P2 and P3, and four NMOS tubes N1, N2, N4, and N5.

[0016] The gate of N1 and the gate of N5 are connected, the gate of N2 and the gate of N4 are connected, the drain of N4 and the source of N1 are connected to node X1, the drain of N5 and the source of N2 are connected to node X2, and the source of N4 and N5 are connected to ground GND.

[0017] The drain of N1 and P2 is connected to node a, the gate of P2 is connected to node X0, the source of P2 and P3 is connected to VDD, the drain of N2 and P3 is connected to node b, the gate of P3 is connected to node X3, node a is connected to double exponential current source I1, and node b is connected to VSS and double exponential current source I2.

[0018] In one embodiment, the input control module includes four PMOS tubes P1, P4, P5, P6, and two NMOS tubes N3 and N6.

[0019] The source of P1 is connected to VDD, the gate of P1 and the gate of N3 are connected to node X1, the drain of P1 is connected to the source of P5, the gate of P5 is connected to node X3, the drain of P5 and N3 is connected to node X0, and the source of N3 is connected to ground GND.

[0020] The source of the P4 is connected with the VDD, the gate of the P4 and the gate of the N6 are connected with the node X1, the drain of the P4 is connected with the source of the P6, the gate of the P6 is connected with the node X0, the drain of the P6 and the drain of the N6 are connected with the node X3, and the source of the N6 is connected with the ground GND.

[0021] In one embodiment, the clock and power module comprises a clock CLK source, an inverted clock source, a direct current power source and a variable direct current power source.

[0022] The output ends of the clock CLK source and the inverted clock source are connected with the clock gating circuit.

[0023] The direct current power source is used to provide working voltage for the low-power rugged module, and the output voltage of the direct current power source is 1V.

[0024] The output end of the variable direct current power source is connected with the substrate of the PMOS tube in the clock gating circuit.

[0025] One of the above technical solutions has the following advantages and beneficial effects: The above low-power rugged module with controllable clock edge time comprises a clock gating circuit, a rugged unit and a clock and power module. The substrates of two PMOS tubes in the clock gating circuit are connected with the variable direct current power source to realize the controllable function of the clock edge time. The rugged unit uses the cross-coupled CMOS bistable structure of the bistable latch module to store the synchronous data after the clock gating in the nodes X0 to X3, and uses the input path of the input control module to input the data to the nodes X0 to X3. In the clock and power module, the voltage VDD is set to 1V to reduce the overall power consumption and save energy. The module has the function of resisting six-node flipping, is more stable and has higher safety. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1 The working curve diagram of the SEI rugged module in the prior art; Figure 2 The principle diagram of the low-power rugged module with controllable clock edge time in one embodiment; Figure 3 The simulation result diagram of the Cadence software in one embodiment; Figure 4Fig. 4 is a schematic diagram of the impact on clock edge for one embodiment when VDD1 = 0.4V; Figure 5 Fig. 5 is a schematic diagram of the impact on clock edge for one embodiment when VDD1 = 0.6V; Figure 6 Fig. 6 is a schematic diagram of the impact on clock edge for one embodiment when VDD1 = 0.8V; Figure 7 Fig. 7 is a Monte Carlo simulation waveform diagram of six-node flipping for one embodiment. DETAILED DESCRIPTION

[0028] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0030] It should be noted that a reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. One of ordinary skill in the art can understand that the embodiments described herein can be combined with one another. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, as well as all possible combinations of the items, and includes these combinations.

[0031] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0032] In one embodiment, as shown in Fig. 1, a low-power consumption hardened module with controllable clock edge time is provided, comprising: Figure 2 a clock gating circuit 10 for transmitting input data D and negative input data DN to node X1 and node X2 through two PMOS tubes, and transmitting input data D and negative input data DN to node X3 and node X0 through two NMOS tubes. Specifically, the MOS tubes in the clock gating circuit are transmission tubes, responsible for transmitting input data D and negative input data DN to nodes X0 to X3.

[0033]

[0034] ​The input data D and the negative input data DN are inversely related, that is, when D is high, DN is low, and when D is low, DN is high.

[0035] The reinforcing unit 20 comprises a bistable latch module and an input control module. The bistable latch module is used to store the clock-gated synchronous data at nodes X0 to X3 in a cross-coupled CMOS bistable structure. The input control module is used to receive the clock-gated synchronous data through the nodes X0 to X3 and drive the clock-gated synchronous data through an input path.

[0036] Specifically, in the reinforcing unit, the nodes X1 and X2 adopt N-type polarity reinforcing technology, and the nodes X0 and X3 adopt source isolation technology of PMOS transistor stacking for reinforcement. When CLK is high, Figure 2 The transmission tubes P7, P8, N7 and N8 of the nodes X0 to X3 are open, and the input data D and the negative input data DN write data into the storage unit through the transmission tubes to store the signals to the nodes X0 and X3. When CLK is low, the transmission tubes are closed, the storage nodes (X0, X3) maintain their original values, and the data is retained in the SEI module through a feedback loop (composed of two cross-coupled inverters P2, N4, P3 and N5).

[0037] The anti-radiation working principle of the reinforcing unit is as follows: when the node X1 is bombarded by heavy ions, the logic value of the node voltage changes from 1 to 0. At this time, the PMOS transistor P1 is open, and the NMOS transistor N3 is closed. However, since the PMOS transistor P5 is always in a closed state, the node X0 is in a high resistance state, so the voltage of the node X0 always remains in a low level state and does not change. The nodes X2 and X3 are not affected and remain in the original state. The pull-up path (P2 and N1) of the node X1 is open, and the pull-down path (N4) is closed. Finally, the node X1 recovers to the initial high level under the pull-up action of P2 and N1; the other nodes are the same.

[0038] The clock and power module 30 is used to provide the clock CLK and the inverted clock for the clock gating circuit, and is also used to provide a variable DC voltage for the substrates of two PMOS tubes in the clock gating circuit to adjust the clock edge time, and is also used to provide an operating voltage for the low-power reinforcing module.

[0039] Specifically, the clock and power module adds a variable DC voltage source VDD1 as a variable DC power source connected to the substrate voltage of the PMOS tube transmitting signals to the nodes X1 and X2, which is responsible for adjusting the clock edge time; the added inverted clock is the inversion of the clock CLK, that is, when CLK is high, it is low.

[0040] Figure 1 The clock and power module provides a clock CLK, an inverted clock , double exponential current sources I1 and I2 (for detecting whether the node self-inversion can be achieved), a direct current source VDD, and a variable direct current source VDD1.

[0041] The low-power reinforcement module of controllable clock edge time includes a clock gating circuit, a reinforcement unit, and a clock and power module. In the clock gating circuit, the substrates of two PMOS tubes are connected to the variable direct current source, achieving the controllable function of clock edge time. The reinforcement unit stores the synchronous data after clock gating in nodes X0 to X3 by using the cross-coupled CMOS bistable structure of the bistable latch module, and inputs the data to the nodes X0 to X3 by using the input path of the input control module. In the clock and power module, the voltage VDD is set to 1V, reducing the overall power consumption and saving energy. The module has the function of resisting six-node flipping, is more stable, and has higher safety.

[0042] In one embodiment, the clock gating circuit 10 includes two PMOS tubes P7 and P8, and two NMOS tubes N7 and N8.

[0043] The substrates of P7 and P8 are connected to the variable direct current voltage output terminal VDD1 of the clock and power module, the gates of P7 and P8 are connected to the inverted clock output terminal of the clock and power module, the drains of P7 and P8 receive input data D and negative input data DN respectively, and the sources of P7 and P8 are connected to nodes X1 and X2 respectively.

[0044] The substrates of N7 and N8 are connected to the ground GND, the gates of N7 and N8 are connected to the clock CLK output terminal of the clock and power module, the drains of N7 and N8 receive input data D and negative input data DN respectively, and the sources of N7 and N8 are connected to nodes X3 and X0 respectively.

[0045] Specifically, the transmission gate of nodes X1 and X2 is changed to a PMOS tube, so that the voltage of X1 and X2 nodes can be smoothly raised to VDD when the level is raised.

[0046] The substrates of the two PMOS tubes are connected to the variable direct current source VDD1, achieving the controllable function of clock edge time.

[0047] In one embodiment, the bistable latch module includes two PMOS tubes P2 and P3, and four NMOS tubes N1, N2, N4, and N5.

[0048] The gate of N1 is connected with the gate of N5, the gate of N2 is connected with the gate of N4, the drain of N4 and the source of N1 are connected with node X1, the drain of N5 and the source of N2 are connected with node X2, and the source of N4 and N5 are connected with ground GND.

[0049] The drain of N1 and the drain of P2 are connected with node a, the gate of P2 is connected with node X0, the source of P2 and P3 are connected with VDD, the drain of N2 and P3 are connected with node b, the gate of P3 is connected with node X3, node a is connected with double exponential current source I1, and node b is connected with VSS and double exponential current source I2.

[0050] In one embodiment, the input control module comprises four PMOS tubes P1, P4, P5 and P6, and two NMOS tubes N3 and N6.

[0051] The source of P1 is connected with VDD, the gate of P1 and the gate of N3 are connected with node X1, the drain of P1 is connected with the source of P5, the gate of P5 is connected with node X3, the drain of P5 and the drain of N3 are connected with node X0, and the source of N3 is connected with ground GND.

[0052] The source of P4 is connected with VDD, the gate of P4 and the gate of N6 are connected with node X1, the drain of P4 is connected with the source of P6, the gate of P6 is connected with node X0, the drain of P6 and the drain of N6 are connected with node X3, and the source of N6 is connected with ground GND.

[0053] In one embodiment, the clock and power supply module comprises a clock CLK source, an inverted clock source, a direct current power supply and a variable direct current power supply.

[0054] The output ends of the clock CLK source and the inverted clock source are connected with the clock gating circuit.

[0055] The direct current power supply is used to provide working voltage for the low-power rugged module, and the output voltage of the direct current power supply is 1V. Specifically, VDD is changed to 1V, further reducing the overall power consumption and saving energy.

[0056] The output end of the variable direct current power supply is connected with the substrate of the PMOS tube in the clock gating circuit.

[0057] In one verification embodiment, the low-power rugged module with controllable clock edge time shown in FIG. Figure 2 is simulated by Cadence software, and the simulation results (a node and b node in net36 and net015 respectively) of the Cadence software are as shown in FIG. Figure 2 Figure 3 ​As shown, it can be observed that the high level of nodes X1 and X2 can now reach a position very close to VDD, which greatly improves the noise margin and reduces the probability of level misjudgment and static power consumption.

[0058] Compared to existing hardened modules, this invention has the advantages of greater noise tolerance and lower probability of level misjudgment. Specifically, when nodes X1 and X2 in the circuit module transition from low to high level, the voltage can smoothly rise to VDD, instead of rising to 0.7VDD in a short time and then rising very slowly, which greatly improves noise tolerance and reduces the probability of misjudgment.

[0059] The effect of changing the substrate voltage VDD1 on the clock edge is as follows: Figure 4 to Figure 6 As shown (the rising and falling edges of CLK and D inputs are both 1ns). Figure 4 This is a schematic diagram illustrating the effect of VDD1=0.4V on the clock edge. Figure 5 This is a schematic diagram illustrating the effect of VDD1=0.6V on the clock edge. Figure 6 This is a schematic diagram illustrating the effect of VDD1 = 0.8V on the clock edge; from Figure 4 to Figure 6 It can be seen that: when VDD1=0.4V, the fall time is 1.17ns; when VDD1=0.6V, the fall time is 1.288ns; and when VDD1=0.8V, the fall time is 1.564ns. Compared with the original ruggedized module, this invention has the advantages of higher device safety, lower noise, and better electromagnetic compatibility. Specifically, by adjusting the substrate voltage of the transmission gates P7 and P8 of nodes X1 and X2, the rise / fall time of the circuit signal can be increased or decreased when the subthreshold current of the device is negligible, thereby improving circuit safety.

[0060] The low-power ruggedized module with controllable clock edge timing proposed in this application has the advantage of resisting six-node flips, compared to the original module's resistance to four-node flips, thus offering greater robustness. Figure 7 Flip the six nodes (node ​​X0 to node X3, and...) Figure 2 The Monte Carlo simulation waveforms of the two nodes a and b) connecting the double exponential current source are shown in the figure. Figure 7 As can be seen, in all 100 simulations, all nodes successfully returned to their original levels, which proves that this module can withstand six-node flips and is more secure.

[0061] The low-power hardened module with controllable clock edge timing proposed in this application has a VDD of 1V, which is 83.33% of the original VDD, while the dynamic power consumption in digital circuits is... The static power consumption is proportional to VDD, and the change of the substrate voltage is negligible to the change of the subthreshold leakage current of the circuit module, and the improved circuit module has a power consumption reduction of 17% to 30%.

[0062] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0063] The above embodiments only express several implementation manners of the present application, and the description is specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be pointed out that, for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application.

Claims

1. A low power hardened module of controllable clock edge time, characterized in that, The application relates to a low-power consumption and reinforced clock gating circuit. The clock gating circuit comprises two PMOS tubes P7 and P8 and two NMOS tubes N7 and N8. The substrates of the PMOS tubes P7 and P8 are connected with a variable DC voltage output terminal VDD1 of a clock and power module, the gates of the PMOS tubes P7 and P8 are connected with an inverse clock output terminal of the clock and power module, the drains of the PMOS tubes P7 and P8 receive input data D and negative input data DN respectively, and the sources of the PMOS tubes P7 and P8 are connected with a node X1 and a node X2 respectively. The substrates of the NMOS tubes N7 and N8 are connected with a ground GND, the gates of the NMOS tubes N7 and N8 are connected with a clock CLK output terminal of the clock and power module, the drains of the NMOS tubes N7 and N8 receive the input data D and the negative input data DN respectively, and the sources of the NMOS tubes N7 and N8 are connected with a node X3 and a node X0 respectively.

2. The low-power clock edge time hardening module of claim 1, wherein, The bistable latch module comprises two PMOS tubes P2 and P3 and four NMOS tubes N1, N2, N4 and N5. The gate of the NMOS tube N1 is connected with the gate of the NMOS tube N5, the gate of the NMOS tube N2 is connected with the gate of the NMOS tube N4, the drain of the NMOS tube N4 is connected with the source of the NMOS tube N1, the drain of the NMOS tube N5 is connected with the source of the NMOS tube N2, and the sources of the NMOS tubes N4 and N5 are connected with the ground GND. The drain of the NMOS tube N1 is connected with the drain of the PMOS tube P2, the gate of the PMOS tube P2 is connected with the node X0, the sources of the PMOS tubes P2 and P3 are connected with VDD, the drain of the NMOS tube N2 is connected with the drain of the PMOS tube P3, the gate of the PMOS tube P3 is connected with the node X3, the node a is connected with a double exponential current source I1, and the node b is connected with VSS and a double exponential current source I2.

3. The low power clock edge time hardening module of claim 1, wherein, The input control module comprises four PMOS tubes P1, P4, P5 and P6 and two NMOS tubes N3 and N6. The source of the PMOS tube P1 is connected with VDD, the gate of the PMOS tube P1 and the gate of the NMOS tube N3 are connected with the node X1, the drain of the PMOS tube P1 is connected with the source of the PMOS tube P5, the gate of the PMOS tube P5 is connected with the node X3, the drain of the PMOS tube P5 and the drain of the NMOS tube N3 are connected with the node X0, and the source of the NMOS tube N3 is connected with the ground GND. ​ 4. The low power clock edge time hardening module of claim 1, wherein, ​ ​ The source of P4 is connected with VDD, the gate of P4 and the gate of N6 are connected with node X1, the drain of P4 is connected with the source of P6, the gate of P6 is connected with node X0, the drain of P6 and the drain of N6 are connected with node X3, and the source of N6 is connected with ground GND.

5. The low power consumption clock edge time hardening module of claim 1, wherein, The clock and power module comprises a clock source, an inverted clock source, a direct current power supply and a variable direct current power supply. The output ends of the clock source and the inverted clock source are connected with the clock gating circuit. The direct current power supply is used for providing working voltage for the low-power ruggedized module, and the output voltage of the direct current power supply is 1V. The output end of the variable direct current power supply is connected with the substrate of the PMOS tube in the clock gating circuit.

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