Low-power-consumption low-temperature-drift high-frequency oscillator circuit capable of realizing internal frequency division

Abstract

The invention discloses a low-power-consumption low-temperature-drift high-frequency oscillator circuit capable of internally dividing frequency, and relates to the technical field of oscillators. The oscillator circuit comprises a digital power supply voltage generating circuit, a reference voltage generating circuit and an RC oscillator, the digital power supply voltage generating circuit is used for generating digital power supply voltage VDDD and inputting the digital power supply voltage VDDD to the RC oscillator, and the reference voltage generating circuit is used for outputting reference voltage VREF and bias current IB, the reference voltage VREF and the bias current IB are input to the RC oscillator, and the RC oscillator is used for outputting frequency under the action of the digital power supply voltage generating circuit and the reference voltage generating circuit. The oscillator circuit can accurately carry out frequency division, and the output frequency is stable.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of oscillator, in particular to a low-power low-temperature drift high-frequency oscillator circuit capable of internal frequency division. BACKGROUND

[0002] At present, the frequency output by the RC oscillator in the analog circuit is low, and many use the method of increasing current to speed up the frequency output of the oscillator, thereby increasing the power consumption of the module. If frequency division is needed, most of them need to connect a frequency divider circuit at the output end, making the overall circuit too complex and cumbersome. The current with temperature coefficient also affects the overall frequency, and the duty cycle of the output frequency changes.

[0003] The existing common RC oscillator increases the bias current, thereby increasing the branch current, resulting in large power consumption, which is not suitable for application in low-power scenarios. By using the method of charging the capacitor, a large area of layout is occupied. If a divided frequency signal is needed, a frequency divider circuit needs to be connected subsequently, and the overall circuit is complex. Without the addition of a temperature drift adjustment circuit, temperature has a great influence on the frequency output, so the RC oscillator circuit in the prior art mainly has the following shortcomings:

[0004] First, it cannot be divided by internal circuit to obtain the output frequency after frequency division. Second, it occupies a large amount of resources in power consumption, making the overall system power consumption large. Third, by using the method of charging the capacitor, the frequency cannot be very high, and a large area of layout is occupied. Fourth, the temperature coefficient affects the current, thereby affecting the output frequency. Fifth, the duty cycle of the output frequency changes and cannot be stable at 50%. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a low-power low-temperature drift high-frequency oscillator circuit capable of accurate frequency division and stable output frequency.

[0006] To solve the above technical problems, the technical solution adopted by the present application is: a low-power low-temperature drift high-frequency oscillator circuit capable of internal frequency division, the oscillator circuit comprising a digital power supply voltage generating circuit, a reference voltage generating circuit and an RC oscillator, the digital power supply voltage generating circuit being used to generate a digital power supply voltage VDDD and input the digital power supply voltage VDDD to the RC oscillator, the reference voltage generating circuit being used to output a reference voltage VREF and a bias current IB and input the reference voltage VREF and the bias current IB to the RC oscillator, and the RC oscillator being used to output a frequency under the action of the digital power supply voltage generating circuit and the reference voltage generating circuit.

[0007] The further technical scheme is characterized in that: the RC oscillator comprises a frequency division circuit, an OSC symmetric range adjusting circuit and an RS flip-flop circuit, an output end of the frequency division circuit is connected with an input end of the OSC symmetric range adjusting circuit, an output end of the OSC symmetric range adjusting circuit is connected with an input end of the RS flip-flop circuit, and an output of the RS flip-flop circuit outputs a frequency through a buffer.

[0008] The further technical scheme is characterized in that: the frequency division circuit comprises an operational amplifier U1, a non-inverting input end of the U1 is connected with a reference voltage VREF, a bias current input end of the U1 is connected with a bias current IB, an output end of the U1 is connected with a gate of a PMOS tube MP3, a source of the MP3 is connected with a digital power supply voltage VDDD, a drain of the MP3 is divided into two paths, a first path is connected with an inverting input end of the U1, and a second path is connected with a drain of an NMOS tube MN5 through a resistor R8 and a resistor R1 in sequence, a source of the MN5 is connected with the ground, and a gate of the MN5 is connected with the digital power supply voltage VDDD.

[0009] A drain of an NMOS tube MN6 is connected with a joint between the resistor R1 and a resistor R2, a source of the MN6 is connected with the drain of the MN5, and a gate of the MN6 is a selection port of whether to be turned on or not; a drain of an NMOS tube MN7 is connected with a joint between the resistor R2 and a resistor R3, a source of the MN7 is connected with the drain of the MN5, and a gate of the MN7 is a selection port of whether to be turned on or not; a drain of an NMOS tube MN8 is connected with a joint between the resistor R3 and a resistor R4, a source of the MN8 is connected with the drain of the MN5, and a gate of the MN8 is a selection port of whether to be turned on or not; a drain of an NMOS tube MN9 is connected with a joint between the resistor R4 and a resistor R5, a source of the MN9 is connected with the drain of the MN5, and a gate of the MN9 is a selection port of whether to be turned on or not; a drain of an NMOS tube MN10 is connected with a joint between the resistor R5 and a resistor R6, a source of the MN10 is connected with the drain of the MN5, and a gate of the MN10 is a selection port of whether to be turned on or not; a drain of an NMOS tube MN11 is connected with a joint between the resistor R6 and a resistor R7, a source of the MN11 is connected with the drain of the MN5, and a gate of the MN11 is a selection port of whether to be turned on or not; and a drain of an NMOS tube MN12 is connected with a joint between the resistor R7 and a resistor R8, a source of the MN12 is connected with the drain of the MN5, and a gate of the MN12 is a selection port of whether to be turned on or not.

[0010] Further technical solutions are as follows: the OSC symmetrical range adjusting circuit comprises two symmetrically arranged adjusting circuit units, the first adjusting circuit unit comprises B PMOS tubes, the sources of the B PMOS tubes are connected with a digital power supply voltage VDDD, and the gates of the B PMOS tubes are connected with a control voltage Vbp; the drains of the B PMOS tubes are connected together and then divided into three paths, the first path is connected with the gate of an NMOS tube MN14, the second path is connected with a capacitor array, and the third path is connected with the drain of an NMOS tube MN13; the source of the MN13 is grounded, the gate of the MN13 is connected with a control signal CLK1 output by an RS flip-flop circuit; the source of the MN14 is grounded, the drain of the MN14 is connected with the drain of a PMOS tube MP4 to serve as an OUT1 output end of the first adjusting circuit unit, the source of the MP4 is connected with the VDDD, and the gate of the MP4 is connected with the control voltage Vbp; the control signal of the second adjusting circuit unit is a control signal CLK2 output by the RS flip-flop circuit, and the output of the second adjusting circuit unit is OUT2.

[0011] The beneficial effects of the above technical solutions are as follows: the oscillator circuit described in the application can be adjusted by resistance inside the circuit, so that the output of the overall RC oscillator is divided, and an external frequency divider is not needed. By combining the resistances of the positive and negative temperature coefficients, a low-temperature-drift output frequency can be obtained, and the influence of temperature on the output of the oscillator is reduced. The output frequency after division can be adjusted in a small range to meet the required accurate frequency in design. By using the parasitic capacitance of the MOS tube itself, the output frequency can be improved to obtain a higher-frequency oscillator output. The use of branch current is further reduced, so that the overall power consumption is low, which is suitable for low-power consumption scene applications, and the use area of the capacitor can be reduced. Through the symmetric structure of the circuit, two symmetric structures work for half a cycle, so that the duty cycle of the final output frequency can be stabilized at 50%. BRIEF DESCRIPTION OF DRAWINGS

[0012] The application will be described in further detail below with reference to the drawings and specific embodiments.

[0013] Figure 1 is a principle block diagram of the oscillator circuit described in the embodiment of the application;

[0014] Figure 2 is a principle block diagram of the RC oscillator in the oscillator circuit described in the embodiment of the application;

[0015] Figure 3 is a principle diagram of the frequency division circuit in the RC oscillator described in the embodiment of the application;

[0016] Figure 4 is a principle diagram of the internal circuit of resistors R1-R8 in the frequency division circuit described in the embodiment of the application;

[0017] Figure 5 is the schematic diagram of the OSC symmetry range adjusting circuit in the frequency dividing circuit according to the embodiment of the present application;

[0018] Figure 6 is the schematic diagram of the RS flip-flop circuit in the RC oscillator according to the embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0020] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present application. However, the present application can be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the concept of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0021] As shown in Figure 1 , the embodiment of the present application discloses a low-power low-temperature drift high-frequency oscillator circuit capable of internal frequency division. The oscillator circuit comprises a digital power supply voltage generating circuit, a reference voltage generating circuit and an RC oscillator. The digital power supply voltage generating circuit is used to generate a digital power supply voltage VDDD and input the digital power supply voltage VDDD to the RC oscillator. The reference voltage generating circuit is used to output a reference voltage VREF and a bias current IB and input the reference voltage VREF and the bias current IB to the RC oscillator. The RC oscillator is used to output a frequency under the action of the digital power supply voltage generating circuit and the reference voltage generating circuit.

[0022] Figure 1 In the block diagram, VDDD_LDO is a digital power supply voltage generating circuit (low-voltage linear voltage stabilizing circuit) outputting a digital power supply voltage VDDD. The reference voltage generating circuit outputs VREF to provide a reference voltage for the RC oscillator circuit. IB is outputted to provide a bias current for the RC oscillator. The whole connection is that the digital power supply voltage generating circuit generates a digital power supply voltage VDDD connected to the RC oscillator, the reference voltage generating circuit generates a reference voltage VREF and a bias current IB connected to the RC oscillator, and the RC oscillator outputs OSC_OUT, which is the output frequency of the whole RC oscillator.

[0023] As shown in Figure 2The shown is the component principle block diagram of RC oscillator, including frequency division circuit (including low temperature drift implementation circuit), OSC symmetry range adjustment circuit and RS trigger circuit. The frequency division circuit output is connected with the OSC symmetry range adjustment circuit, the output of which is connected with the RS trigger circuit, and the output of the RS trigger circuit is output through a buffer as OSC_OUT, that is, the final output frequency of RC oscillator.

[0024] As Figure 3 The shown is the circuit principle diagram of frequency division circuit, which includes operational amplifier U1, the non-inverting input end of which is connected with reference voltage VREF, the bias current input end of which is connected with bias current IB, the output end of which is connected with the gate of PMOS tube MP3, the source of which is connected with digital power supply voltage VDDD, and the drain of which is divided into two paths, the first path of which is connected with the inverting input end of U1, and the second path of which is connected with the drain of NMOS tube MN5 through resistance R8-resistance R1 in sequence, the source of which is connected with ground, and the gate of which is connected with digital power supply voltage VDDD.

[0025] The drain of NMOS tube MN6 is connected with the joint between resistance R1 and resistance R2, the source of which is connected with the drain of MN5, and the gate of which is a selection port of whether to be conducted; the drain of NMOS tube MN7 is connected with the joint between resistance R2 and resistance R3, the source of which is connected with the drain of MN5, and the gate of which is a selection port of whether to be conducted; the drain of NMOS tube MN8 is connected with the joint between resistance R3 and resistance R4, the source of which is connected with the drain of MN5, and the gate of which is a selection port of whether to be conducted; the drain of NMOS tube MN9 is connected with the joint between resistance R4 and resistance R5, the source of which is connected with the drain of MN5, and the gate of which is a selection port of whether to be conducted; the drain of NMOS tube MN10 is connected with the joint between resistance R5 and resistance R6, the source of which is connected with the drain of MN5, and the gate of which is a selection port of whether to be conducted; the drain of NMOS tube MN11 is connected with the joint between resistance R6 and resistance R7, the source of which is connected with the drain of MN5, and the gate of which is a selection port of whether to be conducted; the drain of NMOS tube MN12 is connected with the joint between resistance R7 and resistance R8, the source of which is connected with the drain of MN5, and the gate of which is a selection port of whether to be conducted.

[0026] Wherein IB is the output of the reference circuit to the offset current of the operational amplifier. VREF is the output of the reference circuit to the reference voltage of the operational amplifier, connected to the non-inverting input of the operational amplifier U1. Vbp is the output voltage connected to the operational amplifier U1, VF is the feedback voltage connected to the inverting input of the operational amplifier U1. S1-S7 is the selection port of whether NMOS MN6-MN12 is turned on. The resistance values of resistors R1-R8 are equal. The frequency division process is: when S1-S7 is high, NMOS MN6-MN12 is turned on, thereby changing the current size and the voltage Vbp size, thereby uniformly dividing the output frequency of the overall oscillator.

[0027] For example: when S7 is high, NMOS MN12 is turned on, and the overall oscillator output frequency is the default F. If S6 is high, NMOS MN11 is turned on, and NMOS MN6-MN10 and MN12 are turned off, resistors R1-R6 are short-circuited, and resistors R7-R8 are connected to the circuit. Because the size of each resistor is equal, the branch current becomes 1 / 2 of the original, so the oscillator output frequency is 1 / 2F. By analogy, the output frequency of the oscillator can be divided into F, 1 / 2F, 1 / 3F, 1 / 4F, 1 / 5F, 1 / 6F, 1 / 7F, 1 / 8F. Figure 3 For example, the frequency can be divided into any required frequency by the frequency division formula.

[0028] The frequency division formula is:

[0029]

[0030] Where F out is the output frequency of the overall frequency division circuit, F is the default frequency, R 接入电路 is the resistance value connected to the circuit, and the figure shows that R1-R8 are connected to the circuit, and Ru represents the unit resistance value. The value of Ru is equal to any one of the resistance values of R1-R8, that is, the resistance values of R1-R8 are equal to Ru.

[0031] Figure 4 The low temperature drift implementation is shown, and R1-R8 are Figure 4 composed of N positive temperature coefficient resistors and M negative temperature coefficient resistors. By looking up the process file and simulation, the resistance value curve of different resistance types with temperature change can be obtained, and the temperature coefficient can be obtained. Then, after combination, the influence of temperature on resistance value can be offset by adding positive and negative temperature coefficients.

[0032] Assuming that the positive temperature coefficient is X and the negative temperature coefficient is -Y, the formula obtained is:

[0033] Temperature drift = X*N-Y*M;

[0034] Ultimately, by combining the results, the temperature drift is equal to 0, thus offsetting the effect of temperature.

[0035] like Figure 5 As shown, the OSC symmetrical range adjustment circuit includes two symmetrically arranged adjustment circuit units. The first adjustment circuit unit includes B PMOS transistors. The sources of the B PMOS transistors are connected to the digital power supply voltage VDDD, and the gates of the B PMOS transistors are connected to the control voltage Vbp. The drains of the B PMOS transistors are connected together and then divided into three paths: the first path is connected to the gate of NMOS transistor MN14, the second path is connected to the capacitor array, and the third path is connected to the drain of NMOS transistor MN13. The source of MN13 is grounded, and the gate of MN13 is connected to the control signal CLK1 output by the RS flip-flop circuit. The source of MN14 is grounded, and the drain of MN14 is connected to the drain of PMOS transistor MP4, serving as the OUT1 output terminal of the first adjustment circuit unit. The source of MP4 is connected to VDDD, and the gate of MP4 is connected to the control voltage Vbp. The control signal of the second adjustment circuit unit is the control signal CLK2 output by the RS flip-flop circuit, and the output of the second adjustment circuit unit is OUT2.

[0036] Figure 5 The OSC symmetrical range adjustment circuit shown is mainly used for small-range adjustment at a determined frequency after frequency division. For example, if the frequency division is determined to be 20MHz, it can be adjusted to a small range of 25MHz to 15MHz, allowing the output frequency to be more accurately selected as the frequency required by the circuit. There are two adjustment methods: 1. Adjusting the capacitor array through A selection signals; the more capacitors connected, the slower the frequency. This application is a high-frequency oscillator, mainly due to the utilization of the parasitic capacitance Cgg of the NMOS transistor MN14 itself. A small Cgg allows for a higher frequency, saves area in the layout, and reduces overall power consumption. 2. Adjustment can be achieved through B PMOS transistors; selecting the number of PMOS transistors connected adjusts the bias current, thus adjusting the output frequency range. According to the formula:

[0037]

[0038] Since R = V / I, the formula can be equivalent to:

[0039]

[0040] Therefore, by using the smaller NMOS transistors MN14 and MN14_2, a higher output frequency can be obtained. The frequency can be adjusted by changing the current and capacitor according to the formula.

[0041] Figure 5 For OSC range adjustment circuit,Figure 5 The two circuits are symmetrical. One output is OUT1, with NM13 control signal CLK1; the other output is OUT2, with NM13_2 control signal CLK2. The CLK1 and CLK2 ports are the outputs of RS flip-flops, as shown below. Figure 6 The schematic diagram of the RS flip-flop circuit shows that the NMOS (such as...) is selected by high and low levels. Figure 5 Whether MN13 and MN13_2 in the circuit are conducting.

[0042] For example, when CLK1 is high, NMOS transistor MN13 is turned on. Then, the output of OUT1, after passing through an RS flip-flop, results in CLK1 being low and CLK2 being high. Subsequently, NMOS transistor MN13_2 in the other half of the circuit is turned on. Then, the output of OUT2, after passing through an RS flip-flop, results in CLK2 being low and CLK1 being high, and then NMOS transistor MN13 is turned on. This continues, so for the final OSC output, half the cycle has CLK1 high and CLK2 low; the other half has CLK1 low and CLK2 high. The two symmetrical circuits work alternately, therefore the duty cycle of the OSC output is a stable 50%.

[0043] In summary, the oscillator circuit described in this application divides the output frequency by uniformly adjusting the current through resistors within the RC oscillator, and the range of each divided frequency can be adjusted. Utilizing the parasitic capacitance Cgg of the MOS itself as a charging capacitor increases the oscillator's output frequency without increasing the current, resulting in a smaller area and lower power consumption at the same frequency compared to existing technologies. The technique of canceling out the positive and negative temperature coefficients of the resistors reduces the impact of temperature on the oscillator's output frequency. The two-way symmetrical structure ensures a stable 50% duty cycle for the output frequency.

Claims

1. A low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division capability, characterized in that: The oscillator circuit includes a digital power supply voltage generation circuit, a reference voltage generation circuit, and an RC oscillator. The digital power supply voltage generation circuit generates a digital power supply voltage VDDD and inputs the digital power supply voltage VDDD to the RC oscillator. The reference voltage generation circuit outputs a reference voltage VREF and a bias current IB and inputs the reference voltage VREF and the bias current IB to the RC oscillator. The RC oscillator outputs a frequency under the action of the digital power supply voltage generation circuit and the reference voltage generation circuit.

2. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division as described in claim 1, characterized in that: The RC oscillator includes a frequency divider circuit, an OSC symmetrical range adjustment circuit, and an RS flip-flop circuit. The output of the frequency divider circuit is connected to the input of the OSC symmetrical range adjustment circuit, the output of the OSC symmetrical range adjustment circuit is connected to the input of the RS flip-flop circuit, and the output of the RS flip-flop circuit outputs the frequency through a buffer.

3. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division as described in claim 2, characterized in that: The frequency divider circuit includes an operational amplifier U1. The non-inverting input of U1 is connected to the reference voltage VREF, the bias current input of U1 is connected to the bias current IB, the output of U1 is connected to the gate of PMOS transistor MP3, the source of MP3 is connected to the digital power supply voltage VDDD, and the drain of MP3 is divided into two paths. The first path is connected to the inverting input of U1, and the second path is connected to the drain of NMOS transistor MN5 after passing through resistor R8 and resistor R1. The source of MN5 is grounded, and the gate of MN5 is connected to the digital power supply voltage VDDD. The drain of NMOS transistor MN6 is connected to the junction between resistors R1 and R2. The source of MN6 is connected to the drain of MN5. The gate of MN6 is the selection port for whether it is turned on. The drain of NMOS transistor MN7 is connected to the junction between resistors R2 and R3. The source of MN7 is connected to the drain of MN5. The gate of MN7 is the selection port for whether it is turned on. The drain of NMOS transistor MN8 is connected to the junction between resistors R3 and R4. The source of MN8 is connected to the drain of MN5. The gate of MN8 is the selection port for whether it is turned on. The drain of NMOS transistor MN9 is connected to the junction between resistors R4 and R5. The source of MN9 is connected to the drain of MN5. The drain of MN5 is connected as described above, and the gate of MN9 is the selection port for whether it is turned on or off; the drain of NMOS transistor MN10 is connected to the junction between resistors R5 and R6, the source of MN10 is connected to the drain of MN5, and the gate of MN10 is the selection port for whether it is turned on or off; the drain of NMOS transistor MN11 is connected to the junction between resistors R6 and R7, the source of MN11 is connected to the drain of MN5, and the gate of MN11 is the selection port for whether it is turned on or off; the drain of NMOS transistor MN12 is connected to the junction between resistors R7 and R8, the source of MN12 is connected to the drain of MN5, and the gate of MN12 is the selection port for whether it is turned on or off.

4. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division as described in claim 2, characterized in that: The frequency division formula of the frequency divider circuit is: Where F out The value represents the output frequency of the overall frequency divider circuit, where F is the default frequency and R is the value of the output frequency. 接入电路 The resistance value connected in the circuit is Ru, which represents the unit resistance value and is equal to any of the resistance values ​​of R1 to R8. That is, the resistance values ​​of R1 to R8 are all equal and equal to Ru.

5. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division as described in claim 3, characterized in that: The resistors R1-R8 comprise N positive temperature coefficient resistors and M negative temperature coefficient resistors connected in series.

6. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division capability as described in claim 5, characterized in that: The formula for calculating the temperature drift of resistors R1 and R8 is as follows: Temperature drift = X·NY·M; The positive temperature coefficient is X, and the negative temperature coefficient is -Y. Finally, by combining them, the temperature drift is equal to 0, thus offsetting the temperature effect.

7. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division capability as described in claim 2, characterized in that: The OSC symmetrical range adjustment circuit includes two symmetrically arranged adjustment circuit units. The first adjustment circuit unit includes B PMOS transistors. The sources of the B PMOS transistors are connected to the digital power supply voltage VDDD, and the gates of the B PMOS transistors are connected to the control voltage Vbp. The drains of the B PMOS transistors are connected together and then divided into three paths: the first path is connected to the gate of NMOS transistor MN14, the second path is connected to the capacitor array, and the third path is connected to the drain of NMOS transistor MN13. The source of MN13 is grounded, and the gate of MN13 is connected to the control signal CLK1 output by the RS flip-flop circuit. The source of MN14 is grounded, and the drain of MN14 is connected to the drain of PMOS transistor MP4, serving as the OUT1 output terminal of the first adjustment circuit unit. The source of MP4 is connected to VDDD, and the gate of MP4 is connected to the control voltage Vbp. The control signal of the second adjustment circuit unit is the control signal CLK2 output by the RS flip-flop circuit, and the output of the second adjustment circuit unit is OUT2.

8. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division as described in claim 7, characterized in that: The RS flip-flop circuit includes an RS flip-flop and a buffer U2. The output terminals OUT1 and OUT2 are respectively connected to the two input terminals of the RS flip-flop. One output terminal of the RS flip-flop outputs the control signal CLK2, and the other output terminal of the RS flip-flop is divided into two paths. The first path outputs the control signal CLK1, and the second path outputs a frequency with a stable duty cycle after passing through the buffer U2.

9. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division capability as described in claim 1, characterized in that: The duty cycle of the output frequency is 50%.

10. The low-power, low-temperature drift, high-frequency oscillator circuit with internal frequency division as described in claim 1, characterized in that: The frequency divider circuit includes a low temperature drift implementation circuit.

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