Multi-channel synchronous fast rising edge pulse generation device

Abstract

The invention belongs to the technical field of instrument application, and provides a multipath synchronous fast rising edge pulse generation device, which comprises an input trigger pulse conditioning circuit, an FPGA (Field Programmable Gate Array) module, a program control pulse delay circuit, a multipath fast pulse signal generation circuit based on an avalanche triode, a multipath clock fan-out buffer and a time-to-digital conversion circuit, the FPGA is combined with the program control pulse signal delay circuit to generate picosecond-level delay trigger pulses, the avalanche triode-based fast pulse signal generation circuit is triggered to generate fast rising edge pulse signals, high-amplitude pulse signal output is generated, and the driving capability is ensured; moreover, the time difference between the output synchronization pulse and the reference pulse is measured through the time-to-digital conversion circuit, and the trigger pulse delay of each avalanche transistor fast pulse signal generation circuit is adjusted through the FPGA and the program control pulse signal delay circuit, thereby achieving the synchronization adjustment of each pulse. The problem that the synchronism of multiple paths of pulses becomes poor due to changes of factors such as temperature and power supply voltage is effectively solved.

Description

Technical Field

[0001] This invention belongs to the field of instrumentation application technology, specifically providing a multi-channel synchronous fast rising edge pulse generation device. Background Technology

[0002] In multi-channel test / measurement applications, multiple instruments (such as oscilloscopes, RF signal generators, etc.) are typically combined into a measurement system. To ensure synchronization of tests and measurements, the instruments are generally set to external triggering mode, using multiple synchronous trigger pulse signals for device triggering. For this application context, a multi-channel synchronous fast-rising-edge pulse generator must have the following characteristics: First, the multiple pulses must be highly synchronized to ensure highly synchronized triggering times for multiple instruments, thus guaranteeing sampling accuracy. Second, the generated pulses must have a fast rise edge, which effectively reduces the impact of jitter on sampling accuracy. Third, to ensure signal integrity, the input impedance of the trigger port of general test and measurement instruments is typically 50Ω. Especially for special applications such as explosion testing, where instruments often need to be placed separately, the multi-channel synchronous pulse generator needs to be connected to the trigger port of the instrument via a long RF coaxial cable. Considering transmission loss, the multi-channel synchronous pulse generator must have strong driving capability or generate synchronous pulses with high amplitude.

[0003] For example, Chinese patent document CN105429613A discloses a synchronous multi-channel pulse generation system and method. The system includes: a communication module for receiving command frames and sending them to an FPGA module; an FPGA module for generating a synchronous pulse signal with a long delay time based on the command frame; and a CMOS analog delay module for generating a synchronous pulse signal with a short delay time based on the command frame. By adjusting the delay at the nanosecond level through the FPGA module and at the picosecond level through the CMOS analog delay module, synchronous pulses with high delay accuracy and a wide delay time range are generated, reducing the size and cost of the pulse generation system and greatly improving its versatility. However, the synchronous multi-channel pulse generation system designed in this patent document uses a comparator to output the final pulse signal, which typically cannot simultaneously achieve a fast rise time and a high pulse amplitude. That is, while a high-voltage comparator can output a high-amplitude pulse signal, such comparators have a low slew rate and cannot achieve a fast rise time, and using a high-speed operational amplifier cannot meet the application requirements of outputting a high-voltage amplitude pulse signal. In addition, the synchronization of each pulse signal in the system needs to be calibrated and set at the factory. However, the CMOS analog delay module used to adjust the pulse delay controls the pulse delay through the charging and discharging process of the charging capacitor. However, it is affected by the ambient temperature. When the temperature changes, the capacitance value will change accordingly, which will affect the delay time and cause the synchronization of multiple pulses to deteriorate.

[0004] For example, Chinese patent document CN119782235A discloses a multi-channel output pulse synchronization device with adjustable delay time, comprising: an FPGA, an SMA connector, a host computer, a serial communication terminal, and output channels. The FPGA acts as the central controller. One pulse trigger input is sent to the FPGA from the SMA connector, and the FPGA outputs to the output channels. The FPGA communicates with the host computer via the serial port to set the delay data in the registers of each channel. When the FPGA receives the input pulse signal, it reads the delay data stored in the register according to the program settings and outputs the pulse to the pins of each output channel. The minimum adjustable precision of this multi-channel output pulse synchronization device is 52ps, and the output delay time of each channel is independently adjustable, exhibiting strong controllability and adaptability. However, although this patent can generate multi-channel pulse signals with high synchronization through the FPGA, the multi-channel pulses are output through comparators or operational amplifiers, which still cannot simultaneously achieve fast rise time and high pulse amplitude. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-channel synchronous fast rising edge pulse generation device to solve the following technical problems: the output pulse of the existing multi-channel synchronous pulse generation system is difficult to balance fast rising edge and high pulse amplitude, and the synchronization of the output multi-channel pulse is easily affected by environmental factors (such as changes in ambient temperature) or changes in power supply voltage, which makes its synchronization worse and makes it impossible to adaptively adjust the synchronization of the output pulse according to the usage conditions.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A multi-channel synchronous fast rising edge pulse generation device, characterized in that it specifically includes: one input trigger pulse conditioning circuit, one FPGA module, one multi-channel clock fan-out buffer, N programmable pulse delay circuits, N multi-channel fast pulse signal generation circuits based on avalanche transistors, and N time-to-digital conversion circuits; wherein:

[0008] The programmable pulse delay circuit, the multi-channel fast pulse signal generation circuit based on avalanche transistor, and the time-to-digital conversion circuit correspond one-to-one and together constitute N channels.

[0009] The input trigger pulse conditioning circuit is used to convert the externally input non-standard voltage trigger pulse signal into a standard level trigger signal and input it into the FPGA module;

[0010] The FPGA module is used to generate N trigger pulses and 1 reference pulse based on a standard level trigger signal. Each trigger pulse is input to the corresponding channel's programmable pulse signal delay circuit, and the reference pulse is input to a multi-channel clock fan-out buffer. At the same time, the FPGA module is connected to control the programmable pulse signal delay circuit and the time-to-digital converter circuit.

[0011] The multi-channel clock fan-out buffer is used to divide the reference pulse output by the FPGA into N channels, and each reference pulse is input to the time-to-digital converter circuit of the corresponding channel.

[0012] The programmable pulse signal delay circuit is controlled by the FPGA module and is used to generate a picosecond-level delay for the trigger pulse input by the FPGA module, and output the delayed pulse to the multi-channel fast pulse signal generation circuit based on the avalanche transistor.

[0013] The multi-channel fast pulse signal generation circuit based on avalanche transistor is used to generate fast rising edge pulse signals and divide them into M synchronous fast rising edge pulse signals. Among them, M-1 synchronous fast rising edge pulse signals are used as the output of the device, and 1 synchronous fast rising edge pulse signal is used as the feedback input to the time-to-digital converter circuit.

[0014] The time-to-digital conversion circuit is used to measure the delay time between the reference pulse and the synchronous fast rising edge pulse signal, and feeds the measurement result back to the FPGA module.

[0015] The FPGA module automatically adjusts the delay amount of the programmable pulse signal delay circuit of the corresponding channel according to the delay time measurement result, so that N channels can synchronously output (M-1)×N synchronous fast rising edge pulse signals.

[0016] Optionally, the input trigger pulse conditioning circuit is composed of a hysteresis comparator. The externally input non-standard voltage trigger pulse signal is input to the hysteresis comparator after being divided by a resistor, and the hysteresis comparator generates a standard level pulse signal output.

[0017] Optionally, the FPGA module includes: a multi-channel delay trigger pulse generation module, a pulse delay measurement reference signal generation module, a time-to-digital conversion circuit control module, and a programmable pulse delay circuit control module;

[0018] The multi-channel delay trigger pulse generation module generates trigger pulses for the corresponding channels based on the input standard level trigger signal and the delay measurement result;

[0019] The pulse delay measurement reference signal generation module is used to generate a reference pulse;

[0020] The time-to-digital converter circuit control module is used to control the time-to-digital converter circuit of each channel and read the delay measurement results of the corresponding channel.

[0021] The programmable pulse delay circuit control module is used to control the threshold voltage of the digital-to-analog converter in the programmable pulse signal delay circuit.

[0022] Optionally, the programmable pulse signal delay circuit includes: a digital-to-analog converter module and a high-speed comparator module;

[0023] The digital-to-analog converter circuit is controlled by the FPGA module and is used to set the threshold voltage at the inverting input of the high-speed comparator.

[0024] The inverting input of the high-speed comparator module is connected to the output of the digital-to-analog converter circuit, and the non-inverting input is connected to the trigger pulse output by the FPGA module.

[0025] Optionally, the multi-channel fast pulse signal generation circuit based on avalanche transistors includes: a high-voltage DC regulated power supply, an avalanche transistor pulse signal generation circuit, and a passive power divider;

[0026] The high-voltage DC regulated power supply provides high-voltage power to the avalanche transistor pulse signal generation circuit;

[0027] The avalanche transistor pulse signal generation circuit is used to generate a high-voltage, fast-rising-edge pulse signal. When the base of the avalanche transistor receives a trigger pulse, avalanche breakdown occurs, and the energy storage capacitor of the avalanche transistor pulse signal generation circuit discharges rapidly, generating a fast-rising-edge pulse signal.

[0028] The passive power divider is used to divide the fast rising edge pulse signal generated by the avalanche transistor pulse signal generation circuit into M synchronous fast rising edge pulse outputs.

[0029] Optionally, the multi-channel clock fan-out buffer is composed of a clock fan-out buffer chip, which generates N synchronous reference pulse outputs based on the reference pulse input from the FPGA.

[0030] Optionally, the time-to-digital conversion circuit includes: a time-to-digital conversion chip and a pulse amplitude adjustment module;

[0031] The time-to-digital converter chip is configured via an FPGA module. Its start pin is connected to a reference pulse, and its stop pin is connected to a fast rising edge pulse signal. The FPGA module controls the reading of the delay time difference between the fast rising edge pulse signal and the reference pulse signal.

[0032] The pulse amplitude adjustment module is used to attenuate fast rising edge pulse signals to ensure the normal operation of the time-to-digital converter chip.

[0033] Furthermore, the calibration process for the multi-channel synchronous fast rising edge pulse generation device includes the following steps:

[0034] Step 1. The FPGA module completes the initialization configuration of the programmable pulse signal delay circuit and the time-to-digital conversion circuit;

[0035] Step 2. The FPGA module controls the initial delay measurement of the fast rising edge pulses output by each channel;

[0036] The FPGA module generates a synchronous trigger pulse signal and a reference pulse signal, and sets the threshold voltage of the programmable pulse signal delay circuit to the minimum value. It reads the delay measurement results of each channel and uses the channel with the largest delay as the reference channel.

[0037] Step 3. The FPGA module controls the coarse adjustment of the channel trigger pulse delay;

[0038] The FPGA module generates trigger pulse signals and reference pulse signals multiple times. During each triggering process, the trigger pulse delay settings of the other channels except the reference channel are gradually increased according to the preset step size. The delay measurement results of each channel are read. When the difference between the delay measurement result of the adjusted channel and the delay measurement result of the reference channel is less than the preset coarse adjustment threshold, the coarse adjustment of the delay of that channel is completed and the coarse adjustment setting of that channel is saved until the coarse adjustment of the delay of all channels is completed.

[0039] Step 4. The FPGA module controls the fine-tuning of the channel trigger pulse delay;

[0040] The FPGA module generates trigger pulse signals and reference pulse signals with corresponding channel delays multiple times according to the coarse adjustment settings of the channel trigger pulse delay. During each triggering process, the threshold voltage of the high-speed comparator module in the programmable pulse signal delay circuit is increased by a preset step size for the other channels except the reference channel. The delay measurement results of each channel are read. When the difference between the delay measurement result of the channel and the delay measurement result of the reference channel is less than the preset fine adjustment threshold, the channel delay fine adjustment is completed and the delay fine adjustment settings of the channel are saved until the delay fine adjustment of all channels is completed.

[0041] Based on the above technical solution, the beneficial effects of the present invention are as follows:

[0042] This invention provides a multi-channel synchronous fast-rising-edge pulse generation device. It uses an FPGA combined with a programmable pulse signal delay circuit to generate picosecond-level delayed trigger pulses, which in turn trigger a fast-rising-edge pulse signal generation circuit based on an avalanche transistor to generate fast-rising-edge pulse signals. These signals are then output through a passive power divider to drive a 50Ω load. The device generates output pulse signals based on the avalanche effect of the avalanche transistor, achieving fast rising edges. Furthermore, depending on the avalanche transistor selection and the applied supply voltage, high-amplitude pulse signal output can be achieved, ensuring driving capability. The device also integrates a time-to-digital converter circuit, which measures the time difference between the output synchronous pulse and the reference pulse before each use. The FPGA and programmable pulse signal delay circuit are used to adjust the trigger pulse delay of each avalanche transistor fast-rising-edge pulse signal generation circuit, achieving synchronization adjustment of each pulse. This effectively solves the problem of deteriorated synchronization of multiple pulses caused by changes in temperature, supply voltage, and other factors, ensuring the synchronization of the trigger pulses. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the system structure of the multi-channel synchronous fast rising edge pulse generation device in this invention.

[0044] Figure 2 This is a schematic diagram illustrating the calibration process of the multi-channel synchronous fast rising edge pulse generation device in this invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0046] This embodiment provides a multi-channel synchronous fast rising edge pulse generation device, such as... Figure 1 As shown, it specifically includes: one input trigger pulse conditioning circuit, one FPGA module, one multi-channel clock fan-out buffer, N programmable pulse delay circuits, N multi-channel fast pulse signal generation circuits based on avalanche transistors, and N time-to-digital conversion circuits; wherein:

[0047] The input trigger pulse conditioning circuit is used to convert the externally input non-standard voltage trigger pulse signal into a standard level signal and input it into the FPGA module to trigger the generation of multiple pulse outputs;

[0048] The FPGA module is used to generate N trigger pulses with different delays and 1 reference pulse based on the externally input trigger pulse signal. Each trigger pulse is input to the corresponding programmable pulse signal delay circuit, and the reference pulse is input to a multi-channel clock fan-out buffer. At the same time, the FPGA module controls the programmable pulse signal delay circuit to generate a picosecond-level delay for the trigger pulse. The FPGA module is configured with a time-to-digital converter circuit to measure the delay between the fast rising edge pulse signal of each output channel and the reference pulse output by the multi-channel clock fan-out buffer, and automatically adjust the delay of the FPGA output multi-channel trigger pulses and the delay of the programmable pulse signal delay circuit.

[0049] The programmable pulse signal delay circuit is controlled by the FPGA module and is used to generate picosecond-level delay pulses from the trigger pulse signals input to the FPGA module, and output them to the multi-channel fast pulse signal generation circuit based on avalanche transistors.

[0050] The multi-channel fast pulse signal generation circuit based on avalanche transistor is used to generate high-voltage, fast-rising-edge pulse signals, and then a passive power divider is used to divide the high-voltage pulse signal into M synchronous fast-rising-edge pulse signals for output.

[0051] The multi-channel clock fan-out buffer is used to divide the reference pulse signal output by the FPGA into N channels and input them to the time-to-digital converter circuit, thereby measuring the delay between the fast rising edge synchronous pulse output by the multi-channel synchronous fast rising edge pulse generator and the reference signal.

[0052] The time-to-digital converter circuit is used to measure the delay time between the reference pulse signal output by the FPGA through the multi-channel clock fan-out buffer and the fast rising edge pulse signal output by the multi-channel synchronous fast rising edge pulse generator.

[0053] Optionally, the input trigger pulse conditioning circuit is composed of a hysteresis comparator. A high-speed comparator is selected for the design. Its function is to convert the externally input non-standard voltage trigger pulse signal into a standard level pulse signal for input to the FPGA module. The externally input trigger pulse signal is divided by resistors and then input to the hysteresis comparator to generate a standard level pulse signal for output.

[0054] Optionally, the FPGA module includes: a multi-channel delay trigger pulse generation module, a pulse delay measurement reference signal generation module, a time-to-digital conversion circuit control module, and a programmable pulse delay circuit control module;

[0055] The multi-channel delay trigger pulse generation module generates multiple trigger pulses with different time delays based on the input trigger pulse signal and the time delay measurement results of each output pulse during calibration. The output pulses are then sent to the programmable pulse signal delay circuit. In this module, each trigger pulse generates a nanosecond-level delay to perform a coarse adjustment of the output pulse synchronization.

[0056] The pulse delay measurement reference signal generation module generates a reference signal for measuring the delay between the fast rising edge synchronization pulse signals of each output. The reference pulse signal generated by this module is output to the multi-channel clock fan-out buffer to generate multiple reference pulse signals. Taking advantage of the high pulse synchronization of the multi-channel clock fan-out buffer, it is used to measure the time delay between the multiple pulses output by the device designed in this invention and the reference pulse, thereby determining the synchronization between the pulses output by the device of this invention.

[0057] The time-to-digital converter circuit control module is used to control the multi-channel time-to-digital converter circuit, and reads the time delay of the multi-channel pulse signal output by the device relative to the reference signal during calibration. It also transmits the time delay result of the output multi-channel pulse to the multi-channel delay trigger pulse generation module (implemented in the FPGA module) and the programmable pulse delay circuit control module for adjusting the delay of the output pulse.

[0058] The programmable pulse delay circuit control module controls the output voltage of the digital-to-analog converter in the programmable pulse signal delay circuit. This voltage signal is input to the inverting input of the comparator in the programmable pulse signal delay circuit. Meanwhile, the trigger pulse signal output by the multi-channel delay trigger pulse generation module in the FPGA module is input to the non-inverting input of the comparator in the programmable pulse signal delay circuit. Since the trigger pulse output by the FPGA has a certain rising edge, the delay of the trigger pulse output by the comparator in the programmable pulse signal delay circuit can be adjusted by changing the voltage of the inverting input, thereby achieving picosecond-level delay of the trigger pulse signal and realizing fine adjustment of the trigger pulse signal delay.

[0059] Optionally, the programmable pulse signal delay circuit includes: a digital-to-analog converter module and a high-speed comparator module;

[0060] The digital-to-analog converter circuit is controlled by the FPGA module and is used to set the threshold voltage of the inverting input of the high-speed comparator. Since the trigger pulse signal input to the programmable pulse signal delay circuit has a certain rising edge, the output voltage of the digital-to-analog converter circuit can be set by the FPGA to flexibly adjust the threshold voltage of the high-speed comparator, thereby adjusting the delay time of the high-speed comparator to generate pulse output to the input trigger pulse signal, and realizing picosecond-level delay output adjustment.

[0061] The inverting input of the high-speed comparator in the high-speed comparator module is connected to the output of the digital-to-analog converter circuit to set different comparator threshold voltages. The trigger pulse signal output by the multi-channel delay trigger pulse generation module in the FPGA module is input to the non-inverting input of the high-speed comparator module. Since the trigger pulse output by the FPGA has a certain rising edge, the delay of the trigger pulse output by the high-speed comparator can be adjusted by changing the voltage of the inverting input, thereby achieving picosecond-level delay of the trigger pulse signal and realizing fine adjustment of the trigger pulse signal delay.

[0062] Optionally, the multi-channel fast pulse signal generation circuit based on avalanche transistors includes: a high-voltage DC regulated power supply, an avalanche transistor pulse signal generation circuit, and a passive power divider;

[0063] The high-voltage DC regulated power supply provides high-voltage power to the avalanche transistor pulse signal generation circuit;

[0064] The avalanche transistor pulse signal generation circuit is used to generate a fast-rising-edge pulse signal with a high voltage amplitude. When the base of the avalanche transistor receives the trigger pulse signal, avalanche breakdown occurs, and the energy storage capacitor of the avalanche transistor pulse signal generation circuit discharges rapidly, generating a high-voltage, fast-rising-edge pulse signal. By adjusting the delay of the trigger pulse signal input to the multi-channel fast pulse signal generation circuit based on the avalanche transistor, the synchronization adjustment of each fast-rising-edge pulse signal can be achieved.

[0065] The passive power divider is used to divide the high-voltage, fast-rising-edge pulse signal generated by the avalanche transistor pulse signal generation circuit into multiple highly synchronized fast-rising-edge pulse outputs.

[0066] Optionally, the multi-channel clock fan-out buffer is composed of a clock fan-out buffer chip, which can generate multiple highly synchronized pulse signal outputs according to the trigger pulse signal input by the FPGA, thereby providing a reference for the measurement of the pulse delay of each output of the device.

[0067] Optionally, the time-to-digital conversion circuit includes: a time-to-digital conversion chip and a pulse amplitude adjustment module;

[0068] In the time-to-digital converter circuit, the time-to-digital converter chip is configured through an FPGA module. The start pin of the time-to-digital converter chip is connected to a reference pulse signal output by a multi-channel clock fan-out buffer, and the stop pin of the time-to-digital converter chip is connected to a fast rising edge pulse signal output by a passive power divider. The FPGA module controls the reading of the time difference between the fast rising edge pulse signal measured by each time-to-digital converter circuit and the reference pulse signal output by the multi-channel clock fan-out buffer, which serves as the basis for adjusting the trigger pulse delay.

[0069] The pulse amplitude adjustment module is used to attenuate the fast rising edge pulse signal input from the passive power divider, ensuring that its amplitude does not exceed the normal range of the pin input voltage of the time-to-digital converter chip.

[0070] Based on the aforementioned multi-channel synchronous fast rising edge pulse generator, upon power-on, it first enters calibration mode. In calibration mode, by adjusting the delay of each trigger pulse, the output of multiple fast rising edge pulses is synchronized. After calibration is completed, the device automatically enters normal operation mode, that is, it receives external trigger pulses and generates multiple synchronous fast rising edge pulse signals. The calibration process is as follows: Figure 2 As shown, the specific steps include:

[0071] Step 1. The FPGA module first completes the initialization configuration of the digital-to-analog converter circuit module and the time-to-digital converter circuit in the programmable pulse signal delay circuit;

[0072] Step 2. The FPGA module controls the initial delay measurement of the fast rising edge output pulse of each channel;

[0073] The FPGA module generates synchronous multi-channel trigger pulse signals and reference pulse signals through its internal multi-channel delay trigger pulse generation module. These signals are then output to each programmable pulse signal delay circuit and multi-channel clock fan-out buffer. The threshold of the programmable pulse signal delay circuit is set to the minimum value of the high-speed comparator threshold. This controls each time-to-digital converter circuit to measure the delay between the fast rising edge synchronous pulse output from each channel and the reference pulse signal output from the multi-channel clock fan-out buffer, using the channel with the largest delay as a reference.

[0074] Step 3. The FPGA module controls the coarse adjustment of the channel trigger pulse delay;

[0075] The FPGA module controls the internal multi-channel delay trigger pulse generation module to generate multiple trigger pulse signals. Each time a trigger pulse signal is generated, except for the reference channel and the trigger signal input to the multi-channel clock fan-out buffer, the delay setting of the trigger pulse is increased by a certain step size for the other channels. At the same time, the time-to-digital conversion circuit controls each time to measure the delay between the fast rising edge synchronization pulse output of the channel and the reference pulse signal output by the multi-channel clock fan-out buffer. Relative to the reference pulse signal, when the delay of the adjusted channel output pulse and the delay of the reference channel are less than the set coarse adjustment threshold (the delay of the adjusted channel does not exceed the delay of the reference channel), the delay adjustment of the channel is stopped and the coarse adjustment setting of the channel is saved. The delay of the channel is not increased when the trigger pulse is generated next time. Otherwise, the channel continues to increase the trigger pulse delay by the set step size until the delay of all channels and the reference channel is less than the set coarse adjustment threshold.

[0076] Step 4. The FPGA module controls the fine-tuning of the channel trigger pulse delay;

[0077] The FPGA module controls the internal multi-channel delay trigger pulse generation module to generate multiple trigger pulse signals with corresponding channel delays multiple times according to the coarse adjustment setting of the channel trigger pulse delay. Each time a trigger pulse signal is generated and output, except for the reference channel and the trigger signal input to the multi-channel clock fan-out buffer, the delays of the other channels are set according to the delay determined in step 3. Except for the reference channel, the FPGA module controls the digital-to-analog converter in the programmable pulse signal delay circuit of the other channels to increase the output voltage value by a certain step size each time to increase the trigger pulse delay of that channel. At the same time, it controls each time-to-digital conversion circuit to measure the current... The delay between the fast rising edge synchronization pulse output by the device channel and the reference pulse signal output by the multi-channel clock fan-out buffer, relative to the reference pulse signal, is such that when the delay of the adjusted channel output pulse and the delay of the reference channel are less than the set fine-tuning threshold, the channel stops delay adjustment and saves the channel's delay fine-tuning setting. The output voltage of the digital-to-analog converter in the programmable pulse signal delay circuit of the channel no longer changes. Otherwise, the channel continues to increase the output voltage of the digital-to-analog converter according to the set step size to increase the trigger pulse delay until the delay of all channels and the reference channel is less than the set fine-tuning threshold, and the calibration is completed.

[0078] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A multi-channel synchronous fast rising edge pulse generation device, characterized in that, Specifically, it includes: The system includes one input trigger pulse conditioning circuit, one FPGA module, one multi-channel clock fan-out buffer, N programmable pulse delay circuits, N multi-channel fast pulse signal generation circuits based on avalanche transistors, and N time-to-digital conversion circuits; among which: The programmable pulse delay circuit, the multi-channel fast pulse signal generation circuit based on avalanche transistor, and the time-to-digital conversion circuit correspond one-to-one and together constitute N channels. The input trigger pulse conditioning circuit is used to convert the externally input non-standard voltage trigger pulse signal into a standard level trigger signal and input it into the FPGA module; The FPGA module is used to generate N trigger pulses and 1 reference pulse based on a standard level trigger signal. Each trigger pulse is input to the corresponding channel's programmable pulse signal delay circuit, and the reference pulse is input to a multi-channel clock fan-out buffer. At the same time, the FPGA module is connected to control the programmable pulse signal delay circuit and the time-to-digital converter circuit. The multi-channel clock fan-out buffer is used to divide the reference pulse output by the FPGA into N channels, and each reference pulse is input to the time-to-digital converter circuit of the corresponding channel. The programmable pulse signal delay circuit is controlled by the FPGA module and is used to generate a picosecond-level delay for the trigger pulse input by the FPGA module, and output the delayed pulse to the multi-channel fast pulse signal generation circuit based on the avalanche transistor. The multi-channel fast pulse signal generation circuit based on avalanche transistor is used to generate fast rising edge pulse signals and divide them into M synchronous fast rising edge pulse signals. Among them, M-1 synchronous fast rising edge pulse signals are used as the output of the device, and 1 synchronous fast rising edge pulse signal is used as the feedback input to the time-to-digital converter circuit. The time-to-digital conversion circuit is used to measure the delay time between the reference pulse and the synchronous fast rising edge pulse signal, and feeds the measurement result back to the FPGA module. The FPGA module automatically adjusts the delay amount of the programmable pulse signal delay circuit of the corresponding channel according to the delay time measurement result, so that N channels can synchronously output (M-1)×N synchronous fast rising edge pulse signals.

2. The multi-channel synchronous fast rising edge pulse generation device according to claim 1, characterized in that, The input trigger pulse conditioning circuit is composed of a hysteresis comparator. The externally input non-standard voltage trigger pulse signal is input to the hysteresis comparator after being divided by a resistor, and the hysteresis comparator generates a standard level pulse signal output.

3. The multi-channel synchronous fast rising edge pulse generating device according to claim 1, characterized in that, The FPGA module includes: a multi-channel delay trigger pulse generation module, a pulse delay measurement reference signal generation module, a time-to-digital conversion circuit control module, and a programmable pulse delay circuit control module; The multi-channel delay trigger pulse generation module generates trigger pulses for the corresponding channels based on the input standard level trigger signal and the delay measurement result; The pulse delay measurement reference signal generation module is used to generate a reference pulse; The time-to-digital converter circuit control module is used to control the time-to-digital converter circuit of each channel and read the delay measurement results of the corresponding channel. The programmable pulse delay circuit control module is used to control the threshold voltage of the digital-to-analog converter in the programmable pulse signal delay circuit.

4. The multi-channel synchronous fast rising edge pulse generating device according to claim 1, characterized in that, The programmable pulse signal delay circuit includes: a digital-to-analog converter module and a high-speed comparator module; The digital-to-analog converter circuit is controlled by the FPGA module and is used to set the threshold voltage at the inverting input of the high-speed comparator. The inverting input of the high-speed comparator module is connected to the output of the digital-to-analog converter circuit, and the non-inverting input is connected to the trigger pulse output by the FPGA module.

5. The multi-channel synchronous fast rising edge pulse generating device according to claim 1, characterized in that, The multi-channel fast pulse signal generation circuit based on avalanche transistors includes: a high-voltage DC regulated power supply, an avalanche transistor pulse signal generation circuit, and a passive power divider; The high-voltage DC regulated power supply provides high-voltage power to the avalanche transistor pulse signal generation circuit; The avalanche transistor pulse signal generation circuit is used to generate a high-voltage, fast-rising-edge pulse signal. When the base of the avalanche transistor receives a trigger pulse, avalanche breakdown occurs, and the energy storage capacitor of the avalanche transistor pulse signal generation circuit discharges rapidly, generating a fast-rising-edge pulse signal. The passive power divider is used to divide the fast rising edge pulse signal generated by the avalanche transistor pulse signal generation circuit into M synchronous fast rising edge pulse outputs.

6. The multi-channel synchronous fast rising edge pulse generating device according to claim 1, characterized in that, The multi-channel clock fan-out buffer is composed of a clock fan-out buffer chip, which generates N synchronous reference pulse outputs based on the reference pulse input from the FPGA.

7. The multi-channel synchronous fast rising edge pulse generating device according to claim 1, characterized in that, The time-to-digital conversion circuit includes: a time-to-digital conversion chip and a pulse amplitude adjustment module; The time-to-digital converter chip is configured via an FPGA module. Its start pin is connected to a reference pulse, and its stop pin is connected to a fast rising edge pulse signal. The FPGA module controls the reading of the delay time difference between the fast rising edge pulse signal and the reference pulse signal. The pulse amplitude adjustment module is used to attenuate fast rising edge pulse signals to ensure the normal operation of the time-to-digital converter chip.

8. The multi-channel synchronous fast rising edge pulse generating device according to claim 1, characterized in that, The calibration process for the multi-channel synchronous fast rising edge pulse generator includes the following steps: Step 1. The FPGA module completes the initialization configuration of the programmable pulse signal delay circuit and the time-to-digital conversion circuit; Step 2. The FPGA module controls the initial delay measurement of the fast rising edge pulses output by each channel; The FPGA module generates a synchronous trigger pulse signal and a reference pulse signal, and sets the threshold voltage of the programmable pulse signal delay circuit to the minimum value. It reads the delay measurement results of each channel and uses the channel with the largest delay as the reference channel. Step 3. The FPGA module controls the coarse adjustment of the channel trigger pulse delay; The FPGA module generates trigger pulse signals and reference pulse signals multiple times. During each triggering process, the trigger pulse delay settings of the other channels except the reference channel are gradually increased according to the preset step size. The delay measurement results of each channel are read. When the difference between the delay measurement result of the adjusted channel and the delay measurement result of the reference channel is less than the preset coarse adjustment threshold, the coarse adjustment of the delay of that channel is completed and the coarse adjustment setting of that channel is saved until the coarse adjustment of the delay of all channels is completed. Step 4. The FPGA module controls the fine-tuning of the channel trigger pulse delay; The FPGA module generates trigger pulse signals and reference pulse signals with corresponding channel delays multiple times according to the coarse adjustment settings of the channel trigger pulse delay. During each triggering process, the threshold voltage of the high-speed comparator module in the programmable pulse signal delay circuit is increased by a preset step size for the other channels except the reference channel. The delay measurement results of each channel are read. When the difference between the delay measurement result of the channel and the delay measurement result of the reference channel is less than the preset fine adjustment threshold, the channel delay fine adjustment is completed and the delay fine adjustment settings of the channel are saved until the delay fine adjustment of all channels is completed.

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