Multi-protocol dynamic switching method and system based on FPGA

Abstract

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic communication technology, specifically to a multi-protocol dynamic switching method and system based on FPGA. Background Technology

[0002] With the rapid development of avionics, intelligent communications and other fields, the demand for support for multiple communication protocols is increasing. As the number of protocols increases, static protocol configuration schemes result in a large amount of logic resources being idle, while the parallel operation of multiple protocol modules also leads to timing conflicts and wasted power consumption.

[0003] Existing technologies employ various configuration schemes. First, multiple independent hardware schemes are used, but this results in significant resource waste, with only some hardware operating at any given time, while the rest remain idle, leading to high system cost and large size. Second, static parallel configuration schemes, while integrating multiple protocol modules on the FPGA, require all modules to simultaneously occupy logic resources. As the number of protocol types increases, resource utilization becomes extremely low, and the parallel operation of multiple modules introduces complex timing constraints and power consumption issues. Third, global reconfiguration schemes suffer from excessively long switching times and interrupt system operation, making them unsuitable for applications requiring real-time protocol switching. For example, in mixed transmission of video surveillance and command control, protocol switching delays can lead to data loss or slow system response. Fourth, existing schemes lack effective cross-protocol data synchronization mechanisms. Differences in clock domains and data formats between different protocols can easily lead to data loss or inconsistent states during protocol switching, affecting system reliability. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a multi-protocol dynamic switching method and system based on FPGA.

[0005] The first aspect of this invention provides a multi-protocol dynamic switching method based on FPGA, comprising: S1: Divide the FPGA chip into regions using a layout planning tool to obtain a static logic area and multiple reconfigurable logic partitions; S2: Based on the protocol switching trigger signal, the current protocol module is suspended, the running status data of the current protocol module is written to the status cache unit, and the protocol context snapshot data is obtained; S3: Based on the target protocol type, load the bitstream of the corresponding reconfigurable logical partition by configuring the access port to obtain the reconfigurable protocol module; S4: Read the protocol context snapshot data, restore the state of the reconstructed protocol module, and obtain the target protocol data path.

[0006] According to the FPGA-based multi-protocol dynamic switching method provided by the present invention, step S1 further includes: S11: Define the physical boundaries of the static logic area in the FPGA chip, and allocate the global control logic, clock management unit and configuration manager to the static logic area; S12: Based on the number of communication protocol types, the remaining resources of the FPGA chip are divided into multiple spatially independent reconfigurable logic partitions. Each reconfigurable logic partition reserves a fixed number of programmable logic units, block memory, and digital signal processing units. S13: Set an independent operating frequency for each reconfigurable logic partition through clock domain isolation constraints, and establish a clock synchronization interface between the static logic area and the reconfigurable logic partition.

[0007] According to the FPGA-based multi-protocol dynamic switching method provided by the present invention, step S2 further includes: S21: Detect the signal type of the protocol switching trigger signal. When the signal type is triggered by an external command, parse the target protocol identifier to obtain the target protocol type. When the signal type is triggered by an event, obtain the target protocol type based on data stream feature pattern matching. S22: Send a data flow pause command to the current protocol module to block the input and output data path of the current protocol module; S23: Extract the state machine parameters, sequence count value, and queue pointer position of the current protocol module through register scan operation, and assemble them into a structured context data packet; S24: Write the context data packet and the data frame that has not been transmitted into the state cache unit through dual-port access to generate protocol context snapshot data.

[0008] According to the FPGA-based multi-protocol dynamic switching method provided by the present invention, step S3 further includes: S31: Based on the target protocol type, read the corresponding bitstream file from the storage medium, decompress the bitstream file using a data compression algorithm, and obtain the original configuration data stream; S32: Input the original configuration data stream to the internal configuration access port, and control the configuration storage unit of the target reconfigurable logical partition to perform frame-by-frame writing operations through the configuration state machine. S33: Monitor the configuration completion signal. When the bit stream loading is detected to be finished, perform a logical reset on the reconstructed reconfigurable logical partition to obtain the reconstructed protocol module.

[0009] According to the FPGA-based multi-protocol dynamic switching method provided by the present invention, step S4 further includes: S41: Read the protocol context snapshot data from the state cache unit and verify the data validity based on the timestamp information; S42: Write the state machine parameters and sequence count values ​​from the valid protocol context snapshot data into the internal register of the reconstructed protocol module; S43: Reload the data frames that have not been transmitted into the input buffer of the reconstruction protocol module according to the queue pointer position; S44: Enable the clock enable signal of the reconfiguration protocol module, establish the connection path between the reconfiguration protocol module and the unified data bus, and generate an activated target protocol data path.

[0010] According to the present invention, a multi-protocol dynamic switching method based on FPGA is provided, wherein the static logic area is provided with a configuration manager, the configuration manager is used to control partial reconfiguration, and the step of the configuration manager controlling partial reconfiguration further includes: S101: Receive a protocol switching request instruction from the host interface, and parse the protocol switching request instruction to obtain the physical address range of the target reconfigurable logical partition; S102: Generate a configuration frame address sequence according to the physical address range, and write part of the bit stream data into the configuration storage unit of the target reconfigurable logical partition in the order of the configuration frames through the internal configuration access port; S103: During the bitstream loading process, the cyclic redundancy check code of the configuration data is verified in real time. When the verification fails, a reloading mechanism is triggered or the system is rolled back to the previous stable configuration state.

[0011] According to the present invention, a multi-protocol dynamic switching method based on FPGA is provided, wherein multiple reconfigurable logical partitions correspond to different protocol types in the Fibre Channel protocol family, specifically including: The first reconfigurable logical partition loads the processing logic of the bus-type command response protocol, and generates status response data after parsing the command words; The second reconfigurable logical partition loads the processing logic of the asynchronous service encapsulation protocol, and encapsulates data packets through service identifier mapping and priority scheduling mechanism; The third reconfigurable logical partition loads the processing logic of the video stream transmission protocol, and performs timestamp embedding and isochronous transmission control processing on the video data frames.

[0012] This invention also provides a multi-protocol dynamic switching system based on FPGA, comprising: An FPGA chip, wherein the internal structure of the FPGA chip is divided into a static logic area and multiple reconfigurable logic partitions; The static logic area includes a global clock management unit, a configuration manager, a unified data bus, and a host interface controller. The configuration manager is connected to each reconfigurable logical partition through an internal configuration access port. Multiple reconfigurable logical partitions, each of which reserves a fixed number of programmable logic units, block memory and digital signal processing units for loading processing logic for different communication protocols; The state buffer unit, consisting of a dual-port block memory, is used to store context snapshot data and incomplete data frames during protocol switching. The clock domain synchronization module includes multiple asynchronous first-in-first-out buffers, which are connected between different reconfigurable logical partitions and a unified data bus to enable data transmission across clock domains.

[0013] A third aspect of the present invention provides a multi-protocol dynamic switching device based on FPGA, comprising: A memory and at least one processor, wherein the memory stores instructions; At least one of the processors invokes the instructions in the memory to cause an FPGA-based multi-protocol dynamic switching device to execute an FPGA-based multi-protocol dynamic switching method as described in any of the preceding claims.

[0014] A fourth aspect of the present invention provides a computer-readable storage medium storing instructions that, when executed by a processor, implement a multi-protocol dynamic switching method based on an FPGA as described in any of the preceding claims.

[0015] This invention establishes a physically isolated architecture of a static logic area and multiple reconfigurable logic partitions within an FPGA chip. Combined with a partial bitstream loading mechanism based on internal configuration access ports, this allows the protocol switching process to require only a local reconfiguration of the target partition without interrupting the entire system. This significantly reduces switching time, meeting the stringent latency requirements of real-time communication scenarios for dynamic protocol switching and effectively preventing data loss and service interruption during the switching process. Furthermore, this invention employs a protocol context snapshot data saving and recovery mechanism. By writing key operating states such as state machine parameters, sequence count values, and queue pointers into a dual-port block memory and performing precise recovery after reconfiguration, it ensures the continuity of data transmission before and after protocol switching. State consistency solves the communication failure problem caused by state loss in traditional solutions. Furthermore, this invention, through a reconfigurable logical partitioning on-demand loading method, ensures that only the currently working protocol module occupies FPGA resources at any given time. Compared to the static parallel configuration scheme where all protocol modules occupy resources simultaneously, hardware resource utilization is improved, significantly reducing the need for FPGA chip size and lowering hardware costs. Additionally, the asynchronous first-in-first-out buffer and global timestamp mechanism introduced in this invention effectively solve the clock domain synchronization problem caused by differences in the operating frequencies of different protocol modules. Through Gray code pointer synchronization and unified data frame format encapsulation, lossless transmission of multi-clock domain data over a wide range is achieved, ensuring the reliability of cross-protocol data interaction.

[0016] Overall, the present invention maintains system flexibility while taking into account real-time performance, resource efficiency, and reliability, providing an efficient and feasible technical solution for complex application scenarios such as avionics and industrial communications that require dynamic switching of multiple protocols. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This application provides a schematic flowchart of a multi-protocol dynamic switching method based on FPGA. Figure 2 This is a schematic diagram of a multi-protocol dynamic switching system structure based on FPGA provided in an embodiment of this application. Detailed Implementation

[0018] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] As mentioned in the background section, this application proposes a multi-protocol dynamic switching method and system based on FPGA.

[0021] like Figure 1 As shown, the first aspect of the present invention provides a multi-protocol dynamic switching method based on FPGA, comprising: S1: Divide the FPGA chip into regions using a layout planning tool to obtain a static logic area and multiple reconfigurable logic partitions.

[0022] Step S1 further includes: S11: Define the physical boundaries of the static logic area in the FPGA chip, and allocate the global control logic, clock management unit and configuration manager to the static logic area.

[0023] In step S11, the present invention first launches the Vivado layout planning graphical tool and selects the physical boundary range of the static logic area in the FPGA chip design canvas by dragging and dropping the mouse. The boundary coordinates of the static logic area are defined by a coordinate system, for example, the range from the starting coordinate 0 to the ending coordinate 100 of the logic chip in the upper left corner of the chip is defined as the static area. Subsequently, the present invention instantiates the hardware description code of the PCIe controller module, DDR4 memory controller module, and global clock management module into this static area, and locks the logic units of these modules in the specified physical locations by setting position constraint statements. The configuration manager module contains an internal configuration access port primitive instance, which directly calls the configuration access hardware circuit inside the FPGA. The clock management unit instantiates a mixed-mode clock manager or phase-locked loop module, receives the externally input reference clock signal, and generates a 250MHz global control clock signal through frequency division, frequency multiplication, and phase adjustment. This clock signal is distributed to all logic modules in the static area through a global clock tree buffer.

[0024] The static logic area includes a configuration manager, which controls partial reconfiguration. The steps of controlling partial reconfiguration by the configuration manager further include: S101: Receive a protocol switching request instruction from the host interface, and parse the protocol switching request instruction to obtain the physical address range of the target reconfigurable logical partition.

[0025] In step S101, the host sends a protocol switching request data packet to the FPGA via the PCIe bus. This data packet contains a 32-bit instruction field and a 32-bit parameter field. The state machine module in the configuration manager continuously polls the receive-first-out buffer of the PCIe interface. When it detects that the buffer is not empty, it reads the high 8 bits of the instruction field as the command code and determines whether the command code equals hexadecimal A5, indicating a protocol switching request. Subsequently, the configuration manager extracts the low 8 bits of the parameter field as the target protocol identifier. The hexadecimal identifier 01 corresponds to the first partition of the FC-AE-1553 protocol, the hexadecimal identifier 02 corresponds to the second partition of the FC-AE-ASM protocol, and the hexadecimal identifier 03 corresponds to the third partition of the FC-AV protocol.

[0026] This invention queries a pre-stored partition address mapping table based on the protocol identifier. This mapping table is stored in a register array inside the configuration manager, and each entry contains the partition start address, end address, and bitstream file offset. For example, the start address of the second partition is hexadecimal 00400000, and the end address is hexadecimal 00600000. The number of configuration frames occupied by this partition is calculated by subtracting the addresses.

[0027] S102: Generate a configuration frame address sequence based on the physical address range, and write part of the bit stream data into the configuration storage unit of the target reconfigurable logical partition in the order of the configuration frames through the internal configuration access port.

[0028] Furthermore, the configuration manager calculates the configuration frame address sequence based on the acquired physical address range. The FPGA's configuration memory is organized according to a frame structure, with each frame containing 101 32-bit configuration words. This invention right-shifts the starting address (hexadecimal 00400000) by 7 bits to obtain the starting frame number (hexadecimal 2000), and right-shifts the ending address (hexadecimal 00600000) by 7 bits to obtain the ending frame number (hexadecimal 3000), generating a continuous frame address sequence from hexadecimal 2000 to hexadecimal 3000. Subsequently, the configuration manager reads the corresponding partial bitstream file from external flash memory via the serial peripheral interface. This file contains the synchronization word (hexadecimal AA995566), the frame address write command (hexadecimal 30004000), and the actual configuration data.

[0029] Subsequently, this invention instantiates an internal configuration access port primitive module, writing each 32-bit word of bitstream data through the data input port, while simultaneously pulling up the chip select enable signal and the write enable signal. The internal configuration access port operates in a 100 MHz clock domain, and can write one 32-bit configuration word per clock cycle. Writing 4096 frames takes approximately 41 microseconds. Finally, the configuration data is written sequentially to the configuration storage unit of the second partition according to the frame address order, overwriting the original FC-AE-1553 protocol logic of that partition and loading the new FC-AE-ASM protocol logic.

[0030] S103: During the bitstream loading process, the cyclic redundancy check code of the configuration data is verified in real time. When the verification fails, a reloading mechanism is triggered or the system is rolled back to the previous stable configuration state.

[0031] Furthermore, each configuration frame in a portion of the bitstream file is appended with a 16-bit Cyclic Redundancy Check (CRC) code, which is automatically calculated by the Vivado tool during bitstream generation. This invention synchronously initiates a CRC calculation module during the internal configuration access port writing process. This module uses a 16-bit check polynomial hexadecimal 1021 to perform word-by-word accumulation calculations on the written configuration data.

[0032] Specifically, the verification module maintains a 16-bit register with an initial value of hexadecimal FFFF. For each 32-bit configuration word received, it performs four iterative operations: XORing the register with each byte of the configuration word; if the highest bit of the result is 1, the register is shifted left by 1 bit and then XORed with the polynomial; otherwise, it is only shifted left by 1 bit.

[0033] After a frame of configuration data is written, the present invention compares the calculated check value with the check value attached to the bitstream file. If the two values ​​are equal, the next frame is written. If the two values ​​are not equal, the configuration manager immediately stops the internal configuration access port write operation and pulls the chip select enable signal low.

[0034] Subsequently, the configuration manager reads the error frame address register to determine the frame number where the verification error occurred, and uses the state machine to fall back to the start address of that frame. It then rereads the frame data from the flash memory and rewrites it into the internal configuration access port. If the verification fails after three consecutive reloads, the invention triggers a global reset signal, writing the internal reprogramming command word (hexadecimal 30008001) into the internal configuration access port. This forces the FPGA to reload the backup configuration image, restoring it to the previous stable protocol configuration state.

[0035] S12: Based on the number of communication protocol types, the remaining resources of the FPGA chip are divided into multiple spatially independent reconfigurable logic partitions. Each reconfigurable logic partition reserves a fixed number of programmable logic units, block memory, and digital signal processing units.

[0036] Furthermore, this invention counts the number of communication protocols that need to be supported in the current design. For example, for the three protocols FC-AE-1553, FC-AE-ASM, and FC-AV, the number of reconfigurable logical partitions is set to three. Independent physical block partitions are created using the Create Physical Block Partition command in the Vivado tool, and each partition is named First Reconfigurable Partition, Second Reconfigurable Partition, and Third Reconfigurable Partition.

[0037] This invention allocates physical resources based on the resource requirement reports of each protocol module. The FC-AE-1553 module requires 1200 lookup tables and 2 block memories, so a rectangular area containing the logical slice start coordinates from 60 to 80 is allocated to the first partition. This area contains a sufficient number of 6-input lookup tables and 36 kilobits of block memory. The FC-AE-ASM module requires 2500 lookup tables and 4 block memories, so a larger area containing the logical slice start coordinates from 60 to 90 is allocated to the second partition. The FC-AV module requires 3500 lookup tables and 8 block memories, so an area containing the logical slice start coordinates from 100 to 140 is allocated to the third partition. Each partition has its routing attribute set to true using a setting attribute command, forcing routing resources within that partition not to cross partition boundaries, thus achieving physical isolation between partitions.

[0038] S13: Set an independent operating frequency for each reconfigurable logic partition through clock domain isolation constraints, and establish a clock synchronization interface between the static logic area and the reconfigurable logic partition.

[0039] The multiple reconfigurable logical partitions correspond to different protocol types in the Fibre Channel protocol family, specifically including: the first reconfigurable logical partition loads the processing logic of the bus-type command response protocol, which parses the command words and generates status response data; the second reconfigurable logical partition loads the processing logic of the asynchronous service encapsulation protocol, which encapsulates data packets through service identifier mapping and priority scheduling mechanism; and the third reconfigurable logical partition loads the processing logic of the video streaming protocol, which performs timestamp embedding and isochronous transmission control processing on video data frames.

[0040] This invention defines independent clock constraints for each reconfigurable logical partition in the Vivado timing constraint file. For the FC-AE-1553 protocol of the first partition, a clock object with a period of 1000 nanoseconds is created using the Create Clock command. This clock signal originates from a dedicated output port of the clock management unit. For the FC-AE-ASM protocol of the second partition, a clock object with a period of 9.4 nanoseconds (106.25 MHz) is created. For the FC-AV protocol of the third partition, a clock object with a period of 6.73 nanoseconds (148.5 MHz) is created. Subsequently, this invention uses the Set Clock Group command to mark these reconfigurable partition clocks and the global clock of the static region as asynchronous clock groups, disabling timing analysis tools from performing setup and hold time checks on cross-clock domain paths. At the boundary between the static logical region and each reconfigurable partition, this invention instantiates a streaming bus interface module, which includes data signals, valid signals, ready signals, and end flag signals. A handshake synchronization circuit is inserted at the boundary, and the valid signal and ready signal are synchronized across clock domains through a dual flip-flop chain. The data signal is clock domain converted through an asynchronous first-in-first-out buffer module.

[0041] S2: Based on the protocol switching trigger signal, suspend the current protocol module, write the running status data of the current protocol module into the status cache unit, and obtain the protocol context snapshot data.

[0042] Step S2 further includes: S21: Detect the signal type of the protocol switching trigger signal. When the signal type is triggered by an external command, parse the target protocol identifier to obtain the target protocol type. When the signal type is triggered by an event, obtain the target protocol type based on data stream feature pattern matching.

[0043] Furthermore, the interrupt controller module of the present invention continuously monitors the level of the general-purpose input / output pins and the interrupt request signal of the PCIe interface. When the general-purpose input / output pins switch from low level to high level, the protocol switching process of the external instruction type is triggered.

[0044] Subsequently, the interrupt controller reads the protocol selection register associated with the general-purpose input / output pin. Bits 1 to 0 of this register encode the target protocol type: binary 00 represents FC-AE-1553, binary 01 represents FC-AE-ASM, and binary 10 represents FC-AV. The register value is transmitted to the configuration manager via the bus to form the target protocol identifier. When an event-driven event is triggered, this invention deploys a protocol identification module on the unified data bus. This module performs real-time feature extraction on the data frames flowing through the bus.

[0045] Specifically, the identification module maintains a 32-byte sliding window buffer. Each received data word is pushed into the window, and the module checks if an MPEG transport stream synchronization byte (hexadecimal 47) is present at a fixed interval of 188 bytes. If three consecutive hexadecimal 47 synchronization bytes are detected at 188-byte intervals, the data stream is determined to be a video stream, and an FC-AV protocol type identifier is generated. If a data packet's starting byte is detected as hexadecimal 20 and subsequent bytes match the 1553 command word format, an FC-AE-1553 protocol type identifier is generated.

[0046] S22: Send a data flow pause command to the current protocol module to block the input and output data path of the current protocol module.

[0047] Furthermore, the configuration manager sends a data flow pause control signal to the currently running protocol module. This signal is transmitted to the flow control state machine inside the protocol module via a dedicated control bus. Upon receiving the pause signal, the flow control state machine pulls down the streaming bus valid signal at the output port to indicate that the data is invalid to the downstream module, and simultaneously pulls down the ready signal at the input port to indicate to the upstream module that it will no longer receive new data. At this time, the data path inside the protocol module is blocked, the input FIFO buffer stops writing operations, and the output FIFO buffer stops reading operations. In this invention, a data isolation multiplexer is inserted at the input and output ports, and the pause signal serves as the selection control terminal. When the selection signal is set to 1, the multiplexer output is forced to all zeros, cutting off the electrical connection between the protocol module and the unified data bus. After the pause operation is completed, the flow control state machine sends an acknowledgment signal back to the configuration manager. After the configuration manager detects that the acknowledgment signal is pulled high, it enters the next stage of the state saving process.

[0048] S23: Extract the state machine parameters, sequence count value, and queue pointer position of the current protocol module through register scan operation, and assemble them into a structured context data packet.

[0049] In step S23, the present invention starts the register scan controller, which accesses all configuration registers and status registers within the current protocol module through the internal debug bus. The scan controller maintains a register address list stored in read-only memory, which includes the physical addresses of key registers such as the state machine register address (hexadecimal 1000), the sequence count register address (hexadecimal 1004), the transmit queue head pointer register address (hexadecimal 1008), and the receive queue tail pointer register address (hexadecimal 100C).

[0050] Subsequently, the controller initiates read operations sequentially according to the address list, sending the read address and read enable signal via the lightweight bus protocol, and waiting for the target register to return 32-bit read data. For example, reading the state machine register yields the current state code hexadecimal 03, indicating the data transmission status; reading the sequence count register yields the current sequence number hexadecimal 000012A5; and reading the head pointer of the transmission queue yields the pointer value hexadecimal 0040, indicating the 64th position in the queue. This invention assembles all read register values ​​into a context data packet according to a fixed format. The data packet structure includes a 4-byte protocol type field, a 4-byte state machine code field, a 4-byte sequence count field, and a 4-byte queue pointer field, totaling 16 bytes of basic context data. For incomplete data pointed to by the queue pointer, this invention additionally reads the corresponding address range of the queue buffer block memory and appends the valid data frames in the queue to the end of the context data packet, forming a complete structured data packet.

[0051] S24: Write the context data packet and the data frame that has not been transmitted into the state cache unit through dual-port access to generate protocol context snapshot data.

[0052] Furthermore, the present invention performs write operations through port A of the dual-port block memory. The address signal of port A is connected to the write address generator. The write address generator maintains an incrementing counter with an initial value of hexadecimal 0000. The counter increments by 1 each time a 32-bit data word is written.

[0053] First, this invention writes the 16-byte basic context data packet sequentially into the block memory in four 32-bit words, with the write address incrementing from hexadecimal 0000 to hexadecimal 0003. Then, this invention calculates the byte length of the incomplete data frame. If the send queue stores 128 bytes of unsent data, then these 128 bytes are written into the block memory in 32 32-bit words, with the write address incrementing from hexadecimal 0004 to hexadecimal 0023.

[0054] After all data has been written, this invention writes a 32-bit timestamp to block memory address hexadecimal 0024. This timestamp value is sampled from a global timestamp counter and records the time when the context snapshot was generated. The write enable signal of block memory port A remains high throughout the write process, and the clock signal uses the configuration manager's operating clock of 100 MHz.

[0055] After the write operation is complete, the present invention writes a checksum field to the block memory address hexadecimal 0025. The checksum is obtained by performing modulo addition on the first 37 words of data and then inverting the result. The checksum field is used in the subsequent recovery phase to verify the integrity of the context data. At this point, the protocol context snapshot data is completely stored in the state cache unit, containing all key information such as the protocol running status, pending data, and timestamps.

[0056] S3: Based on the target protocol type, load the bitstream of the corresponding reconfigurable logical partition by configuring the access port to obtain the reconfigurable protocol module.

[0057] Step S3 further includes: S31: Based on the target protocol type, read the corresponding bitstream file from the storage medium, decompress the bitstream file using a data compression algorithm, and obtain the original configuration data stream.

[0058] Furthermore, this invention locates the bitstream file storage address in the external flash memory chip based on the target protocol type identifier. Specifically, the configuration manager maintains a bitstream file index table, where each entry contains the protocol type identifier, the file start address, and the length. For example, the FC-AE-ASM protocol identifier is hexadecimal 02, and its bitstream file start address is the flash memory offset hexadecimal 00080000.

[0059] This invention sends read commands to the flash memory via a serial peripheral interface. The read bitstream data enters the decompression engine, which uses the LZ4 algorithm and maintains a 64-kilobyte sliding window dictionary to parse the literal bytes and matching pairs of the compressed data blocks. Finally, the literals are output directly, and the matching pairs are used to backtrack through the window to find historical data based on the offset and copy it to the output stream. The decompressed original configuration data stream is stored in a temporary buffer FIFO memory with a depth of 2048 words in 32-bit words.

[0060] S32: Input the original configuration data stream to the internal configuration access port, and control the configuration storage unit of the target reconfigurable logical partition to perform frame-by-frame writing operations through the configuration state machine.

[0061] In step S32, the configuration state machine reads the first 8 words of the original configuration data stream from the temporary buffer FIFO memory, and checks whether it contains the synchronization word hexadecimal AA995566 and the virtual command word hexadecimal 20000000. After confirming the synchronization word, the state machine enters the configuration frame writing stage, reading the subsequent frame address write command hexadecimal 30004000 and the target frame address value. Bits 25 to 23 of the frame address value encode the block type, bits 22 to 17 encode the main row number, bits 16 to 7 encode the column address, and bits 6 to 0 encode the secondary row number.

[0062] Based on the target reconfigurable logical partition physical address range obtained in step S101, this invention converts the physical address into configuration frame coordinates. For example, the frame coordinates corresponding to the starting physical address of the second partition are block type 0, major row number 15, column address 80, and minor row number 0. The state machine sequentially writes the frame address write command and frame coordinate values ​​to the 32-bit data input bus of the internal configuration access port, while simultaneously pulling the write enable signal high for one clock cycle. Next, the state machine reads 101 32-bit configuration words from the temporary buffer. These 101 words constitute a complete configuration frame data, with each word containing the lookup table configuration bits of the logic unit, the initial value of the flip-flops, and the routing resource connection information. The state machine sends these 101 words one by one to the data input bus of the internal configuration access port, pulling the write enable signal high once for each word sent.

[0063] After all 101 words are written, the state machine continues to read the next frame address write command and frame coordinate value, repeating the above frame data writing process. All configuration frames from frame coordinate 0 to frame coordinate 4095 are written sequentially to the configuration storage unit of the target reconfigurable logical partition. The bits of the static random access memory inside the configuration storage unit are overwritten bit by bit, and the original logical configuration of the FC-AE-1553 protocol is completely replaced by the logical configuration of the new FC-AE-ASM protocol.

[0064] S33: Monitor the configuration completion signal. When the bit stream loading is detected to be finished, perform a logical reset on the reconstructed reconfigurable logical partition to obtain the reconstructed protocol module.

[0065] Furthermore, after writing the 101st word of the last configuration frame, the configuration state machine writes a cyclic redundancy check (CRC) command (hexadecimal 30008001) to the internal configuration access port, triggering the configuration completion verification process. The internal configuration access port hardware automatically calculates the CRC value of the written configuration data and compares it with the check value attached to the bitstream file. If the comparison is successful, the configuration completion signal is toggled from low to high. The configuration manager detects the level of the configuration completion signal through polling. When a high level is detected, it writes a start command (hexadecimal 30008001) and a clock enable command (hexadecimal 30018001) to the internal configuration access port, activating the clock tree buffer within the target reconfigurable logical partition.

[0066] Subsequently, the configuration manager sends a logical reset signal to the partition. The reset signal is transmitted through a dedicated reset network to the asynchronous reset terminals of all flip-flops within the partition. The reset signal remains high for 10 clock cycles, forcing the outputs of all flip-flops to zero. The state machine returns to its initial state (hexadecimal 00), and all counters and queue pointers are reset to zero.

[0067] After the reset signal returns to a low level, the reconstructed FC-AE-ASM protocol processing module enters an idle waiting state. At this time, the service identifier mapping unit and priority scheduler inside the module are in a ready state. The ready signal of the input port is pulled high to indicate that data can be received, and the valid signal of the output port is pulled low to indicate that there is no data output. At this point, the hardware logic configuration of the reconstructed protocol module is completed and initialized, forming a protocol module entity with data processing capabilities.

[0068] S4: Read the protocol context snapshot data, restore the state of the reconstructed protocol module, and obtain the target protocol data path.

[0069] Step S4 further includes: S41: Read the protocol context snapshot data from the state cache unit and verify the data validity based on the timestamp information.

[0070] Furthermore, this invention performs read operations through port B of the dual-port block memory. The address signal of port B is connected to a read address generator, which increments sequentially starting from hexadecimal address 0000. First, a 4-byte protocol type field is read from address hexadecimal 0000, a 4-byte state machine code field from address hexadecimal 0001, a 4-byte sequence count field from address hexadecimal 0002, and a 4-byte queue pointer field from address hexadecimal 0003, forming 16 bytes of basic context data. Subsequently, this invention reads a 32-bit timestamp from address hexadecimal 0024, calculates the difference between this timestamp value and the real-time value of the current global timestamp counter, and the difference represents the storage duration of the context snapshot data. If the difference is less than the preset timeout threshold of 100 milliseconds (100,000 microseconds), the data is determined to be within its validity period. Next, this invention reads the checksum field from address hexadecimal 0025, and simultaneously performs modulo addition on the 37 words from address hexadecimal 0000 to hexadecimal 0024. The inverted result is then compared bit-by-bit with the read checksum. If all bits are equal, the check passes. Data validity verification includes two dimensions: timeliness check and integrity check. Only context snapshot data that passes both checks is considered valid data, and the subsequent state recovery process continues. If either check fails, this invention discards the current context data and writes a default initial state value to the reconstruction protocol module to prevent erroneous states from causing protocol processing anomalies.

[0071] S42: Write the state machine parameters and sequence count values ​​from the valid protocol context snapshot data into the internal register of the reconstructed protocol module.

[0072] This invention extracts the 4-byte state machine encoding field from the valid background data. The encoded value, hexadecimal 03, indicates that the original protocol module was in the data transmission state before the switchover. This invention initiates a write operation to the state machine register address (hexadecimal 1000) of the reconstructed protocol module via a lightweight bus protocol, writing the encoded value (hexadecimal 03) into the register. The state machine hardware logic directly jumps to the data transmission state based on the register value, skipping the initialization, handshake, and data reception pre-processing states in the normal flow. Next, this invention extracts the 4-byte sequence count field value (hexadecimal 000012A5) and writes it to the sequence count register address (hexadecimal 1004) of the reconstructed protocol module. The sequence counter continues to increment from hexadecimal 000012A5, maintaining continuity with the sequence number before the switchover. Subsequently, this invention extracts the 4-byte queue pointer field value (hexadecimal 0040) and writes it to the send queue head pointer register address (hexadecimal 1008). The queue management logic will start processing data from the 64th queue position, skipping the first 63 processed positions. All internal register write operations are completed through bus transactions. Each write transaction contains a 32-bit address, 32-bit data, and a write enable control signal. The bus arbiter ensures the atomicity of write operations and prevents register values ​​from being accidentally modified by other modules during state recovery.

[0073] S43: Reload the data frames that have not been transmitted into the input buffer of the reconstruction protocol module according to the queue pointer position.

[0074] In step S43, the present invention calculates the storage location of the incomplete data frame in the context snapshot based on the queue head pointer value (hexadecimal 0040) recovered in step S42. The queue head pointer value is multiplied by the data frame length of 32 bytes and then divided by 4 to obtain the word offset of 512. This offset is then added to the 4 words occupied by the basic context data to obtain the actual read start address (hexadecimal 0204). The present invention reads data continuously starting from the dual-port block memory address (hexadecimal 0204), reading one 32-bit word at a time, and repeating this process 32 times to obtain a 128-byte incomplete data frame.

[0075] During the reading process, data words are sequentially fed into the input buffer FIFO memory of the reconstruction protocol module. The write port of this buffer receives the data stream from the block memory, and the write address pointer automatically increments from the buffer's starting position (hexadecimal 0000). The input buffer has a depth of 512 words, or 2048 bytes, which is sufficient to accommodate multiple incomplete data frames. After all 128 bytes of data have been written to the buffer, this invention writes 128 valid data bytes to the buffer's control register. The buffer's full / empty status determination logic updates the read / write pointer difference based on this value, marking the buffer status as non-empty.

[0076] Finally, after the data processing state machine of the reconstructed protocol module detects the non-empty flag of the input buffer, it extracts the data frame from the buffer read port and continues to process the data frame according to the service identifier mapping and priority scheduling process of the FC-AE-ASM protocol, and the data processing is seamlessly resumed from the interruption position.

[0077] S44: Enable the clock enable signal of the reconfiguration protocol module, establish the connection path between the reconfiguration protocol module and the unified data bus, and generate an activated target protocol data path.

[0078] In step S44, the present invention writes the enable value hexadecimal 00000001 to the clock enable register address hexadecimal 2000 of the reconfiguration protocol module. The 0th bit of this register controls the gate switch of the module's main clock. After receiving the enable signal, the clock gating circuit opens the AND gate logic of the clock path, allowing the 106.25MHz operating clock signal to be transmitted to all timing logic units inside the reconfiguration protocol module.

[0079] Upon arrival of the clock signal, the flip-flops within the module begin to toggle their states on the rising edge of the clock, and the state machine resumes operation from the recovered data transmission state, with the counter incrementing according to the clock tick. Subsequently, this invention configures a multiplexer connecting the reconfigurable protocol module and the unified data bus. The control register address of this multiplexer is hexadecimal 3000. This invention writes the selection value hexadecimal 02 to this address, instructing the multiplexer to connect the output port of the second reconfigurable logic partition to the input port of the unified data bus, and simultaneously connect the output port of the unified data bus to the input port of the second partition. The switch matrix inside the multiplexer reconfigures the data path according to the selection value, establishing a 32-bit data signal connection, a valid signal connection, a ready signal connection, and an end-of-line flag signal connection from the output port of the reconfigurable protocol module to the unified data bus.

[0080] After the connection is established, the FC-AE-ASM protocol data frames output by the reconfiguration protocol module flow to the PCIe interface or other peripheral interfaces through the unified data bus, and externally input data frames are also routed to the input port of the reconfiguration protocol module through the unified data bus. At this point, the target protocol data path is fully activated, the bidirectional data transmission function of the FC-AE-ASM protocol returns to normal operation, and the protocol switching process is complete.

[0081] like Figure 2 As shown, the present invention also provides a multi-protocol dynamic switching system based on FPGA, comprising: An FPGA chip, wherein the internal structure of the FPGA chip is divided into a static logic area and multiple reconfigurable logic partitions; The static logic area includes a global clock management unit, a configuration manager, a unified data bus, and a host interface controller. The configuration manager is connected to each reconfigurable logical partition through an internal configuration access port. Multiple reconfigurable logical partitions, each of which reserves a fixed number of programmable logic units, block memory and digital signal processing units for loading processing logic for different communication protocols; The state buffer unit, consisting of a dual-port block memory, is used to store context snapshot data and incomplete data frames during protocol switching. The clock domain synchronization module includes multiple asynchronous first-in-first-out buffers, which are connected between different reconfigurable logical partitions and a unified data bus to enable data transmission across clock domains.

[0082] The present invention also provides a multi-protocol dynamic switching device based on FPGA, comprising: A memory and at least one processor, wherein the memory stores instructions; At least one of the processors invokes the instructions in the memory to cause an FPGA-based multi-protocol dynamic switching device to execute an FPGA-based multi-protocol dynamic switching method as described in any of the preceding claims.

[0083] The present invention also provides a computer-readable storage medium storing instructions that, when executed by a processor, implement a multi-protocol dynamic switching method based on FPGA as described in any of the preceding claims.

[0084] Furthermore, in the FPGA-based multi-protocol dynamic switching system provided by this invention, the unified data bus adopts a streaming transport bus protocol architecture, including: The data channel signal line transmits a 32-bit wide data payload. The valid signal line indicates whether the data on the data channel is valid. The ready signal line indicates whether the receiver is ready to receive data; The end-of-frame marker line indicates the end of the data frame. The data payload embeds a 4-bit protocol type identifier field and a 32-bit global timestamp field.

[0085] Furthermore, the FPGA field-programmable gate array chip is a Xilinx UltraScale series or 7 series chip, the internal configuration access port is an ICAP primitive module, and the external flash memory chip is a NOR flash memory or a QSPI interface flash memory.

[0086] This invention enables a single hardware platform to rapidly switch between different communication scenarios through microsecond-level dynamic protocol switching capabilities, significantly reducing the hardware deployment costs and space requirements of avionics and intelligent communication systems. Secondly, the system maintains data transmission continuity and state consistency during protocol switching, avoiding data packet loss and service interruptions caused by switching delays in traditional solutions. The on-demand loading of hardware resources improves resource utilization by over 40%, reducing reliance on large-scale FPGA chips. Furthermore, the cross-clock domain data synchronization mechanism ensures reliable data interaction between protocols operating at different frequencies, providing stable and reliable communication guarantees for multi-protocol mixed transmission scenarios, meeting the comprehensive requirements of modern complex systems for flexibility, real-time performance, and reliability.

[0087] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A multi-protocol dynamic switching method based on FPGA, characterized in that, include: S1: Divide the FPGA chip into regions using a layout planning tool to obtain a static logic area and multiple reconfigurable logic partitions; S2: Based on the protocol switching trigger signal, the current protocol module is suspended, the running status data of the current protocol module is written to the status cache unit, and the protocol context snapshot data is obtained; S3: Based on the target protocol type, load the bitstream of the corresponding reconfigurable logical partition by configuring the access port to obtain the reconfigurable protocol module; S4: Read the protocol context snapshot data, restore the state of the reconstructed protocol module, and obtain the target protocol data path.

2. The FPGA-based multi-protocol dynamic switching method according to claim 1, characterized in that, Step S1 further includes: S11: Define the physical boundaries of the static logic area in the FPGA chip, and allocate the global control logic, clock management unit and configuration manager to the static logic area; S12: Based on the number of communication protocol types, the remaining resources of the FPGA chip are divided into multiple spatially independent reconfigurable logic partitions. Each reconfigurable logic partition reserves a fixed number of programmable logic units, block memory, and digital signal processing units. S13: Set an independent operating frequency for each reconfigurable logic partition through clock domain isolation constraints, and establish a clock synchronization interface between the static logic area and the reconfigurable logic partition.

3. The FPGA-based multi-protocol dynamic switching method according to claim 1, characterized in that, Step S2 further includes: S21: Detect the signal type of the protocol switching trigger signal. When the signal type is triggered by an external command, parse the target protocol identifier to obtain the target protocol type. When the signal type is triggered by an event, obtain the target protocol type based on data stream feature pattern matching. S22: Send a data flow pause command to the current protocol module to block the input and output data path of the current protocol module; S23: Extract the state machine parameters, sequence count value, and queue pointer position of the current protocol module through register scan operation, and assemble them into a structured context data packet; S24: Write the context data packet and the data frame that has not been transmitted into the state cache unit through dual-port access to generate protocol context snapshot data.

4. The FPGA-based multi-protocol dynamic switching method according to claim 1, characterized in that, Step S3 further includes: S31: Based on the target protocol type, read the corresponding bitstream file from the storage medium, decompress the bitstream file using a data compression algorithm, and obtain the original configuration data stream; S32: Input the original configuration data stream to the internal configuration access port, and control the configuration storage unit of the target reconfigurable logical partition to perform frame-by-frame writing operations through the configuration state machine. S33: Monitor the configuration completion signal. When the bit stream loading is detected to be finished, perform a logical reset on the reconstructed reconfigurable logical partition to obtain the reconstructed protocol module.

5. The FPGA-based multi-protocol dynamic switching method according to claim 1, characterized in that, Step S4 further includes: S41: Read the protocol context snapshot data from the state cache unit and verify the data validity based on the timestamp information; S42: Write the state machine parameters and sequence count values ​​from the valid protocol context snapshot data into the internal register of the reconstructed protocol module; S43: Reload the data frames that have not been transmitted into the input buffer of the reconstruction protocol module according to the queue pointer position; S44: Enable the clock enable signal of the reconfiguration protocol module, establish the connection path between the reconfiguration protocol module and the unified data bus, and generate an activated target protocol data path.

6. The FPGA-based multi-protocol dynamic switching method according to claim 1, characterized in that, The static logic area is provided with a configuration manager, which is used to control partial reconfiguration. The steps of the configuration manager controlling partial reconfiguration further include: S101: Receive a protocol switching request instruction from the host interface, and parse the protocol switching request instruction to obtain the physical address range of the target reconfigurable logical partition; S102: Generate a configuration frame address sequence according to the physical address range, and write part of the bit stream data into the configuration storage unit of the target reconfigurable logical partition in the order of the configuration frames through the internal configuration access port; S103: During the bitstream loading process, the cyclic redundancy check code of the configuration data is verified in real time. When the verification fails, a reloading mechanism is triggered or the system is rolled back to the previous stable configuration state.

7. The FPGA-based multi-protocol dynamic switching method according to claim 1, characterized in that, Multiple reconfigurable logical partitions correspond to different protocol types within the Fibre Channel protocol family, specifically including: The first reconfigurable logical partition loads the processing logic of the bus-type command response protocol, and generates status response data after parsing the command words; The second reconfigurable logical partition loads the processing logic of the asynchronous service encapsulation protocol, and encapsulates data packets through service identifier mapping and priority scheduling mechanism; The third reconfigurable logical partition loads the processing logic of the video stream transmission protocol, and performs timestamp embedding and isochronous transmission control processing on the video data frames.

8. A multi-protocol dynamic switching system based on FPGA, characterized in that, include: An FPGA chip, wherein the internal structure of the FPGA chip is divided into a static logic area and multiple reconfigurable logic partitions; The static logic area includes a global clock management unit, a configuration manager, a unified data bus, and a host interface controller. The configuration manager is connected to each reconfigurable logical partition through an internal configuration access port. Multiple reconfigurable logical partitions, each of which reserves a fixed number of programmable logic units, block memory and digital signal processing units for loading processing logic for different communication protocols; The state buffer unit, consisting of a dual-port block memory, is used to store context snapshot data and incomplete data frames during protocol switching. The clock domain synchronization module includes multiple asynchronous first-in-first-out buffers, which are connected between different reconfigurable logical partitions and a unified data bus to enable data transmission across clock domains.

9. A multi-protocol dynamic switching device based on FPGA, characterized in that, include: A memory and at least one processor, wherein the memory stores instructions; At least one of the processors invokes the instructions in the memory to cause an FPGA-based multi-protocol dynamic switching device to perform an FPGA-based multi-protocol dynamic switching method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed by a processor, implement a multi-protocol dynamic switching method based on an FPGA as described in any one of claims 1 to 7.

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