Wafer packaging structure and wafer packaging method

Abstract

The invention discloses a wafer packaging structure and a wafer packaging method.The wafer packaging structure comprises a cap and a wafer which are oppositely arranged, a device structure is arranged on the wafer, a sealing ring is arranged between the cap and the wafer, and therefore a sealing cavity is defined by a metal layer and an organic material layer in the cap, the sealing ring and the wafer; the metal layer in the cap comprises a first metal region and a plurality of second metal regions which are insulated from each other, the second metal regions are electrically connected with the device structure through metal bumps, and metal balls electrically connected with an external power supply are arranged on the second metal regions; therefore, the device structure obtains the electric energy of an external power supply through the metal bumps, the second metal regions and the metal balls, breaks through the existing MEMS wafer level packaging mode, optimizes the process flow, shortens the process time, reduces the cost, and improves the production efficiency. In addition, the metal protruding block is located in the sealing cavity and can support the cap structure, so that the cap structure is firm and stable.

Description

[0001] This application claims priority to Chinese Patent Application No. 202410867198.7, filed on June 28, 2024, entitled “Wafer Packaging Structure and Wafer Packaging Method”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor wafer packaging technology, and in particular to a wafer packaging structure and wafer packaging method. Background Technology

[0003] Wafer-level packaging (WLP) is a technology that directly packages chips onto a wafer during the wafer manufacturing process. This facilitates chip miniaturization and high integration. Specifically, wafer-level packaging of semiconductor chips yields semiconductor wafer package structures. For example, Micro-Electro-Mechanical Systems (MEMS) are miniature systems integrating micro-mechanical structures, electronic circuits, and sensors. MEMS packaging structures protect and encapsulate MEMS chips to ensure their performance and reliability. Current MEMS wafer-level packaging primarily involves covering the MEMS wafer with a silicon cap via a packaging ring to form a sealed cavity. The device structures on the MEMS wafer are then placed within this sealed cavity. A through-silicon via (TSV) process is then performed on the silicon cap to expose the device structure's pads, allowing for redistribution layer (RDL) routing.

[0004] It is evident that the existing through-silicon via (TSV) and redistribution line (RDL) processes in MEMS wafer-level packaging result in relatively complex processes, high costs, and low production efficiency. Summary of the Invention

[0005] To address the aforementioned technical problems, embodiments of this application provide a wafer packaging structure and a wafer packaging method to break through existing MEMS wafer-level packaging methods, optimize the process flow, shorten process time, reduce costs, and improve production efficiency.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] According to a first aspect of this application, a wafer packaging structure includes:

[0008] A cap and a wafer are positioned opposite each other, and a device structure is disposed on the wafer, the device structure being located between the cap and the wafer;

[0009] The cap includes a metal layer and an organic material layer. The metal layer includes a first metal region and a plurality of second metal regions, and an insulating region is provided between the first metal region and the second metal regions.

[0010] A sealing ring is located between the cap and the wafer. The metal layer and the organic material layer in the cap, the sealing ring, and the wafer form a sealed cavity, and the device structure is located within the sealed cavity.

[0011] A metal bump is located between the second metal region and the device structure, and the second metal region is electrically connected to the device structure through the metal bump;

[0012] A metal ball is disposed on the surface of the second metal region away from the wafer. The metal ball is electrically connected to an external power source. The device structure obtains electrical energy from the external power source through the metal bump, the second metal region, and the metal ball.

[0013] According to a second aspect of this application, a wafer packaging method includes:

[0014] A wafer is provided, on which a device structure is disposed;

[0015] The wafer and the device structure are packaged at the wafer level to form a wafer package structure. In addition to the wafer and the device structure, the wafer package structure also includes a cap disposed opposite to the wafer, and the device structure is located between the cap and the wafer.

[0016] The cap includes a metal layer and an organic material layer. The metal layer includes a first metal region and a plurality of second metal regions, and an insulating region is provided between the first metal region and the second metal regions.

[0017] A sealing ring is provided between the cap and the wafer. The metal layer and the organic material layer in the cap, the sealing ring and the wafer form a sealed cavity, and the device structure is located in the sealed cavity.

[0018] A metal bump is provided between the second metal region and the device structure, and the second metal region is electrically connected to the device structure through the metal bump;

[0019] A metal ball is disposed on the surface of the second metal region away from the wafer. The metal ball is electrically connected to an external power source. The device structure obtains electrical energy from the external power source through the metal bump, the second metal region, and the metal ball.

[0020] Compared with existing technologies, the above technical solution has the following advantages:

[0021] The wafer packaging structure provided in this application includes a cap and a wafer disposed opposite to each other. A device structure is disposed on the wafer and is located between the cap and the wafer. The cap includes a metal layer and an organic material layer. A sealing ring is disposed between the cap and the wafer, so that the metal layer and organic material layer in the cap, the sealing ring and the wafer form a sealed cavity, so that the device structure is located in the sealed cavity. Furthermore, the metal layer in the cap includes a first metal region and a plurality of second metal regions. The first metal region and the second metal region are insulated and isolated by an insulating region between them. A metal bump is disposed between the second metal region and the device structure, so that the second metal region is electrically connected to the device structure through the metal bump. At the same time, a metal ball electrically connected to an external power source is disposed on the surface of the second metal region facing away from the wafer, so that the device structure obtains electrical energy from the external power source through the metal bump, the second metal region and the metal ball.

[0022] Therefore, compared to existing technologies that require silicon caps or through-silicon via (TSV) processes on the wafer to achieve electrical connection between the device structure and the external power supply, the wafer packaging structure provided in this application sets the cap to include a metal layer and an organic material layer. On the one hand, the combination of the metal layer and the organic material layer realizes the function of the cap as a sealing ring and the wafer forming a sealed cavity to seal the device structure. On the other hand, by simply dividing the metal layer in the cap into a first metal region and multiple second metal regions that are insulated from each other, the second metal regions can be electrically connected to the device structure through metal bumps, and electrically connected to the external power supply through metal balls, ultimately achieving electrical connection between the device structure and the external power supply. This breaks through the existing MEMS wafer-level packaging methods, optimizes the process flow, shortens the process time, reduces costs, and improves production efficiency. Furthermore, the metal bumps are located inside the sealed cavity, thereby supporting the cap structure and making the cap structure robust and stable.

[0023] Other objects and advantages of this application will be described in detail in conjunction with the accompanying drawings in the following embodiments. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a cross-sectional schematic diagram of a wafer packaging structure provided in an embodiment of this application;

[0026] Figure 2 for Figure 1 A top view of the wafer packaging structure shown.

[0027] Figure 3 This is a cross-sectional schematic diagram of another wafer packaging structure provided in the embodiments of this application;

[0028] Figure 4 This is a cross-sectional schematic diagram of another wafer packaging structure provided in the embodiments of this application;

[0029] Figure 5 This is a cross-sectional schematic diagram of another wafer packaging structure provided in the embodiments of this application;

[0030] Figure 6 This is a cross-sectional schematic diagram of a wafer and the device structure on the wafer;

[0031] Figures 7a-7n In a wafer packaging method provided in an embodiment of this application, for Figure 6 The diagram shows the structural schematics corresponding to each process step in wafer-level packaging of the wafer and the device structure on the wafer.

[0032] Figures 8a-8g In another wafer packaging method provided in the embodiments of this application, for Figure 6 The diagram shows the structural schematics corresponding to each process step in wafer-level packaging of the wafer and the device structure on the wafer.

[0033] Figure label:

[0034] 10-Cap, 101-Flat portion, 102-Protrusion, 11-Metal layer, 111-First metal region, 112-Second metal region, 113-Insulating region, 12-Organic material layer, 121-First organic material layer, 122-Second organic material layer, 20-Wafer, 21-Device structure, 211-Device body, 212-Pad, 30-Sealing ring, Q1-Sealing cavity, 40-Metal bump, 41-First part, 42-Second part, 401-Seed layer, 4011-First seed layer, 4012-Second seed layer, 402-First metal layer, 403-Second metal layer, 404-Third metal layer, 405-Electroplated adhesive layer, 50-Metal ball, 100-First substrate, 110-First sacrificial layer, 120-Second sacrificial layer, T1-Groove, K1-First through hole, K2-Second through hole. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0037] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0038] As described in the background section, the existing through-silicon via (TSV) and redistribution line (RDL) processes in MEMS wafer-level packaging make the process flow relatively complex, costly, and inefficient.

[0039] In view of this, embodiments of this application provide a wafer packaging structure. Figure 1 A cross-sectional schematic diagram of a wafer packaging structure provided in an embodiment of this application is shown, as follows: Figure 1 As shown, the wafer packaging structure includes a cap 10 and a wafer 20 disposed opposite to each other. A device structure 21 is disposed on the wafer 20 and is located between the cap 10 and the wafer 20.

[0040] like Figure 1 As shown, the cap 10 includes a metal layer 11 and an organic material layer 12. A sealing ring 30 is provided between the cap 10 and the wafer 20. Thus, the metal layer 11 and the organic material layer 12, the sealing ring 30 and the wafer 20 in the cap 10 form a sealed cavity Q1, so that the device structure 21 is located in the sealed cavity Q1.

[0041] like Figure 1 As shown, the metal layer 11 in the cap 10 includes a first metal region 111 and a plurality of second metal regions 112. An insulating region 113 is provided between the first metal region 111 and the second metal region 112, that is, the first metal region 111 and the second metal region 112 are insulated and isolated by the insulating region 113 between them. A metal bump 40 is provided between the second metal region 112 and the device structure 21, so that the second metal region 112 is electrically connected to the device structure 21 through the metal bump 40. At the same time, a metal ball 50 is provided on the surface of the second metal region 112 away from the wafer 20, and the metal ball 50 is electrically connected to an external power source, so that the second metal region 112 is electrically connected to the external power source through the metal ball 50. Thus, the device structure 21 is electrically connected to the external power source in sequence through the metal bump 40, the second metal region 112 and the metal ball 50, and obtains electrical energy from the external power source.

[0042] Therefore, compared to existing technologies that require silicon caps or through-silicon via (TSV) processes on wafers to achieve electrical connection between the device structure and the external power supply, the wafer packaging structure provided in this application provides a cap 10 comprising a metal layer 11 and an organic material layer 12. On one hand, the combination of the metal layer 11 and the organic material layer 12 serves as a cap, forming a sealed cavity Q1 with the sealing ring 30 and the wafer 20 to seal the device structure 21. On the other hand, by dividing the metal layer 11 in the cap 10 into a first metal region 111 and multiple second metal regions 112 that are insulated from each other, the second metal regions 112 can be electrically connected to the device structure 21 via metal bumps 40, and electrically connected to the external power supply via metal balls 50, ultimately achieving electrical connection between the device structure 21 and the external power supply. This breaks through the existing MEMS wafer-level packaging methods, optimizes the process flow, shortens the process time, reduces costs, and improves production efficiency. Furthermore, the metal bump 40 is located inside the sealing cavity Q1, thereby supporting the cap structure and making the cap structure firm and stable.

[0043] In the embodiments of this application, the device structure 21 can be a MEMS chip, but is not limited to a MEMS chip, and can also be other semiconductor chips. This application does not limit the device structure 21.

[0044] In practical applications, such as Figure 1 As shown, the device structure 21 includes a device body 211 and pads 212. The device body 211 is electrically led out through the pads 212. That is, the device structure 21 is electrically connected to an external power source through metal bumps 40, a second metal region 112 and metal balls 50.

[0045] Since the device structure 21 typically includes multiple pads 212, correspondingly, the metal layer 11 in the cap 10 includes multiple second metal regions 112. The pads 212 and the second metal regions 112 correspond one-to-one, and the corresponding pads 212 and second metal regions 112 are electrically connected through metal bumps 40. Furthermore, the second metal regions 112 and the metal balls 50 are also electrically connected one-to-one.

[0046] Figure 2 Further shown Figure 1 The diagram shows a top view of the wafer packaging structure. Figure 2 The diagram shows four metal spheres, 50, combined with... Figure 1 As shown, each of the four metal spheres 50 corresponds to a second metal region 112 and a metal bump 40, but this application does not limit the number of second metal regions 112. Furthermore, from... Figure 2As can be seen, the sealing ring 30 is arranged around the device structure 21 to seal it within the sealing cavity Q1. Figure 1 Can be seen as Figure 2 Cross-sectional view in the AA' direction.

[0047] In the embodiments of this application, in the metal layer 11 of the cap 10, the insulating region 113 between the first metal region 111 and the second metal region 112 can be air or other insulating materials, and this application does not limit it.

[0048] In this embodiment of the application, the cap 10 includes a metal layer 11 and an organic material layer 12. In addition to combining with the metal layer 11 to achieve the function of a cap, the organic material layer 12 can also protect the metal layer 11. At the same time, the metal layer 11 can also provide mechanical support for the organic material layer 12, enhance the mechanical structural strength of the organic material layer 12, and make the cap structure more stable and firm.

[0049] It should be noted that this application does not limit the stacking relationship between the metal layer 11 and the organic material layer 12. Optionally, such as... Figure 3 As shown, the organic material layer 12 may include a first organic material layer 121 located on the side of the metal layer 11 near the wafer 20; alternatively, such as Figure 4 As shown, the organic material layer 12 may include a second organic material layer 122 located on the side of the metal layer 11 opposite to the wafer 20; alternatively, such as Figure 1 As shown, the organic material layer 12 may simultaneously include a first organic material layer 121 and a second organic material layer 122 located on opposite sides of the metal layer 11 along the thickness direction. Specific embodiments are described below.

[0050] Optional, such as Figure 3 As shown, the organic material layer 12 includes a first organic material layer 121 located on the side of the metal layer 11 close to the wafer 20. At this time, the first organic material layer 121 can extend from the surface of the first metal region 111 through the insulating region 113 to a part of the surface of the second metal region 112. The surface of the second metal region 112 exposed by the first organic material layer 121 corresponds to the first through hole K1 penetrating the first organic material layer 121. The metal bump 40 is embedded in the first through hole K1. Thus, the first organic material layer 121 and the metal layer 11 are combined to realize the capping effect and form a sealing cavity Q1 sealing device structure 21 with the sealing ring 30 and the wafer 20. Furthermore, the metal bump 40 passes through the first organic material layer 121 and is electrically connected to the second metal region 112.

[0051] Another option, such as Figure 4As shown, the organic material layer 12 includes a second organic material layer 122 located on the side of the metal layer 11 away from the wafer 20. At this time, the second organic material layer 122 extends from the surface of the first metal region 111 through the insulating region 113 to a part of the surface of the second metal region 112. The exposed surface of the second metal region 112 of the second organic material layer 122 corresponds to the second through hole K2 penetrating the second organic material layer 122. The metal ball 50 is embedded in the second through hole K2. Thus, the second organic material layer 122 and the metal layer 11 are combined to realize the capping effect and form a sealing cavity Q1 sealing device structure 21 with the sealing ring 30 and the wafer 20. Furthermore, the second metal region 112 is electrically connected to the external power supply through the metal ball 50 penetrating the second organic material layer 122.

[0052] Another option, such as Figure 1 As shown, the organic material layer 12 simultaneously includes a first organic material layer 121 and a second organic material layer 122 located on opposite sides of the metal layer 11 along its thickness direction. In this case, one possibility is that the first organic material layer 121 extends from the surface of the first metal region 111 through the insulating region 113 to a portion of the surface of the second metal region 112. The exposed surface of the second metal region 112 of the first organic material layer 121 corresponds to the first through-hole K1 penetrating the first organic material layer 121, and the metal bump 40 is embedded in the first through-hole K1. In this case, since the first organic material layer 121 can already be combined with the metal layer 11 to achieve a capping effect and form a sealing cavity Q1 sealing device structure 21 with the sealing ring 30 and the wafer 20, the second organic material layer 122 can extend only on the surface of the first metal region 111. However, in this case, the second organic material layer 122 can also be... Figure 4 As shown, a portion of the surface of the first metal region 111 extends through the insulating region 113 to the surface of the second metal region 112. The exposed surface of the second metal region 112 of the second organic material layer 122 corresponds to the second through hole K2 penetrating the second organic material layer 122, and the metal ball 50 is embedded in the second through hole K2.

[0053] It is conceivable that when the organic material layer 12 simultaneously includes a first organic material layer 121 and a second organic material layer 122 located on opposite sides of the metal layer 11 along the thickness direction, another possibility is that the second organic material layer 122 is as follows: Figure 4As shown, the surface of the first metal region 111 extends through the insulating region 113 to a portion of the surface of the second metal region 112. The exposed surface of the second organic material layer 122 of the second metal region 112 corresponds to the second through-hole K2 penetrating the second organic material layer 122. The metal ball 50 is embedded in the second through-hole K2. In this case, since the second organic material layer 122 can be combined with the metal layer 11 to achieve a capping effect and form a sealing cavity Q1 sealing device structure 21 with the sealing ring 30 and the wafer 20, the first organic material layer 121 can extend only on the surface of the first metal region 111. However, in this case, the first organic material layer 121 can also be as follows: Figure 1 and Figure 3 As shown, a portion of the surface of the first metal region 111 extends through the insulating region 113 to the surface of the second metal region 112. The surface of the second metal region 112 exposed by the first organic material layer 121 corresponds to the first through hole K1 penetrating the first organic material layer 121. The metal bump 40 is embedded in the first through hole K1.

[0054] Compared with the above embodiments, it can be understood that the organic material layer 12 includes two organic material layers located on opposite sides of the metal layer 11 along the thickness direction. Compared with the single organic material layer located on one side of the metal layer 11 along the thickness direction, the protection of the metal layer 11 is more comprehensive. Furthermore, the metal layer 11 can provide mechanical support for the two organic material layers, enhance the mechanical structural strength of the two organic material layers, and make the cap structure more stable and robust.

[0055] It should be noted that the first organic material layer 121 extending to a portion of the surface of the second metal region 112 refers to the portion of the first organic material layer 121 extending to the surface of the second metal region 112 facing the wafer 20, so that the first organic material layer 121 and the metal layer 11 combine to achieve a capping effect and form a sealing cavity Q1 sealing device structure 21 with the sealing ring 30 and the wafer 20; similarly, the second organic material layer 122 extending to a portion of the surface of the second metal region 112 refers to the second organic material layer 122 extending to the surface of the second metal region 112 away from the wafer 20, so that the second organic material layer 122 and the metal layer 11 combine to achieve a capping effect and form a sealing cavity Q1 sealing device structure 21 with the sealing ring 30 and the wafer 20.

[0056] It should also be noted that when the organic material layer 12 includes a first organic material layer 121 and a second organic material layer 122 located on opposite sides of the metal layer 11 along the thickness direction, the materials of the first organic material layer 121 and the second organic material layer 122 may be the same or different. The material of the first organic material layer 121 may include polyimide (PI) or a patternable epoxy resin material.

[0057] It should also be noted that, in order to improve the mechanical support effect of the metal layer 11 on the organic material layer, the material of the metal layer 11 can be a metal with high hardness, such as copper, nickel, gold or nickel-gold alloy. Among them, nickel and gold have oxidation resistance, and nickel in particular has a higher hardness than most metal materials and is less likely to be oxidized. Therefore, when the material of the metal layer 11 is nickel, gold or nickel-gold alloy, the mechanical support effect on the organic material layer is better and it is not easily oxidized and deformed.

[0058] The organic material layer 12 includes at least a first organic material layer 121 located on the side of the metal layer 11 near the wafer 20, and the first organic material layer 121 extends from the surface of the first metal region 111 through the insulating region 113 to a portion of the surface of the second metal region 112. The exposed surface of the second metal region 112 of the first organic material layer 121 corresponds to a first through-hole K1 penetrating the first organic material layer 121. Based on the metal bump 40 being embedded in the first through-hole K1, further, as... Figure 1 and Figure 3 As shown, the metal bump 40 includes a first part 41 embedded in the first through hole K1 and a second part 42 protruding from the first through hole K1. The orthographic projection of the first part 41 on the plane where the wafer 20 is located is located within the orthographic projection of the second part 42 on the plane where the wafer 20 is located. That is to say, the second part 42 will also contact the part of the surface of the first organic material layer 121 facing the wafer 20. Thus, the metal bump 40 not only serves to connect the device structure 21 and the second metal region 112, but also serves to support the first organic material layer 121 and the overall cap structure, making the cap structure more stable and firm.

[0059] like Figure 1 , Figure 3 and Figure 4 As shown, the metal bump 40 includes multiple metal layers disposed along the direction from the second metal region 112 toward the device structure 21. The multiple metal layers include a seed layer 401, a first metal layer 402, a second metal layer 403, and a third metal layer 404. In the actual fabrication process, the seed layer 401 is usually deposited first, which may include a first seed layer-titanium layer and a second seed layer-copper layer. Then, the first metal layer 402, the second metal layer 403, and the third metal layer 404 are formed by electroplating. The first metal layer 402 can be a copper layer, the second metal layer 403 can be a nickel layer, and the third metal layer 404 can be a tin layer or a silver-tin layer. After etching away the excess seed layer 401, metal bump reflow is performed to finally form the metal bump 40. Subsequently, the metal bump 40 is bonded to the device structure 21.

[0060] The inventors discovered that, since there are multiple metal bumps 40, and after the reflow process, due to limitations in the electroplating equipment's capabilities, as well as issues such as the uniformity of the photolithographic plating and differences in openings, the heights of the individual metal bumps 40 are not entirely consistent. This may cause some metal bumps 40 to fail to bond properly to the device structure 21, resulting in differences in wafer coplanarity. Therefore, optionally, in some embodiments of this application, the heights of all metal bumps 40 are set to be equal to improve wafer coplanarity and surface flatness, thereby enhancing the bonding strength between the device structure 21 and the metal bumps 40 on the wafer 20.

[0061] The inventors also discovered that the sealing ring 30 is typically made of metal. After the reflow process, the heights of the metal sealing ring and the metal bumps 40 become unequal, which undoubtedly exacerbates the difference in wafer coplanarity height. Therefore, optionally, in some embodiments of this application, the sealing ring 30 is no longer made of metal; that is, the material of the sealing ring 30 is different from that of the metal bumps 40. Specifically, the material of the sealing ring 30 includes organic materials, such as epoxy resin. This makes it easier to control the height of the sealing ring 30, thereby reducing the height difference between the sealing ring 30 and the metal bumps 40, improving wafer coplanarity, increasing wafer surface flatness, and enhancing the bonding strength between the device structure 21 on wafer 20 and the metal bumps 40, as well as the bonding strength between wafer 20 and the sealing ring 30.

[0062] exist Figure 1 , Figure 3 as well as Figure 4 In the wafer packaging structure shown, the cap 10 is set flat along the horizontal direction of the wafer 20. In this case, the height of the sealing ring 30 should be as equal as possible to the height of the metal bump 40. As mentioned above, the material of the sealing ring 30 is an organic material, such as epoxy resin, so that the height of the sealing ring 30 can be controlled so that the height of the sealing ring 30 is equal to the height of the metal bump 40, thereby improving the coplanarity of the wafer and the flatness of the wafer surface, and thus improving the wafer bonding strength.

[0063] Considering that organic materials are generally coated by spin coating or spray coating, if the height of the sealing ring 30 is not too high, such as not exceeding 35μm, the height of the sealing ring 30 can be controlled so that the height of the sealing ring 30 is equal to the height of the metal bump 40. If the height of the sealing ring 30 is too high, the coating method will result in uneven height of the upper surface of the organic material, which will also lead to poor coplanarity of the wafer surface and affect the bonding of the wafer.

[0064] Based on this, further options include, for example Figure 5As shown, the cap 10 is not flat along the horizontal direction of the wafer 20, but includes a flat portion 101 along the horizontal direction of the wafer 20 and a protrusion 102 away from the direction of the wafer 20. The device structure 21 and the metal bump 40 are located between the protrusion 102 and the wafer 20, and the sealing ring 30 is located between the flat portion 101 and the wafer 20. With this arrangement, the height difference between the protrusion 102 and the flat portion 101 replaces part of the height of the sealing ring 30, so that the height of the sealing ring 30 can be less than the height of the metal bump 40, or in other words, the height of the sealing ring 30 is reduced. Therefore, when organic materials are coated by spin coating or spray coating to form the sealing ring 30, the height of the sealing ring 30 is easier to control, and the surface of the sealing ring 30 is relatively flatter, improving the coplanarity of the wafer and the flatness of the wafer surface, enhancing the bonding strength between the device structure 21 and the metal bump 40 on the wafer 20, and the bonding strength between the wafer 20 and the sealing ring 30.

[0065] In the above embodiment, the height of the sealing ring 30 is less than the height of the metal bump 40, and the height range of the sealing ring 30 can be 5μm-15μm, including the endpoint value.

[0066] In general, the height of the sealing ring 30 is less than or equal to the height of the metal bump 40, and the height range of the sealing ring 30 can be 5μm-35μm, including the end values.

[0067] Accordingly, embodiments of this application also provide a wafer packaging method, which includes:

[0068] S10: As Figure 6 As shown, a wafer 20 is provided, on which a device structure 21 is disposed.

[0069] The device structure 21 includes a device body 211 and a pad 212, with the device body 211 electrically led out through the pad 212.

[0070] S20: Combination Figure 1 , Figure 3 and Figure 4 As shown, wafer 20 and device structure 21 are packaged at the wafer level to form a wafer package structure. In addition to wafer 20 and device structure 21, the wafer package structure also includes a cap 10 disposed opposite to wafer 20, and device structure 21 is located between cap 10 and wafer 20.

[0071] The cap 10 includes a metal layer 11 and an organic material layer 12. The metal layer 11 includes a first metal region 111 and a plurality of second metal regions 112. An insulating region 113 is provided between the first metal region 111 and the second metal region 112.

[0072] A sealing ring 30 is provided between the cap 10 and the wafer 20. The metal layer 11 and organic material layer 12 in the cap 10, the sealing ring 30 and the wafer 20 form a sealed cavity Q1, and the device structure 21 is located in the sealed cavity Q1.

[0073] A metal bump 40 is provided between the second metal region 112 and the device structure 21, and the second metal region 112 is electrically connected to the device structure 21 through the metal bump 40.

[0074] A metal ball 50 is disposed on the surface of the second metal region 112 away from the wafer 20. The metal ball 50 is electrically connected to an external power source. The device structure 21 obtains electrical energy from the external power source through the metal bump 40, the second metal region 112 and the metal ball 50.

[0075] In practical applications, such as Figure 1 As shown, the device structure 21 is electrically connected to an external power source through the metal bump 40, the second metal region 112 and the metal ball 50. That is, the device body 211 is electrically connected to an external power source through the pad 212, the metal bump 40, the second metal region 112 and the metal ball 50.

[0076] Since the device structure 21 typically includes multiple pads 212, correspondingly, the metal layer 11 in the cap 10 includes multiple second metal regions 112. The pads 212 and the second metal regions 112 correspond one-to-one, and the corresponding pads 212 and second metal regions 112 are electrically connected through metal bumps 40. Furthermore, the second metal regions 112 and the metal balls 50 are also electrically connected one-to-one.

[0077] In the embodiments of this application, in the metal layer 11 of the cap 10, the insulating region 113 between the first metal region 111 and the second metal region 112 can be air or other insulating materials, and this application does not limit it.

[0078] It should be noted that this application does not limit the stacking relationship between the metal layer 11 and the organic material layer 12. Optionally, such as... Figure 3 As shown, the organic material layer 12 may include a first organic material layer 121 located on the side of the metal layer 11 near the wafer 20; alternatively, such as Figure 4 As shown, the organic material layer 12 may include a second organic material layer 122 located on the side of the metal layer 11 opposite to the wafer 20; alternatively, such as Figure 1 As shown, the organic material layer 12 may simultaneously include a first organic material layer 121 and a second organic material layer 122 located on opposite sides of the metal layer 11 along the thickness direction.

[0079] The following is based on Figure 1Taking the example of the organic material layer 12 shown, which includes a first organic material layer 121 and a second organic material layer 122 located on opposite sides of the metal layer 11 along the thickness direction, this paper details how to perform wafer-level packaging of wafer 20 and device structure 21. Based on this, those skilled in the art can conceive of the case where the organic material layer 12 only includes the first organic material layer 121 or only includes the second organic material layer 122, which will not be elaborated further.

[0080] Specifically, step S20, which involves wafer-level packaging of the wafer 20 and the device structure 21, includes:

[0081] S21: As Figure 7a As shown, a first substrate 100 is provided.

[0082] The first substrate 100 can be a silicon substrate.

[0083] S22: As Figure 7b As shown, a first sacrificial layer 110 and a second sacrificial layer 120 are sequentially formed on the first substrate 100, and a metal layer 11 is formed on the second sacrificial layer 102.

[0084] The material of the first sacrificial layer 110 can be a ternary compound material PSG composed of silicon, oxygen and phosphorus, or silicon dioxide. The thickness of the first sacrificial layer 110 can be around 1000 Å. The first sacrificial layer 110 can serve as an etching barrier layer when the first substrate 100 is subsequently removed.

[0085] The material of the second sacrificial layer 120 can be titanium, and its thickness can be between 1000 Å and 3000 Å.

[0086] The material of the metal layer 11 may include copper, nickel, gold or nickel-gold alloy, and its thickness may be between 1 μm and 3 μm.

[0087] S23: As Figure 7c As shown, a first organic material layer 121 is formed on the metal layer 11, and a first through hole K1 is formed by etching the first organic material layer 121.

[0088] Specifically, a first organic material layer 121 can be formed by coating a polyimide material (PI adhesive) or a patternable epoxy resin material on the surface of the metal layer 11. The thickness of the first organic material layer 121 can be between 5μm and 15μm. After photolithography exposure and development of the first organic material layer 121, a first through hole K1 is formed through the first organic material layer 121. The first through hole K1 is the opening for subsequent electroplating of metal bumps.

[0089] S24: As Figures 7d-7g As shown, a metal bump 40 is formed at the first through hole K1.

[0090] Specifically, forming a metal bump 40 at the first through hole K1 includes:

[0091] S241: As Figure 7d As shown, a seed layer 401 is deposited on the first organic material layer 121, and the seed layer 401 is embedded in the first through hole K1.

[0092] The seed layer 401 may include a first seed layer 4011 - a titanium layer and a second seed layer 4012 - a copper layer. The thickness of the titanium layer may be approximately 1000 Å - 3000 Å, and the thickness of the copper layer may be approximately 5000 Å - 1 μm.

[0093] S242: As Figure 7e As shown, a photolithography electroplating resist layer 405 is coated on the seed layer 401. The photolithography electroplating resist layer 405 is exposed and developed to form a third through hole K3. The orthographic projection of the first through hole K1 onto the plane of the first substrate 100 is located within the orthographic projection of the third through hole K3 onto the plane of the first substrate 100, that is, the third through hole K3 exposes the first through hole K1.

[0094] S243: As Figure 7f As shown, a first metal layer 402, a second metal layer 403, and a third metal layer 404 are sequentially electroplated on the seed layer 401 exposed by the third through hole K3.

[0095] The first metal layer 402 can be a copper layer with a thickness between 10μm and 30μm, the second metal layer 403 can be a nickel layer with a thickness between 5μm and 10μm, and the third metal layer 404 can be a tin layer or a silver-tin alloy layer or other metal layers with a low melting point with a thickness between 5μm and 10μm.

[0096] S244: As Figure 7g As shown, the electroplated adhesive layer 405 is peeled off by a wet process, and the excess seed layer 401 is etched by a wet process. Then, the process is repeated to obtain the metal bump 40.

[0097] As can be seen, the metal bump 40 includes a first part 41 embedded in the first through hole K1 and a second part 42 protruding from the first through hole K1. The orthographic projection of the first part 41 on the plane where the wafer 20 is located is located within the orthographic projection of the second part 42 on the plane where the wafer 20 is located. That is to say, the second part 42 will also contact the part of the surface of the first organic material layer 121 facing the wafer 20. Thus, the metal bump 40 not only serves to connect the device structure 21 and the second metal region 112, but also serves to support the first organic material layer 121 and the overall cap structure, making the cap structure more stable and firm.

[0098] Optionally, the height of each metal bump 40 can be set to be equal, so as to improve the coplanarity of the wafer and the flatness of the wafer surface after subsequent bonding with the wafer, and enhance the bonding strength between the device structure on the wafer and the metal bump.

[0099] S25: As Figure 7h As shown, a sealing ring 30 is formed on the first organic material layer 121 surrounding the metal bump 40.

[0100] Optionally, the sealing ring 30 can be a metal sealing ring.

[0101] Alternatively, the sealing ring 30 may be made of an organic material. In this case, the sealing ring 30 may be formed by a coating method. Specifically, an organic material may be coated on a first organic material layer 121 around the metal bump 40, and then the coated organic material may be photolithographically formed to form the sealing ring 30. In this way, the height of the sealing ring 30 is easier to control, so as to reduce the height difference between the sealing ring 30 and the metal bump 40.

[0102] S26: As Figure 7i As shown, the metal bump 40 and the device structure 21 are bonded together, and the sealing ring 30 is bonded together with the wafer 20 to form a sealing cavity Q1.

[0103] As described above, a first sacrificial layer 110, a second sacrificial layer 120, a metal layer 11, a first organic material layer 121, a metal bump 40, and a sealing ring 30 are formed on the first substrate 100 to form a first structure. The wafer 20 and the device structure 21 on the wafer 20 form a second structure. The side of the first structure with the metal bump 40 and the sealing ring 30 is opposite to the side of the second structure with the device structure 21, thereby correspondingly bonding the metal bump 40 and the device structure 21, and correspondingly bonding the sealing ring 30 to the wafer 20.

[0104] Specifically, the first and second structures are aligned using a bonding alignment machine. The bonding degree is set within the bonding alignment machine. For example, first, a vacuum is drawn and the temperature is raised to about 150°C, the working temperature of the bonding adhesive. Then, pressure is applied to about 10KN and held for 5-15 minutes. The temperature is then raised to the eutectic bonding temperature, which needs to be set according to the melting point of the metal bump 40. If the temperature exceeds the melting point of the metal bump 40 by 10%, the bonding temperature should be set between 230°C and 250°C. After bonding, the pressure is held for 15-20 minutes, and finally the temperature is lowered to room temperature to complete the bonding.

[0105] It should be noted that, since the metal bump 40 and device structure 21 need to be bonded together, and the sealing ring 30 and wafer 20 also need to be bonded together, optionally, the bonding connection of the metal bump 40 and device structure 21 and the bonding connection of the sealing ring 30 and wafer 20 can be performed separately; alternatively, the sealing ring 30 and wafer 20 can be bonded together simultaneously when the metal bump 40 and device structure 21 are bonded together. This can reduce process steps, shorten process time, and improve production efficiency. In this case, the material selection of the metal bump 40, the material selection of the sealing ring 30, and the temperature settings for the synchronous bonding connection of the metal bump 40 and device structure 21 and the sealing ring 30 and wafer 20 need to be coordinated to achieve the synchronous bonding connection of the metal bump 40 and device structure 21 and the sealing ring 30 and wafer 20 in the same bonding process. Optionally, the sealing ring 30 may be made of organic materials, and the metal bump 40 may be made of copper, nickel, or tin or silver-tin alloy. The temperature range for synchronously bonding the metal bump 40, device structure 21, and sealing ring 30 to wafer 20 may be 200°C to 280°C, including endpoint values.

[0106] S27: As Figures 7j-7l As shown, the first substrate 100, the first sacrificial layer 110 and the second sacrificial layer 120 are removed to expose the metal layer 11.

[0107] Specifically, such as Figure 7j As shown, the first substrate 100 is first thinned by grinding, and the thickness can be reduced to 30μm-80μm; then, as... Figure 7k As shown, the remaining first substrate 100 is etched away using dry etching, and the first sacrificial layer 110 serves as an etching barrier layer; subsequently, as... Figure 7l As shown, wet etching removes the first sacrificial layer 110 and the second sacrificial layer 120, exposing the metal layer 11.

[0108] S28: As Figure 7m As shown, the exposed metal layer 11 is etched to form a first metal region 111 and a plurality of second metal regions 112. The first metal region 111 and the second metal region 112 are spaced apart to form an insulating region 113.

[0109] Specifically, a photoresist layer is coated on the metal layer 11, and the photoresist layer is exposed and developed to expose the opening to be etched. The exposed metal layer 11 is etched by a wet process to form a first metal region 111 and a plurality of second metal regions 112. The first metal region 111 and the second metal region 112 are insulated and isolated by an insulating region 113.

[0110] S29: As Figure 7nAs shown, a second organic material layer 122 is formed on the first metal region 111. Thus, the metal layer 11, the first organic material layer 121, and the second organic material layer 122 constitute the cap 10.

[0111] Specifically, an organic material is coated on the metal layer 11 to form a second organic material layer 122, and the second organic material layer 122 is etched to form a second through hole K2 that penetrates the second organic material layer 122. The second through hole K2 exposes the second metal region 112 and the insulating region 113.

[0112] S30: As Figure 1 As shown, metal balls 50 are formed on the second metal region 112, ultimately forming a wafer packaging structure.

[0113] Specifically, metal balls 50 are fabricated on the second metal zone 112 by printing solder balls or by chemical plating. The metal balls 50 are used for electrical connection with an external power source.

[0114] In the actual process, the wafer 20 will be thinned further, such as to 100μm-150μm. Finally, through the dicing process, a single wafer packaging structure is formed to complete the entire packaging process.

[0115] exist Figure 1 , Figure 3 as well as Figure 4 In the wafer packaging structure shown, the cap 10 is flat along the horizontal direction of the wafer 20. In this case, the height of the sealing ring 30 should be as equal as possible to the height of the metal bump 40. As mentioned above, preferably, the material of the sealing ring 30 is different from that of the metal bump 40. Specifically, the material of the sealing ring 30 includes organic materials, such as epoxy resin. In this way, the height of the sealing ring 30 is easier to control, so as to reduce the height difference between the sealing ring 30 and the metal bump 40, thereby improving the coplanarity of the wafer and the flatness of the wafer surface, enhancing the bonding strength between the device structure 21 on the wafer 20 and the metal bump 40, as well as the bonding strength between the wafer 20 and the sealing ring 30.

[0116] Considering that organic materials are generally coated by spin coating or spray coating, if the height of the sealing ring 30 is not too high, such as not exceeding 35μm, the height of the sealing ring 30 can be controlled so that the height of the sealing ring 30 is equal to the height of the metal bump 40. If the height of the sealing ring 30 is too high, the coating method will result in uneven height of the upper surface of the organic material, which will also lead to poor coplanarity of the wafer surface and affect the bonding of the wafer.

[0117] Based on this, optionally, before the first sacrificial layer 110, the second sacrificial layer 120, the metal layer 11, and the first organic material layer 121 are sequentially formed on the first substrate 100, the wafer packaging method further includes:

[0118] S11: As Figure 8a As shown, a groove T1 is formed on the first substrate 100.

[0119] With this setting, and thus... Figure 8b As shown, a first sacrificial layer 110, a second sacrificial layer 120, a metal layer 11 and a first organic material layer 121 are sequentially formed on the first substrate 100. The first organic material layer 121 in the groove is etched to form a first through hole K1 that penetrates the first organic material layer 121.

[0120] Then as Figure 8c As shown, a metal bump 40 is formed at the first through hole K1, and a sealing ring 30 is formed on the first organic material layer 121 outside the groove;

[0121] Then as Figure 8d As shown, the metal bump 40 and the device structure 21 are bonded together accordingly, and the sealing ring 30 is bonded together with the wafer 20 accordingly to form a sealing cavity Q1;

[0122] Furthermore, such as Figure 8e As shown, the first substrate 100, the first sacrificial layer 110, and the second sacrificial layer 120 are removed to expose the metal layer 11;

[0123] Then as Figure 8f As shown, the exposed metal layer 11 is etched to form a first metal region 111 and a plurality of second metal regions 112. The first metal region 111 and the second metal region 112 are spaced apart to form an insulating region 113.

[0124] Furthermore, such as Figure 8g As shown, a second organic material layer 122 is formed on the first metal region 111. Thus, the metal layer 11, the first organic material layer 121, and the second organic material layer 122 constitute the cap 10.

[0125] Finally, as Figure 5 As shown, a metal ball 50 is formed on the second metal region 112.

[0126] from Figure 5As can be seen, the subsequently formed cap 10 includes a flat portion 101 arranged along the horizontal direction of the wafer 20 and a protrusion 102 arranged away from the direction of the wafer 20. The device structure 21 and the metal bump 40 are located between the protrusion 102 and the wafer 20, and the sealing ring 30 is located between the flat portion 101 and the wafer 20. With this arrangement, the height difference between the protrusion 102 and the flat portion 101 replaces part of the height of the sealing ring 30, so that the height of the sealing ring 30 can be less than the height of the metal bump 40, or in other words, the height of the sealing ring 30 is reduced. Therefore, when organic materials are coated by spin coating or spray coating to form the sealing ring 30, the height of the sealing ring 30 is easier to control, and the surface of the sealing ring 30 is relatively flatter, improving the coplanarity of the wafer and the flatness of the wafer surface, enhancing the bonding strength between the device structure 21 and the metal bump 40 on the wafer 20, and the bonding strength between the wafer 20 and the sealing ring 30.

[0127] In the above embodiment, the height of the sealing ring 30 is less than the height of the metal bump 40, and the height range of the sealing ring 30 can be 5μm-15μm, including the endpoint value.

[0128] In general, the height of the sealing ring 30 is less than or equal to the height of the metal bump 40, and the height range of the sealing ring 30 can be 5μm-35μm, including the end values.

[0129] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0130] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer package structure, characterized by, The application relates to a wafer packaging structure comprising: a cap and a wafer oppositely arranged, wherein a device structure is arranged on the wafer and located between the cap and the wafer; the cap comprises a metal layer and an organic material layer, the metal layer comprises a first metal region and a plurality of second metal regions, and an insulating region is arranged between the first metal region and the second metal regions; a sealing ring is arranged between the cap and the wafer, and the metal layer and the organic material layer in the cap, the sealing ring and the wafer form a sealed cavity, and the device structure is located in the sealed cavity; a metal bump is arranged between the second metal region and the device structure, and the second metal region is electrically connected with the device structure through the metal bump; a metal ball is arranged on the surface of the second metal region away from the wafer, the metal ball is electrically connected with an external power supply, and the device structure obtains electric energy of the external power supply through the metal bump, the second metal region and the metal ball.

2. The wafer packaging structure according to claim 1, wherein: the organic material layer comprises a first organic material layer arranged on the side of the metal layer close to the wafer, or a second organic material layer arranged on the side of the metal layer away from the wafer, or a first organic material layer and a second organic material layer arranged on opposite sides of the metal layer along the thickness direction.

3. The wafer package structure of claim 1, wherein, the organic material layer comprises a first organic material layer arranged on the side of the metal layer close to the wafer; the first organic material layer extends from the surface of the first metal region to the surface of the second metal region through the insulating region, the surface of the second metal region exposed by the first organic material layer corresponds to a first through hole penetrating through the first organic material layer, and the metal bump is embedded in the first through hole.

4. The wafer package structure of claim 1, wherein, the organic material layer comprises a second organic material layer arranged on the side of the metal layer away from the wafer; the second organic material layer extends from the surface of the first metal region to the surface of the second metal region through the insulating region, the surface of the second metal region exposed by the second organic material layer corresponds to a second through hole penetrating through the second organic material layer, and the metal ball is embedded in the second through hole.

5. The wafer package structure of claim 1, wherein, the organic material layer comprises a first organic material layer and a second organic material layer arranged on opposite sides of the metal layer along the thickness direction; the first organic material layer extends from the surface of the first metal region to the surface of the second metal region through the insulating region, the surface of the second metal region exposed by the first organic material layer corresponds to a first through hole penetrating through the first organic material layer, and the metal bump is embedded in the first through hole; the second organic material layer extends on the surface of the first metal region.

6. The wafer package structure of claim 3 or 5, wherein, the metal bump comprises a first part embedded in the first through hole and a second part protruding out of the first through hole, and the projection of the first part on the plane where the wafer is located is located in the projection of the second part on the plane where the wafer is located.

7. The wafer package structure of claim 1, wherein, the organic material layer comprises a first organic material layer and a second organic material layer arranged on opposite sides of the metal layer along the thickness direction; The material of the first organic material layer is the same as or different from the material of the second organic material layer, and the material of the first organic material layer comprises polyimide.

8. The wafer package structure of claim 1, wherein, The material of the metal layer comprises copper, nickel, gold or nickel-gold alloy.

9. The wafer-level package structure of claim 1, wherein, The metal bump comprises a plurality of metal layers arranged in the direction of the device structure from the second metal area, and the plurality of metal layers comprise a seed layer, a first metal layer, a second metal layer and a third metal layer.

10. The wafer package structure of claim 1, wherein, The height of each metal bump is equal.

11. The wafer package structure of claim 1, wherein, The material of the sealing ring is different from the material of the metal bump, and the material of the sealing ring comprises organic material.

12. The wafer package structure of claim 1, wherein, The height of the sealing ring is less than or equal to the height of the metal bump, and the height of the sealing ring ranges from 5 μm to 35 μm, inclusive.

13. The wafer-level package structure of claim 1, wherein, The cap comprises a flat portion arranged in the horizontal direction of the wafer and a convex portion arranged away from the wafer, and the device structure and the metal bump are located between the convex portion and the wafer, and the sealing ring is located between the flat portion and the wafer.

14. The wafer package structure of claim 13, wherein, The height of the sealing ring is less than the height of the metal bump, and the height of the sealing ring ranges from 5 μm to 15 μm, inclusive.

15. A wafer packaging method, characterized by, Comprise: A wafer is provided, and a device structure is arranged on the wafer. The wafer and the device structure are packaged at the wafer level to form a wafer packaging structure, and the wafer packaging structure comprises the wafer and the device structure, and a cap arranged opposite to the wafer, and the device structure is located between the cap and the wafer. The cap comprises a metal layer and an organic material layer, the metal layer comprises a first metal area and a plurality of second metal areas, and the first metal area and the second metal area have an insulating area therebetween. A sealing ring is arranged between the cap and the wafer, and the metal layer and the organic material layer in the cap, the sealing ring and the wafer form a sealed cavity, and the device structure is located in the sealed cavity. A metal bump is arranged between the second metal area and the device structure, and the second metal area is electrically connected to the device structure through the metal bump. A metal ball is arranged on the surface of the second metal area away from the wafer, the metal ball is electrically connected to an external power supply, and the device structure obtains electric energy from the external power supply through the metal bump, the second metal area and the metal ball.

16. The wafer packaging method of claim 15, wherein, The organic material layer comprises a first organic material layer and a second organic material layer located on opposite sides of the metal layer in the thickness direction. The wafer and the device structure are packaged at the wafer level, which comprises: A first substrate is provided. A first sacrificial layer and a second sacrificial layer are sequentially formed on the first substrate, and a metal layer is formed on the second sacrificial layer. A first organic material layer is formed on the metal layer, and a first through hole penetrating through the first organic material layer is formed by etching the first organic material layer. A metal bump is formed at the first through hole. A sealing ring is formed on the first organic material layer around the metal bump. The metal bump and the device structure are correspondingly bonded and connected, and the sealing ring and the wafer are correspondingly bonded and connected to form the sealed cavity. removing the first substrate, the first sacrificial layer and the second sacrificial layer to expose the metal layer; etching the exposed metal layer to form a first metal region and a plurality of second metal regions, the first metal region and the second metal regions being arranged in intervals to form an insulating region; forming a second organic material layer on the first metal region, whereby the metal layer, the first organic material layer and the second organic material layer form a cap; forming a metal ball on the second metal region.

17. The wafer packaging method of claim 16, wherein, When the metal bump and the device structure are bonded, the sealing ring and the wafer are bonded at the same time, wherein the temperature range for synchronously bonding the metal bump and the device structure and the sealing ring and the wafer is 200-280°C, inclusive.

18. The wafer packaging method of claim 16, wherein, Before sequentially forming the first sacrificial layer, the second sacrificial layer, the metal layer and the first organic material layer on the first substrate, the wafer packaging method further comprises: forming a groove on the first substrate, so that the cap formed later comprises a flat portion arranged in the horizontal direction of the wafer and a protruding portion arranged away from the wafer, the device structure and the metal bump are located between the protruding portion and the wafer, and the sealing ring is located between the flat portion and the wafer.

19. The wafer packaging method of claim 15, wherein, The material of the sealing ring is an organic material, and the forming method of the sealing ring comprises a coating method.

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