Core board

Abstract

The invention provides a core board, one side of the core board is provided with a first layer of welding spot pins composed of a plurality of welding spot pins, the first layer of welding spot pins are distributed in a square shape, and the first layer of welding spot pins comprise a first side, a second side, a third side and a fourth side in the anticlockwise direction; along the anticlockwise direction, the first side sequentially comprises a first basic system function area and a first low-speed audio and video input and output function area; the second side comprises a first low-speed inter-board communication function area; the third side sequentially comprises a second low-speed inter-board communication function area, a low-speed debugging and downloading function area, a third low-speed inter-board communication function area and a second low-speed audio and video input and output function area; and the fourth side sequentially comprises a fourth low-speed inter-board communication functional area, a second basic system functional area and a fifth low-speed inter-board communication functional area. By adopting the scheme, the operation stability, the operation convenience and the scene adaptability of the core board can be improved.

Description

Technical Field

[0001] This invention relates to the field of embedded technology, and more specifically, to a core board. Background Technology

[0002] As the core computing and control unit of electronic devices, the core board needs to integrate diverse functions such as power management, data communication, program debugging, and audio / video processing to adapt to different application scenarios. The reasonable division and priority configuration of functional areas are key to ensuring the stable operation of basic functions and supporting the collaborative work of multiple modules, and directly determine the reliability and scenario adaptability of the core board.

[0003] While core boards in the current industry have integrated various basic functions, they lack systematic planning in the design of functional areas. The priority order of functional areas is not clear, flexible methods are not adopted for multiple sets of interfaces, and targeted isolation measures are not taken for signals in different functional areas. The overall approach is mainly based on simple function stacking, without fully considering the role of functional partitioning in improving performance and flexibility.

[0004] The current core board lacks a clear functional area priority division, which makes it impossible to prioritize the stability of basic functions and is prone to startup or power supply abnormalities; the signals of different functional areas are not effectively isolated, which can easily cause crosstalk and damage signal integrity; the interface lead-out method is fixed and cannot be flexibly selected according to actual scenarios; the vague division of functional areas not only reduces the efficiency of debugging and maintenance, but also limits the customized expansion capabilities of the core board and makes it difficult to match the application needs of multiple scenarios. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a core board that can improve the operational stability, ease of operation and adaptability to different scenarios.

[0006] This application provides a core board, on one side of which is provided a first layer of solder pins composed of multiple solder pins. The first layer of solder pins is distributed in a square shape in a counterclockwise direction. The first layer of solder pins includes a first side, a second side, a third side, and a fourth side. In a counter-clockwise direction: The first side includes, in sequence: the first basic system function area and the first low-speed audio and video input / output function area; The second side includes: the first low-speed inter-board communication functional area; The third side includes, in order: the second low-speed inter-board communication function area, the low-speed debugging and download function area, the third low-speed inter-board communication function area, and the second low-speed audio and video input / output function area; The fourth side includes, in order: the fourth low-speed board-to-board communication functional area, the second basic system functional area, and the fifth low-speed board-to-board communication functional area.

[0007] Optionally, in a counterclockwise direction, the first layer of solder joint pins includes a series of pins 1 to 149, wherein the first layer of solder joint pins has a first opening at the apex formed by the first side and the fourth side, and pins 37, 75 and 113 are located at the apex of the square. Pins 2 to 4 constitute the first basic system functional area; pins 6 to 9, pins 11 to 18, pins 20 to 27, and pins 29 to 36 constitute the first low-speed audio and video input / output functional area. Pins 38 to 43, pins 45 to 50, pins 52 to 55, pins 57 to 62, pins 64 to 69, and pins 71 to 74 constitute the first low-speed inter-board communication functional area. Pins 76 and 77 constitute the second low-speed inter-board communication functional area; pins 79 to 84 constitute the first low-speed debugging and downloading functional area; pins 86 to 88, pins 90 to 94, pins 96 to 101, and pins 103 to 106 constitute the third low-speed inter-board communication functional area; pins 108 to 112 constitute the second low-speed audio and video input / output functional area. Pins 114 and 115, pins 117 and 118, pins 119 and 120, pins 122 to 125, pins 127 to 130, and pins 132 to 135 constitute the fourth low-speed inter-board communication functional area; pins 137 to 145 constitute the second basic system functional area; and pins 147 and 148 constitute the fifth low-speed inter-board communication functional area.

[0008] Optionally, the core board further includes: The multi-layer solder joint pins, which are located on the same side of the core board as the first layer solder joint pins, include, in sequence, the following layers along the direction from the first layer solder joint pins to the center of the core board: second layer solder joint pins, third layer solder joint pins, fourth layer solder joint pins, and fifth layer solder joint pins. The second to fifth layer solder joint pins are all arranged in a square. The second and third layer solder joint pins have a second opening. The first and second openings are located at the same apex. The fourth and fifth layer solder joint pins are closed squares. Following a counter-clockwise order from the first to the fourth side, the second layer of solder joint pins includes: pins 150 to 278 arranged continuously; the third layer of solder joint pins includes: pins 279 to 399 arranged continuously; the fourth layer of solder joint pins includes: pins 400 to 515 arranged continuously; and the fifth layer of solder joint pins includes: pins 516 to 619 arranged continuously. Among these, pins 179, 214, 249, 307, 339, 371, 400, 429, 458, 487, 516, 542, 568, and 594 are located at the top corner of the square. From the first layer of solder joints to the fifth layer of solder joints, the spacing between any two adjacent pins is equal in the counterclockwise direction. From the first layer of solder joints to the fifth layer of solder joints, adjacent layers of solder joints are arranged at equal intervals, while adjacent layers of solder joints are arranged in a staggered manner.

[0009] Optionally, pins 236, 237, 477, and 478 constitute the JTAG interface area; Pins 451, 452, 204, and 205 constitute the mirror download area; The JTAG interface area, the image download area, and the low-speed debug serial port constitute the debug download function area.

[0010] Optional pins: 320, 321, 373, 245, 246, 250, 251, 372, 587, 588, 361, 362, 242, 243, 367, 368, 204, 205, 451, 452, 448, 449, 327, 326, 329, 330, 202, 201, 332, 333, 198, 199, 335, 336, ... 454, pin 455, pin 207, pin 208, pin 210, pin 211, pin 343, pin 344, pin 218, pin 219, pin 569, pin 570, pin 572, pin 573, pin 462, pin 463, pin 221, pin 222, pin 459, pin 460, pin 340, pin 341, pin 378, pin 379, pin 376, pin 375, pin 491, pin 492, pin 257, pin 256, pin 253, pin 254, pin 489, pin 488, pin 494, pin 4 95, Pin 259, Pin 382, ​​Pin 381, Pin 384, Pin 385, Pin 501, Pin 500, Pin 497, Pin 498, Pin 263, Pin 262, Pin 260, Pin 506, Pin 507, Pin 266, Pin 265, Pin 268, Pin 269, Pin 391, Pin 390, Pin 387, Pin 388, Pin 504, Pin 503, Pin 271, Pin 272, Pin 393, Pin 510, Pin 509, Pin 512, Pin 513, Pin 278, Pin 277, Pin 274, Pin 27 5. Pins 397, 396, 394, 324, 323, 443, 442, 196, 195, 445, 446, 215, 216, 358, 359, 346, 347, 157, 158, 178, 180, 181, 213, 248, 338, 370, 399, 457, 486, 515, 567, 593, and 619 constitute the high-speed inter-board communication functional area; The inter-board communication functional area is composed of the first low-speed inter-board communication functional area, the second low-speed inter-board communication functional area, the third low-speed inter-board communication functional area, the fourth low-speed inter-board communication functional area, the fifth low-speed inter-board communication functional area, and the high-speed inter-board communication functional area.

[0011] Optional pins: 532, 533, 166, 167, 297, 298, 163, 164, 535, 536, 419, 420, 295, 294, 169, 170, 425, 426, 303, 304, 422, 541, 423, 172, 173, 300, 301, 186, 187, 189, 190, 314, 315, 317. Pins 318, 436, 437, 308, 309, 311, 312, 430, 431, 433, 434, 183, 184, 292, 291, 413, 414, 526, 527, 160, 161, 288, 289, 529, 530, 407, 408, 285, 286, 154, 155, 410, 411, 523, and... Pins 524, 279, 280, 520, 521, 404, 405, 282, 283, 151, 152, 428, 575, 576, 227, 349, 350, 468, 469, 224, 225, 465, 466, 230, 231, 581, 582, 355, 356, 228, 578, 579, 352, 353, and 471 Pins 472, 474, 475, 233, 234, 584, 585, 481, 517, 518, 480, 239, 240, 364, 365, 483, 484, 590, 591, 401, 402, 439, 440, 192, 193, 416, 175, 176, 306, 417, 539, and 538 constitute the high-speed audio / video input / output functional area; The first low-speed audio / video input / output function area, the second low-speed audio / video input / output function area, and the high-speed audio / video input / output function area constitute the audio / video input / output function area.

[0012] Optionally, among the fifth layer solder joint pins, pins 543, 544, 546, 547, 549, 550, 552, 553, 555, 556, 558, 559, 561, 562, 564, 565, 595, 596, 598, 599, 601, 602, 604, 605, 607, 608, 610, 611, 613, 614, 616, and 617 are extension pins.

[0013] Optionally, the remaining pins from pin 1 to pin 619 are crosstalk-proof digital ground pins.

[0014] Optionally, each pin in the first to fifth layer solder joint pins is circular, with a diameter of 0.5mm-1.2mm. The center-to-center distance between adjacent pins on the same layer is 0.8mm-1.5mm. In the orthographic projection of adjacent pins in staggered arrangement on the corresponding side, the center-to-center distance between two adjacent pins is 0.4mm-0.75mm. In the direction perpendicular to the side, the center-to-center distance between adjacent pins in staggered arrangement on the same side is 1.5mm-2.5mm. The distance from the center of the pin on the first layer solder joint pin to the edge of the core board is 0.8mm-1.5mm.

[0015] Optionally, the core board further includes: a device area located within the area formed by the fifth layer solder pins, wherein active devices and / or passive devices are disposed within the device area, the distance from the center of the pin on the fifth layer solder pin to the edge of the device area is 1.5mm-2.5mm, and the size of the device area is less than or equal to 30mm×30mm.

[0016] Optionally, the first layer of solder joint pins is used to transmit low-speed signals below 2.5GHz, and the second, third, fourth and fifth layer of solder joint pins are used to transmit high-speed signals below 10GHz.

[0017] The technical solution provided in this application includes, but is not limited to, the following beneficial effects: The core board features a first layer of solder joints on one side, arranged in a square pattern and divided into four sides (first, second, third, and fourth) in a counter-clockwise direction. This design provides a regular physical framework for the orderly layout of functional areas. The square distribution conforms to the standardization and symmetry requirements of PCB layout, facilitating precise mating between the core board and the carrier board and reducing the risk of misalignment due to irregular layout. Simultaneously, the clear counter-clockwise division of the four sides creates distinct area boundaries, preventing spatial overlap of functional areas and laying the foundation for the orderly arrangement of subsequent functional areas. It also makes pin location easier during development and maintenance, reducing interface misidentification or operational errors caused by chaotic layout.

[0018] The first basic system functional area and the first low-speed audio / video input / output functional area are arranged sequentially in a counter-clockwise direction along the first edge. The core advantage lies in prioritizing the stability of basic functions and optimizing functional interrelationships. As the underlying support for the core board's operation, the priority layout of the first basic system functional area ensures better resource allocation and avoids the impact of signals or resource occupation from other functional areas, guaranteeing the reliable operation of basic functions such as power supply and reset. Placing the first low-speed audio / video input / output functional area adjacent to the basic system functional area shortens the signal transmission path between the two types of functional areas, reduces signal attenuation and interference during transmission, improves the stability of low-speed audio / video signals, and simplifies wiring design, reducing hardware design complexity.

[0019] The second side only houses the first low-speed inter-board communication functional area, achieving centralized management of low-speed inter-board communication functions. This layout unifies the pins related to low-speed inter-board communication into a single area. On the one hand, it facilitates centralized wiring and signal management for similar low-speed signals, reducing wiring clutter caused by pin dispersion. On the other hand, the independent functional area can physically isolate the low-speed communication signals from the basic system, audio / video, and other functional areas on other sides, avoiding crosstalk between low-speed communication signals and basic system power signals, audio / video signals, ensuring the stability of low-speed inter-board communication, and reducing the risk of packet loss or bit errors in communication scenarios such as industrial control and sensor data acquisition.

[0020] The third side connects multiple functional areas in a counter-clockwise direction, achieving functional complementarity and synergy. The second and third low-speed board communication functional areas extend the low-speed communication functionality of the second side, further increasing the number of low-speed communication interfaces to meet the needs of simultaneous access by multiple devices and maximizing the use of space resources on the first-layer solder joint pins. The low-speed debugging and download functional area is embedded between the two types of communication functional areas, allowing debugging and communication interfaces to be located close together. Developers do not need to search for interfaces across areas during debugging, enabling rapid connection of debugging equipment to the core board, improving debugging efficiency, and reducing the risk of misconnection due to interface dispersion. The final second low-speed audio / video input / output functional area complements the similar functional areas on the first side, expanding low-speed audio / video processing capabilities, forming a more complete low-speed audio / video functional chain, and improving the core board's adaptability to simple multimedia scenarios.

[0021] The fourth functional area layout focuses on expanding communication functions and improving the reliability of the basic system. The fourth and fifth low-speed board inter-board communication functional areas further improve the coverage of low-speed board inter-board communication interfaces, ensuring that the core board can adapt to more external low-speed devices and meet the communication needs of complex industrial scenarios or multi-sensor access scenarios. Placing the second basic system functional area between the two types of communication functional areas forms a redundant backup for the first basic system functional area. When the first basic system functional area fails, the second basic system functional area can ensure the basic operation of the core board, avoid the entire board from paralyzing, and significantly improve the operational reliability of the core board, which is especially suitable for industrial control or embedded scenarios with high requirements for device availability.

[0022] This application achieves a comprehensive advantage of "organized layout, orderly functions, controllable interference, and high reliability" by using a square distribution of the first-layer solder pins and a counter-clockwise side-by-side design, combined with a targeted functional area layout on all four sides. Each side's functional area not only achieves centralized management of similar functions and physical isolation of dissimilar functions, reducing signal crosstalk, but also ensures stable basic operation of the core board, efficient debugging operations, and comprehensive functional coverage through the priority and redundancy layout of the basic system functional area, the convenient arrangement of the debugging functional area, and the expansion and complementarity of the communication and audio / video functional areas. This overall improves the core board's operational stability, ease of operation, and scenario adaptability.

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This shows a schematic diagram of the structure of a core board provided in Embodiment 1 of the present invention; Figure 2 A schematic diagram of the structure of the second type of core board provided in Embodiment 1 of the present invention is shown; Figure 3 A schematic diagram of the structure of the third type of core board provided in Embodiment 1 of the present invention is shown; Figure 4 A simulation diagram of a solder joint pin signal transmission method provided in Embodiment 1 of the present invention is shown; Figure 5 A simulation diagram of the second type of solder joint pin signal transmission provided in Embodiment 1 of the present invention is shown. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0027] It should be noted in advance that all pins involved in this application are standard pins. For specific functions, definitions and explanations, please refer to the functions, definitions and explanations of standard pins in the prior art. They will not be described in detail here.

[0028] Example To facilitate understanding of this application, the following is combined with... Figure 1 The schematic diagram of a core board provided in the embodiment of the present invention shown herein will be used to describe the embodiments of this application in detail.

[0029] See Figure 1 As shown, Figure 1The diagram shows a structural schematic of a core board provided by an embodiment of the present invention. The core board has a first layer of solder pins consisting of multiple solder pins on one side. The first layer of solder pins is arranged in a square pattern along a counterclockwise direction and includes a first side, a second side, a third side, and a fourth side.

[0030] Specifically, the first layer of solder pins is set on one side of the core board to realize the electrical connection between the core board and the external carrier board or device; the square distribution design meets the regularity requirements of PCB layout and facilitates the subsequent division of functional areas and pin management; dividing the four sides in a counterclockwise direction can form clear area boundaries, providing a basic framework for the orderly arrangement of different functional areas.

[0031] Along the counterclockwise direction: the first side includes, in sequence: the first basic system function area and the first low-speed audio and video input / output function area.

[0032] Specifically, the first basic system function area is arranged first because basic system functions (such as power supply and reset) are prerequisites for the operation of the core board and their stability must be guaranteed first. The first low-speed audio and video input and output function area is arranged subsequently based on functional correlation, so that the basic functions and basic audio and video functions are arranged close to each other to reduce signal transmission paths and reduce interference.

[0033] The second side includes: the first low-speed inter-board communication functional area.

[0034] Specifically, the second side has a separate first low-speed inter-board communication functional area to centrally arrange the low-speed part of inter-board communication (such as RGMII), which facilitates wiring and signal management. At the same time, it is distinct from the functional area on the first side to avoid mutual interference between signals of different types of functions and ensure the stability of low-speed communication.

[0035] The third side includes, in order: the second low-speed inter-board communication function area, the low-speed debugging and download function area, the third low-speed inter-board communication function area, and the second low-speed audio and video input / output function area.

[0036] Specifically, the third side connects multiple functional areas to supplement the low-speed inter-board communication function of the second side. At the same time, a low-speed debugging and download function area is added, which allows the debugging interface and the communication interface to be laid out close together, making it convenient for developers to quickly connect during debugging. Finally, the second low-speed audio and video input and output function area is arranged to further expand the audio and video functions and form a complete low-speed audio and video processing link.

[0037] The fourth side includes, in order: the fourth low-speed board-to-board communication functional area, the second basic system functional area, and the fifth low-speed board-to-board communication functional area.

[0038] Specifically, the fourth and fifth low-speed board communication functional areas are set on the fourth side to maximize the use of the space of the first layer solder pins and fully cover the low-speed board communication needs; the second basic system functional area is arranged in the middle to redundancy supplement the first basic system functional area, ensuring that the core board can still maintain basic operation under extreme conditions and improve reliability.

[0039] In an optional implementation, see Figure 2 As shown, Figure 2 A schematic diagram of the structure of the second type of core board provided in the embodiment of the present invention is shown. In the counterclockwise direction, the first layer of solder joint pins includes pins 1 to 149 arranged in a continuous manner. The first layer of solder joint pins has a first opening at the apex corner formed by the first side and the fourth side. Pins 37, 75 and 113 are located at the apex corner of the square.

[0040] Specifically, pins 1 to 149 are arranged in a continuous sequence, allowing designers to quickly locate pin positions by pin number, reducing the difficulty of identification; the design of the first opening is mainly used for the docking and positioning of the core board and the carrier board to avoid misalignment during installation; pins 37, 75, and 113 at the top corner can serve as physical positioning references and also as electrical reference points to ensure the consistency of pin signals on each side.

[0041] Pins 2 to 4 constitute the first basic system functional area; pins 6 to 9, pins 11 to 18, pins 20 to 27, and pins 29 to 36 constitute the first low-speed audio and video input / output functional area.

[0042] Specifically, pins 2 to 4 form the first basic system functional area. Combined with UP5 core board technology, these pins are power supply pins (such as the power supply pins of area A), responsible for providing power to the entire core board and serving as the energy foundation for the core board's operation. Pins 6 to 36 form the first low-speed audio and video input / output functional area. The corresponding LCD interface pins (such as LCD clock, data enable, horizontal and vertical sync, and RGB data pins) can realize basic video display functions to meet the needs of low-speed video applications.

[0043] Pins 38 to 43, pins 45 to 50, pins 52 to 55, pins 57 to 62, pins 64 to 69, and pins 71 to 74 constitute the first low-speed inter-board communication functional area.

[0044] Specifically, the RGMII interface pins in groups A and B of the inter-board communication functional area corresponding to these pins (such as RGMII receive clock, receive data, transmit clock, transmit data, etc.) belong to the category of low-speed Ethernet communication, which can realize low-speed Ethernet data interaction between the core board and external devices. It is suitable for data transmission scenarios in industrial control where the transmission rate requirement is not high.

[0045] Pins 76 and 77 constitute the second low-speed inter-board communication functional area; pins 79 to 84 constitute the first low-speed debugging and download functional area; pins 86 to 88, pins 90 to 94, pins 96 to 101, and pins 103 to 106 constitute the third low-speed inter-board communication functional area; pins 108 to 112 constitute the second low-speed audio and video input / output functional area.

[0046] Specifically, pins 76 and 77 are Group C I2C bus pins (I2C reference clock and data signals), which are low-speed communication interfaces, thus forming the second low-speed inter-board communication functional area; pins 79 to 84 are debug serial port pins (input and output signals) for the A core, M core, and DSP, which can monitor the operating status of different cores respectively, corresponding to the first low-speed debug download functional area; pins 86 to 106 include TF / SD card interface (detection, data, clock, command pins), SDIO interface (data, clock, command pins) and Group A five-wire UART interface (send request, send, receive, clear send pins), which are all low-speed communication or storage interfaces, forming the third low-speed inter-board communication functional area; pins 108 to 112 are I2S interface pins (master clock, data output, data input, bit clock, frame clock), responsible for audio signal transmission, forming the second low-speed audio and video input / output functional area.

[0047] Pins 114 and 115, pins 117 and 118, pins 119 and 120, pins 122 to 125, pins 127 to 130, and pins 132 to 135 constitute the fourth low-speed inter-board communication functional area; pins 137 to 145 constitute the second basic system functional area; and pins 147 and 148 constitute the fifth low-speed inter-board communication functional area.

[0048] Specifically, pins 114 and 115 are group D I2C bus pins, pins 117 to 120 are group C and group D three-wire UART interface pins, pins 122 to 125 are group A and group B CAN bus pins, pins 127 to 130 are group A SPI bus pins, and pins 132 to 135 are general-purpose ADC and LRADC signal pins. These are all low-speed communication or analog signal interfaces, which together constitute the fourth low-speed inter-board communication functional area. Pins 137 to 145 include BOOT startup item control, USB programming control, board reset, sleep wake-up, power on / off and other signal pins, which constitute the second basic system functional area. Pins 147 and 148 are group A I2C bus pins, which belong to low-speed communication interfaces and constitute the fifth low-speed inter-board communication functional area.

[0049] In one optional implementation, see Figure 3 As shown, Figure 3A schematic diagram of the structure of a third type of core board provided in an embodiment of the present invention is shown. The core board further includes: a multi-layer solder pin that is disposed on the same side of the core board as the first layer solder pin. The multi-layer solder pin includes, in sequence, a second layer solder pin, a third layer solder pin, a fourth layer solder pin, and a fifth layer solder pin along the direction from the first layer solder pin to the center of the core board. The second layer solder pin to the fifth layer solder pin are all squarely distributed. The second layer solder pin and the third layer solder pin both have a second opening. The first opening and the second opening are located at the same apex. The fourth layer solder pin and the fifth layer solder pin are closed squares.

[0050] Specifically, the multi-layer solder joint pins are designed to increase the number of pins within a limited core board area, accommodating more functional interfaces and meeting the core board's requirements for multi-functionality and high integration. Each layer is squarely distributed to maintain layout consistency and facilitate the alignment and routing of multi-layer pins. The second opening is in the same position as the first opening, ensuring that the multi-layer pins are uniformly positioned when mating with the carrier board, avoiding connection failures caused by misaligned openings. The fourth and fifth layers are closed squares because the central area of ​​the core board has more compact space, and the closed design can make full use of the space and increase pin density.

[0051] Following a counter-clockwise order from the first to the fourth side, the second layer of solder joint pins includes pins 150 to 278 arranged consecutively; the third layer of solder joint pins includes pins 279 to 399 arranged consecutively; the fourth layer of solder joint pins includes pins 400 to 515 arranged consecutively; and the fifth layer of solder joint pins includes pins 516 to 619 arranged consecutively. Among these, pins 179, 214, 249, 307, 339, 371, 400, 429, 458, 487, 516, 542, 568, and 594 are located at the top corners of the square.

[0052] Specifically, the pins of each layer are arranged in segments with consecutive serial numbers, which can clearly distinguish the pin range of different layers and facilitate design and maintenance. The pins at the top corners serve as the marker pins of each layer, which can not only help with positioning, but also serve as reference nodes for signals of each layer, ensuring the consistency of electrical performance of pins in multiple layers. At the same time, these pins can also be used to detect the connection status of each layer, improving the testability of the core board.

[0053] From the first layer of solder joints to the fifth layer of solder joints, the spacing between any two adjacent pins is equal in the counterclockwise direction.

[0054] Specifically, equal spacing between adjacent pins meets the standardized requirements of PCB design, facilitates production using automated soldering equipment, and reduces soldering deviations caused by inconsistent spacing. At the same time, uniform spacing allows for more consistent signal path lengths, avoids uneven signal delays caused by path differences, and ensures the synchronization of signal transmission, which is especially crucial for the stability of high-speed signal transmission.

[0055] From the first layer of solder joints to the fifth layer of solder joints, adjacent layers of solder joints are arranged at equal intervals, while adjacent layers of solder joints are arranged in a staggered manner.

[0056] Specifically, equidistant arrangement of adjacent layers ensures uniform structure of the core board in the thickness direction, avoiding wiring congestion caused by excessively small interlayer spacing or wasted space due to excessively large interlayer spacing; staggered arrangement can further increase pin density without increasing the core board area, while reducing signal coupling between pins of adjacent layers and reducing crosstalk risk.

[0057] In an alternative implementation, pins 236, 237, 477, and 478 constitute the JTAG interface area.

[0058] Specifically, pins 236 (JTAG_TDO), 237 (JTAG_TDI), 477 (JTAG_TMS), and 478 (JTAG_TCK) are key pins of the JTAG debug interface, used for high-speed debugging of M-core programs. They can realize functions such as breakpoint debugging and register viewing, and the transmission rate is much higher than that of low-speed debug serial ports.

[0059] Pins 451, 452, 204, and 205 constitute the mirror download area.

[0060] Specifically, pins 451 (USB data positive), 452 (USB data negative), 204 (USB VBUS), and 205 (USB ID) are pins of the high-speed USB download interface, which can realize the fast download of system images, greatly improving development efficiency compared with the low-speed download method. These pins together constitute the high-speed debug download function area.

[0061] The JTAG interface area, the image download area, and the low-speed debug serial port constitute the debug download function area.

[0062] Specifically, this functional division covers all the needs of core board debugging and downloading: the low-speed debugging and downloading function area (such as the core debugging serial ports) is suitable for basic operation status monitoring and simple program debugging, with low cost and strong compatibility; the JTAG interface area and image download area are suitable for complex program debugging and fast image downloading, meeting the needs of efficient development. The combination of the two makes the debugging and downloading function area both have basic usability and high efficiency.

[0063] In an optional implementation, pins 320, 321, 373, 245, 246, 250, 251, 372, 587, 588, 361, 362, 242, 243, 367, 368, 204, 205, 451, 452, 448, 449, 327, 326, 329, 330, 202, 201, 332, 333, 198, 199, 335, and... 336, Pin 454, Pin 455, Pin 207, Pin 208, Pin 210, Pin 211, Pin 343, Pin 344, Pin 218, Pin 219, Pin 569, Pin 570, Pin 572, Pin 573, Pin 462, Pin 463, Pin 221, Pin 222, Pin 459, Pin 460, Pin 340, Pin 341, Pin 378, Pin 379, Pin 376, Pin 375, Pin 491, Pin 492, Pin 257, Pin 256, Pin 253, Pin 254, Pin 489, Pin 488, Pin 494 Pins 495, 259, 382, ​​381, 384, 385, 501, 500, 497, 498, 263, 262, 260, 506, 507, 266, 265, 268, 269, 391, 390, 387, 388, 504, 503, 271, 272, 393, 510, 509, 512, 513, 278, 277, 274, and so on. Pins 275, 397, 396, 394, 324, 323, 443, 442, 196, 195, 445, 446, 215, 216, 358, 359, 346, 347, 157, 158, 178, 180, 181, 213, 248, 338, 370, 399, 457, 486, 515, 567, 593, and 619 constitute the high-speed inter-board communication functional area.

[0064] Specifically, the aforementioned pins are grouped to correspond to the core interfaces of high-speed inter-board communication, covering types such as USB, TYPE-C, PCIE, and SERDES, to collaboratively achieve high-bandwidth data transmission, as detailed below: These include pins 335-336 (Group B USB 2.0 data positive / negative), 454-455 (USB 3.0 transmit data positive / negative), and pins 204-205 and 451-452 (other groups of USB 2.0 / 3.0 data or power pins). These pins constitute the differential data link and power supply loop of the USB bus. The USB 2.0 pins support a medium-speed transmission of 480Mbps, while the USB 3.0 pins achieve a high-speed transmission of 5Gbps through independent transmit / receive channels, adapting to data interaction with storage devices such as USB flash drives and high-speed hard drives, as well as peripherals.

[0065] It includes pins 332-333 (TYPE-C power enable / interrupt signals), 198-199, 201-202, 329-330, 326-327, and 448-449 (TYPE-C differential data, configuration, or detection pins). The power enable pin controls the interface power supply switch, and the interrupt pin provides feedback on the connection status. The differential data pins are compatible with USB 3.0 high-speed transmission, support reversible insertion and power adjustment, and are suitable for flexible connection scenarios such as laptops and smart terminals.

[0066] This involves pins 495, 259 (PCIe sleep / wake-up / reference clock request), 495 (PCIe global reset signal), 375-376, 491-492, 501-500, 253-254, 488-489, 384-385, 262-263, 497-498, 381-382, etc. (PCIe differential data channels and clock pins). The sleep / wake-up pins enable low-power management, while the reference clock pins ensure transmission synchronization. Multiple differential data channels form x2 / x4 links, with a single channel rate reaching 8Gbps (version 3.0), meeting the ultra-high bandwidth requirements of high-speed network cards, SSDs, and other peripherals.

[0067] It includes pins 323-324 (SERDES management data / clock), 442-443, and 195-196 (SERDES differential transmission channels). The management pins are responsible for configuration and status interaction, while the differential channels achieve speeds of over 10Gbps through serial transmission technology. This simplifies wiring while supporting stable communication between the core board and high-speed backplanes and long-distance peripherals, making it suitable for industrial-grade long-distance high-speed scenarios.

[0068] Overall, these pins, through categorized and coordinated storage, form the hardware foundation for high-speed inter-board communication functional areas, covering transmission rates from hundreds of Mbps to several Gbps, meeting the large data transmission needs of scenarios such as high-speed storage, high-definition video streaming, and industrial control.

[0069] The inter-board communication functional area is composed of the first low-speed inter-board communication functional area, the second low-speed inter-board communication functional area, the third low-speed inter-board communication functional area, the fourth low-speed inter-board communication functional area, the fifth low-speed inter-board communication functional area, and the high-speed inter-board communication functional area.

[0070] Specifically, this multi-area combination design gives the inter-board communication functional area a strong adaptability: the low-speed communication area covers traditional low-speed interfaces such as I2C, UART, CAN, and SPI, meeting the needs of industrial control, sensor data acquisition and other scenarios; the high-speed communication area covers high-speed interfaces such as USB3.0, PCIE, and TYPE-C, meeting the needs of high-end data transmission scenarios; the combination of the two enables the core board to communicate with external devices of different speeds and types, fully covering the inter-board communication needs.

[0071] In an alternative implementation, pins 532, 533, 166, 167, 297, 298, 163, 164, 535, 536, 419, 420, 295, 294, 169, 170, 425, 426, 303, 304, 422, 541, 423, 172, 173, 300, 301, 186, 187, 189, 190, 314, and 315 are used. Pins 317, 318, 436, 437, 308, 309, 311, 312, 430, 431, 433, 434, 183, 184, 292, 291, 413, 414, 526, 527, 160, 161, 288, 289, 529, 530, 407, 408, 285, 286, 154, 155, 410, 411, 52 3. Pins 524, 279, 280, 520, 521, 404, 405, 282, 283, 151, 152, 428, 575, 576, 227, 349, 350, 468, 469, 224, 225, 465, 466, 230, 231, 581, 582, 355, 356, 228, 578, 579, 352, 353, 4 Pins 71, 472, 474, 475, 233, 234, 584, 585, 481, 517, 518, 480, 239, 240, 364, 365, 483, 484, 590, 591, 401, 402, 439, 440, 192, 193, 416, 175, 176, 306, 417, 539, and 538 constitute the high-speed audio / video input / output functional area.

[0072] Specifically, the high-speed audio / video input / output functional area integrates key pins of various high-performance audio / video interfaces, achieving high-quality audio / video signal transmission and processing through targeted hardware design, as detailed below: In HDMI (High-Definition Multimedia Interface) transmit (TX) mode, the core control pins are 532-533: pin 532 is the HDMI management data signal (SDA), and pin 533 is the HDMI management clock signal (SCL). This pair of pins operates via the I2C bus protocol and serves as a "communication bridge" between the core board and HDMI devices (such as monitors and TVs). The core board can read parameters from external devices (such as the resolution and refresh rate supported by the monitor) through this bus and send configuration commands to the devices (such as outputting 4K@60Hz video or switching HDR mode).

[0073] HDMI TX is responsible for outputting the video signal processed by the core board to the display device, supporting high-definition features such as up to 8K resolution and high dynamic range (HDR); HDMI RX is used to receive high-definition video signals from external devices (such as receiving movie content from a set-top box). The combination of the two enables two-way interaction of high-definition audio and video, and is the core interface for scenarios such as home theaters and conference systems.

[0074] MIPI includes two sub-interfaces: Display Output (DSI) and Comparative Image Input (CSI). The MIPIDSI interface relies on a differential clock channel and multiple differential data channels working together. The core key pins include clock channel and data channel pins: The differential clock channel consists of pin 436 (MIPIDSI clock positive signal) and pin 437 (MIPIDSI clock negative signal), which is responsible for providing a high-speed synchronous clock, providing a timing reference for data transmission, and ensuring that the receiving end can accurately interpret the data; The differential data channel includes multiple channels such as pin 186 (MIPIDSI data 3 positive signal) and pin 187 (MIPIDSI data 3 negative signal), which are responsible for transmitting display data (pixel information, control commands). The MIPI DSI interface features an inseparable clock and data channel that must operate simultaneously. The synchronization signal provided by the clock channel compensates for transmission delay differences, preventing data misalignment. Multiple data channels work in tandem with the clock channel, allowing a single interface to meet the high-speed data requirements of 4K resolution displays. Designed specifically for small to medium-sized high-definition display devices (such as mobile phones, tablets, and automotive screens), it reduces electromagnetic interference through differential signal transmission, ensuring smooth, flicker-free visuals. Similarly, MIPICSI receives image signals from cameras via similar differential data pins, supporting high-speed real-time acquisition up to 48 megapixels. It is a core input interface for machine vision scenarios such as intelligent monitoring and facial recognition.

[0075] The LVDS (Low Voltage Differential Signaling) interface uses low voltage differential transmission technology to achieve high-speed signal transmission (single channel rate up to 1.6Gbps) at low voltage (usually below 3.3V). Its core advantage is strong anti-interference capability. External electromagnetic interference has basically the same effect on the positive and negative pins. By detecting the voltage difference between the two, interference can be effectively canceled, avoiding screen flickering and jitter.

[0076] When implementing display functionality using the LVDS interface, the differential clock channel pins and differential data channel pins must work together: the differential clock channel provides a synchronization timing reference, ensuring the receiver can accurately interpret the data timing; the differential data channel (taking data transmission as an example, it includes multiple sets of differential data pins, such as pin 407 for the LVDS data 3 negative signal and pin 408 for the LVDS data 3 positive signal) is responsible for transmitting display data. The clock channel and data channel are inseparable, and both jointly support the implementation of the display function.

[0077] LVDS interfaces are commonly used in medium to large industrial displays (15-27 inches) and vehicle central control screens, balancing high-speed transmission and stability, and are the mainstream display interface for industrial control terminals.

[0078] The control pins of the EDP (Embedded Display Port) interface are 292-291: Pin 292 is the EDP power enable signal, used to control the power switch of the EDP display (the core board can turn the screen on / off as needed to achieve energy saving); Pin 291 is the EDP plug-in / plug-out detection signal, which detects in real time whether the display is correctly connected. If the connection is abnormal, it can trigger the core board to stop signal output to avoid hardware damage.

[0079] The EDP interface supports up to 8K resolution, making it suitable for ultra-thin laptops, all-in-one PCs, and other devices with strict space requirements, balancing the needs of high-definition display and hardware miniaturization.

[0080] The audio interface includes two key pins: differential speaker output and differential microphone input. The differential speaker interface transmits audio signals through positive / negative differential pins. The differential design reduces interference during transmission (such as power supply noise and external electromagnetic radiation), avoids noise and background noise during playback, and supports lossless audio output. The differential microphone input interface also uses differential pins to collect voice signals, improving anti-interference capabilities and ensuring the clarity of voice collection in noisy environments.

[0081] These audio interfaces are compatible with scenarios requiring high-quality audio interaction, such as conference terminals and smart speakers, and work in conjunction with video interfaces to achieve a synchronized experience of "high-definition video + high-fidelity audio".

[0082] The high-speed audio and video input / output function area, through the coordinated operation of the above interfaces, realizes the output and acquisition of 4K and above resolution video, and the playback and acquisition of high-fidelity audio. It meets the needs of high-end audio and video applications such as multimedia display (such as high-definition TV, conference screen), video surveillance (such as smart camera), and high-end interactive terminals (such as all-in-one machine), and provides the core board with complete high-performance audio and video processing capabilities.

[0083] The first low-speed audio / video input / output function area, the second low-speed audio / video input / output function area, and the high-speed audio / video input / output function area constitute the audio / video input / output function area.

[0084] Specifically, this functional division achieves full-scenario coverage of audio and video processing: the low-speed audio and video area (such as LCD interface, basic I2S interface) is suitable for simple video display (such as small-sized LCD screen) and ordinary audio playback (such as mono speaker), which is low-cost and easy to implement; the high-speed audio and video area (such as HDMI, MIPI, LVDS) is suitable for high-definition, high-speed audio and video processing, meeting the needs of high-end applications; the combination of the two enables the core board to be compatible with various audio and video devices from low-end to high-end.

[0085] In an optional implementation, pins 543, 544, 546, 547, 549, 550, 552, 553, 555, 556, 558, 559, 561, 562, 564, 565, 595, 596, 598, 599, 601, 602, 604, 605, 607, 608, 610, 611, 613, 614, 616, and 617 of the fifth-layer solder joint pins are extension pins.

[0086] Specifically, the extended pin configuration is designed to enhance the customizability of the core board. When users have special functional requirements (such as adding custom sensor interfaces, additional IO control pins, or dedicated communication interfaces), these pins can be used for secondary development without modifying the basic circuitry and existing functional areas of the core board, thus greatly expanding the application scenarios of the core board.

[0087] In an alternative implementation, the remaining pins from pin 1 to pin 619 are crosstalk-proof digital ground pins.

[0088] Specifically, the core function of these anti-crosstalk digital ground pins is to provide a stable return path for signals in each functional area, while isolating signals from different functional areas (such as separating high-speed communication signals from low-speed control signals), effectively suppressing signal crosstalk. Especially for high-speed signals (such as PCIe and HDMI), the ground pins can absorb interference signals, ensure signal integrity, and ensure the stable and independent operation of each functional module of the core board.

[0089] The anti-crosstalk digital ground pins include: pin 1, pin 5, pin 10, pin 19, pin 28, pin 37, pin 44, pin 51, pin 56, pin 63, pin 70, pin 75, pin 78, pin 85, pin 89, pin 95, pin 102, pin 107, pin 113, pin 116, pin 121, pin 126, pin 131, pin 136, pin 146, pin 149, pin 150, pin 153, pin 156, pin 159, pin 162, pin 165, pin 168, pin 171, pin 174, pin 177, pin 179, etc. Pins 182, 185, 188, 191, 194, 197, 200, 203, 206, 209, 212, 214, 217, 220, 223, 226, 229, 232, 235, 238, 241, 244, 247, 249, 252, 255, 258, 261, 264, 267, 270, 273, 276, 281, 284, 287, ... Pins 290, 293, 296, 299, 302, 305, 307, 310, 313, 316, 319, 322, 325, 328, 331, 334, 337, 339, 342, 345, 348, 351, 354, 357, 360, 363, 366, 369, 371, 374, 377, 380, 383, 386, 389, 392, ... Pins 395, 398, 400, 403, 406, 409, 412, 415, 418, 421, 424, 427, 429, 432, 435, 438, 441, 444, 447, 450, 453, 456, 458, 461, 464, 467, 470, 473, 476, 479, 482, 485, 487, 490, 493, 496, and so on.499, pin 502, pin 505, pin 508, pin 511, pin 514, pin 516, pin 519, pin 522, pin 525, pin 528, pin 531, pin 534, pin 537, pin 540, pin 542, pin 545, pin 548, pin 551, pin 554, pin 557, pin 560, pin 563, pin 566, pin 568, pin 571, pin 574, pin 577, pin 580, pin 583, pin 586, pin 589, pin 592, pin 594, pin 597, pin 600, pin 603, pin 606, pin 609, pin 612, pin 615, pin 618.

[0090] In one optional implementation, each pin in the first to fifth layer solder joint pins is circular with a diameter of 0.5mm-1.2mm. The center-to-center distance between adjacent pins on the same layer is 0.8mm-1.5mm. In the orthographic projection of adjacent pins in staggered arrangement on the corresponding side, the center-to-center distance between two adjacent pins is 0.4mm-0.75mm. The center-to-center distance between adjacent pins in staggered arrangement on the same side is 1.5mm-2.5mm in the direction perpendicular to that side. The distance from the center of the pin on the first layer solder joint pin to the edge of the core board is 0.8mm-1.5mm.

[0091] Specifically, round leads facilitate soldering, and a diameter range of 0.5mm-1.2mm balances soldering reliability (too small a diameter is prone to cold solder joints, while too large a diameter occupies too much space) and lead density; the spacing between adjacent leads on the same layer is 0.8mm-1.5mm, and the staggered projection spacing is 0.4mm-0.75mm, which ensures lead density while avoiding the risk of short circuits between adjacent leads; the vertical spacing between layers is 1.5mm-2.5mm, and the spacing from the first layer to the edge is 0.8mm-1.5mm, which ensures sufficient space for PCB routing, while also ensuring the structural strength of the core board and preventing damage to edge leads due to excessive proximity.

[0092] In an optional implementation, the core board further includes a device area located within the region formed by the fifth layer solder pins, wherein active devices and / or passive devices are disposed within the device area, the distance from the center of the pin on the fifth layer solder pin to the edge of the device area is 1.5mm-2.5mm, and the size of the device area is less than or equal to 30mm×30mm.

[0093] Specifically, the device area is located in the center of the core board, which can shorten the connection path between passive devices such as capacitors and the power supply pins of the CPU, thus improving electrical performance while ensuring power integrity. Active devices (such as low-power power chips) and passive devices (such as resistors and capacitors) are arranged in a concentrated manner, which facilitates power supply management and heat dissipation design. The 1.5mm-2.5mm spacing avoids signal interference between devices and pins. The size control within 30mm×30mm makes the core board compact and suitable for miniaturized devices (such as embedded terminals and portable devices).

[0094] The above dimensions and spacing have been verified by simulation. This arrangement can ensure the integrity of frequency signals below 10GHz. Since both low-speed and high-speed signals are below 10GHz, only signals below 10GHz are considered.

[0095] See Figure 4 As shown, Figure 4 This diagram illustrates a simulation of signal transmission via solder joint pins according to Embodiment 1 of the present invention. The horizontal axis represents the signal frequency in GHz, ranging from 0 GHz to 20 GHz; the vertical axis represents the return loss of the signal on the transmission channel, i.e., the ratio of the signal reflected from the transmission channel to the incident signal. In this example, the transmission channel refers to the LGA solder joint connecting the core board and the baseboard. The smaller the value, the less loss occurs when the signal passes through the LGA solder joint, and the better the signal quality. The green line represents the SFF-8431 protocol's limit on the return loss of signals below 10 GHz on the transmission channel, requiring that the actual return loss of the transmission channel not exceed this value. The red curve represents the simulated return loss of signals below 10 GHz passing through the half-hole solder joint under a design with an LGA solder joint diameter of 0.8 mm and a solder joint spacing of 1.27 mm. As can be seen from the diagram, the simulated data has a minimum margin of 4.9 dB relative to the protocol limit across the entire frequency range, which meets the requirements.

[0096] See Figure 5 As shown, Figure 5The diagram illustrates a simulation of the second type of solder joint pin signal transmission provided in Embodiment 1 of the present invention. The horizontal axis represents the signal frequency in GHz, ranging from 0 GHz to 20 GHz; the vertical axis represents the return loss of the signal on the transmission channel, i.e., the ratio of the signal reflected from the transmission channel to the incident signal. In this example, the transmission channel refers to the LGA solder joint connecting the core board and the baseboard. The smaller the value, the less loss occurs when the signal passes through the LGA solder joint, and the better the signal quality. The green line represents the SFF-8431 protocol's limit on the return loss of signals below 10 GHz on the transmission channel, requiring that the actual return loss of the transmission channel cannot exceed this value. The red curve represents the simulated return loss of signals below 10 GHz passing through the half-hole solder joint under a design with an LGA solder joint diameter of 1 mm and a solder joint spacing of 1.5 mm. As can be seen from the diagram, the simulated data has a minimum margin of 3.8 dB relative to the protocol limit across the entire frequency range. Figure 4 The margin in the signal has decreased, resulting in poorer signal quality.

[0097] based on Figure 4 and Figure 5 The simulation data comparison shows that: a smaller solder joint diameter can reduce abrupt changes in the signal transmission path and reduce reflection; a smaller solder joint spacing can reduce parasitic capacitance and inductive coupling between adjacent pins and reduce crosstalk; the combined effect of both results in less energy loss and better signal integrity during transmission. This conclusion provides quantitative support for the optimization direction of core board solder joint design, ensuring that subsequent designs can prioritize the selection of better parameters.

[0098] In an alternative implementation, the first layer of solder joint pins is used to transmit low-speed signals below 2.5 GHz, and the second, third, fourth, and fifth layer of solder joint pins are used to transmit high-speed signals below 10 GHz.

[0099] Specifically, the first layer transmits low-speed signals below 2.5GHz (such as I2C, UART, and LCD signals) because these signals have lower requirements for transmission rate and isolation, and stability can be guaranteed without a multi-layer layout; the second to fifth layers transmit high-speed signals below 10GHz (such as USB 3.0, PCIe, and HDMI signals) because high-speed signals have high requirements for cabling length and isolation, and multi-layer layouts can reduce interference and ensure signal integrity through layered isolation, short-path cabling, and other methods.

[0100] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0101] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. All should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A core plate, characterized by The core board is provided with a first layer of soldering pin composed of a plurality of soldering pin pins on one side, the first layer of soldering pin pins are distributed in a square shape, and the first layer of soldering pin pins comprise a first side, a second side, a third side and a fourth side in a counterclockwise direction; in a counterclockwise direction: The first side comprises a first basic system function area, a first low-speed audio and video input and output function area in sequence; The second side comprises a first low-speed inter-board communication function area; The third side comprises a second low-speed inter-board communication function area, a low-speed debugging and downloading function area, a third low-speed inter-board communication function area, a second low-speed audio and video input and output function area in sequence; The fourth side comprises a fourth low-speed inter-board communication function area, a second basic system function area, a fifth low-speed inter-board communication function area in sequence.

2. The core plate of claim 1, wherein, In a counterclockwise direction, the first layer of soldering pin pins comprise pins (1) to (149) arranged in sequence, wherein the first layer of soldering pin pins have a first opening at a top corner formed by the first side and the fourth side, and pins (37), (75) and (113) are located at the top corner of the square; Pins (2) to (4) constitute the first basic system function area; pins (6) to (9), (11) to (18), (20) to (27), (29) to (36) constitute the first low-speed audio and video input and output function area; Pins (38) to (43), (45) to (50), (52) to (55), (57) to (62), (64) to (69), (71) to (74) constitute the first low-speed inter-board communication function area; Pins (76) and (77) constitute the second low-speed inter-board communication function area; pins (79) to (84) constitute the first low-speed debugging and downloading function area; pins (86) to (88), (90) to (94), (96) to (101), (103) to (106) constitute the third low-speed inter-board communication function area; pins (108) to (112) constitute the second low-speed audio and video input and output function area; Pins (114) and (115), (117) and (118), (119) and (120), (122) to (125), (127) to (130), (132) to (135) constitute the fourth low-speed inter-board communication function area; pins (137) to (145) constitute the second basic system function area; pins (147) and (148) constitute the fifth low-speed inter-board communication function area.

3. The core plate of claim 2, wherein, The core board further comprises: The multi-layer solder joint pins arranged on the same side of the core board as the first-layer solder joint pins comprise, in sequence from the direction of the first-layer solder joint pins approaching the center of the core board, a second-layer solder joint pin, a third-layer solder joint pin, a fourth-layer solder joint pin and a fifth-layer solder joint pin, wherein the second-layer solder joint pin to the fifth-layer solder joint pin are in square distribution, the second-layer solder joint pin and the third-layer solder joint pin each have a second opening, the first opening and the second opening are located at the same corner position, and the fourth-layer solder joint pin and the fifth-layer solder joint pin are closed squares; In counterclockwise order from the first edge to the fourth edge, the second-layer solder joint pin comprises pins (150) to (278) arranged in sequence, the third-layer solder joint pin comprises pins (279) to (399) arranged in sequence, the fourth-layer solder joint pin comprises pins (400) to (515) arranged in sequence, and the fifth-layer solder joint pin comprises pins (516) to (619) arranged in sequence, wherein pins (179), (214), (249), (307), (339), (371), (400), (429), (458), (487), (516), (542), (568) and (594) are located at the corner of the square; In the first-layer solder joint pin to the fifth-layer solder joint pin, the spacing between every two adjacent pins in the counterclockwise direction is equal; In the first-layer solder joint pin to the fifth-layer solder joint pin, every two adjacent layers of solder joint pins are arranged at equal intervals, and every two adjacent layers of solder joint pins are arranged in staggered positions.

4. The core plate of claim 3, wherein, Pins (236), (237), (477) and (478) constitute a JTAG interface area; Pins (451), (452), (204) and (205) constitute a mirror image download area; The JTAG interface area, the mirror image download area and the low-speed debugging serial port constitute a debugging download functional area.

5. The core plate of claim 4, wherein, pin (320), pin (321), pin (373), pin (245), pin (246), pin (250), pin (251), pin (372), pin (587), pin (588), pin (361), pin (362), pin (242), pin (243), pin (367), pin (368), pin (204), pin (205), pin (451), pin (452), pin (448), pin (449), pin (327), pin (326), pin (329), pin (330), pin (202), pin (201), pin (332), pin (333), pin (198), pin (199), pin (335), pin (336), pin (454), pin (455), pin (207), pin (208), pin (210), pin (211), pin (343), pin (344), pin (218), pin (219), pin (569), pin (570), pin (572), pin (573), pin (462), pin (463), pin (221), pin (222), pin (459), pin (460), pin (340), pin (341), pin (378), pin (379), pin (376), pin (375), pin (491), pin (492), pin (257), pin (256), pin (253), pin (254), pin (489), pin (488), pin (494), pin (495), pin (259), pin (382), pin (381), pin (384), pin (385), pin (501), pin (500), pin (497), pin (498), pin (263), pin (262), pin (260), pin (506), pin (507), pin (266), pin (265), pin (268), pin (269), pin (391), pin (390), pin (387), pin (388), pin (504), pin (503), pin (271), pin (272), pin (393), pin (510), pin (509), pin (512), pin (513), pin (278), pin (277), pin (274), pin (275), pin (397), pin (396), pin (394), pin (324), pin (323), pin (443), pin (442), pin (196), pin (195), pin (445), pin (446), pin (215), pin (216), pin (358), pin (359), pin (346), pin (347), pin (157), pin (158), pin (178),Pin (180), pin (181), pin (213), pin (248), pin (338), pin (370), pin (399), pin (457), pin (486), pin (515), pin (567), pin (593), pin (619) constitute high-speed inter-board communication function area; The first low-speed inter-board communication functional area, the second low-speed inter-board communication functional area, the third low-speed inter-board communication functional area, the fourth low-speed inter-board communication functional area, the fifth low-speed inter-board communication functional area and the high-speed inter-board communication functional area constitute an inter-board communication functional area.

6. The core plate of claim 5, wherein, pin (532), pin (533), pin (166), pin (167), pin (297), pin (298), pin (163), pin (164), pin (535), pin (536), pin (419), pin (420), pin (295), pin (294), pin (169), pin (170), pin (425), pin (426), pin (303), pin (304), pin (422), pin (541), pin (423), pin (172), pin (173), pin (300), pin (301), pin (186), pin (187), pin (189), pin (190), pin (314), pin (315), pin (317), pin (318), pin (436), pin (437), pin (308), pin (309), pin (311), pin (312), pin (430), pin (431), pin (433), pin (434), pin (183), pin (184), pin (292), pin (291), pin (413), pin (414), pin (526), pin (527), pin (160), pin (161), pin (288), pin (289), pin (529), pin (530), pin (407), pin (408), pin (285), pin (286), pin (154), pin (155), pin (410), pin (411), pin (523), pin (524), pin (279), pin (280), pin (520), pin (521), pin (404), pin (405), pin (282), pin (283), pin (151), pin (152), pin (428), pin (575), pin (576), pin (227), pin (349), pin (350), pin (468), pin (469), pin (224), pin (225), pin (465), pin (466), pin (230), pin (231), pin (581), pin (582), pin (355), pin (356), pin (228), pin (578), pin (579), pin (352), pin (353), pin (471), pin (472), pin (474), pin (475), pin (233), pin (234), pin (584), pin (585), pin (481), pin (517), pin (518), pin (480), pin (239), pin (240), pin (364), pin (365), pin (483), pin (484), pin (590), pin (591), pin (401), pin (402), pin (439),Pin (440), pin (192), pin (193), pin (416), pin (175), pin (176), pin (306), pin (417), pin (539), pin (538) constitute high-speed audio and video input and output function area; The first low-speed audio and video input and output functional area, the second low-speed audio and video input and output functional area and the high-speed audio and video input and output functional area constitute an audio and video input and output functional area.

7. The core plate of claim 6, wherein, In the fifth layer of the solder joint pins, the pins (543), (544), (546), (547), (549), (550), (552), (553), (555), (556), (558), (559), (561), (562), (564), (565), (595), (596), (598), (599), (601), (602), (604), (605), (607), (608), (610), (611), (613), (614), (616), (617) are extension pins.

8. The core plate of claim 7, wherein, The remaining pins among the pins (1) to (619) are anti-crosstalk digital pins.

9. The core plate of claim 3, wherein, The pins in the first layer of the solder joint pins to the fifth layer of the solder joint pins are circular, and the diameter of the circle is 0.5mm-1.2mm. In the first layer of the solder joint pins to the fifth layer of the solder joint pins, the center distance between adjacent pins on the same layer is 0.8mm-1.5mm, and the adjacent two layers of the solder joint pins arranged in a staggered manner are projected on the corresponding edge, and the center distance between the two adjacent solder joint pins is 0.4mm-0.75mm. The centers of the adjacent two layers of the solder joint pins arranged in a staggered manner on the same edge are in the direction perpendicular to the edge, and the center distance between the centers of the adjacent two layers of the solder joint pins is 1.5mm-2.5mm. The center distance between the center of the pin on the first layer of the solder joint pins and the edge of the core board is 0.8mm-1.5mm.

10. The core plate of claim 3, wherein, The core board further comprises a device area in the area formed by the fifth layer of the solder joint pins, and the device area is provided with active devices and / or passive devices. The center distance between the center of the pin on the fifth layer of the solder joint pins and the edge of the device area is 1.5mm-2.5mm, and the size of the device area is less than or equal to 30mm×30mm.

11. The core plate of claim 3, wherein, The first layer of the solder joint pins is used to transmit low-speed signals below 2.5GHz, and the second layer of the solder joint pins, the third layer of the solder joint pins, the fourth layer of the solder joint pins and the fifth layer of the solder joint pins are used to transmit high-speed signals below 10GHz.

Images