Reconfigurable half-band cascade metering method, chip architecture and chip

Abstract

The invention discloses a reconfigurable half-band cascade metering method, a chip architecture and a chip, and the metering method comprises the steps: carrying out the improvement of a metering method of an existing CIC architecture, replacing all low-pass filters with half-band filters HBF, and carrying out the metering of an input signal through employing the improved metering method; the chip architecture is used for realizing the recording method and specifically comprises an analog ADC (Analog to Digital Converter), the first processor, a first SPI (Serial Peripheral Interface) module, a first register, a random access memory, a second processor, a second register, a second SPI module and a third register, the chip adopts the chip framework; according to the method, the problem of relatively large metering errors is solved, the method and the architecture are proved to have excellent operation capability and extremely low hardware implementation cost in a power grid frequency fluctuation scene, and meanwhile, the method and the architecture have relatively high reconstruction flexibility to face complex multi-metering application scenes.

Description

Technical Field

[0001] This invention relates to a metering method, chip architecture, and chip, particularly a reconfigurable half-band cascaded metering method, chip architecture, and chip. Background Technology

[0002] This section provides only background information relevant to this disclosure and is not necessarily prior art.

[0003] With the development of social practice and the increasing requirements for power grid testing, the need for high-precision measurement results even under conditions of power grid frequency fluctuations has become an essential performance test item for metering chips. The fundamental frequency of power supplied by power grids both domestically and internationally is generally a stable frequency band; for example, the State Grid's power grid operates at a frequency of 50Hz.

[0004] In actual operation, due to nonlinear load user issues, power quality problems occur, causing fluctuations in the fundamental frequency of the power grid. The metering results (active power, RMS value, reactive power) generated by the metering chip based on the fluctuating frequency will have very large metering errors, resulting in poor chip operation, high error, or even failure to function properly.

[0005] Furthermore, the complexity of the three-phase application market and the emergence of various small application scenarios have made the time cost of frequent iterations of metering chips increasingly higher, and the flexibility requirements of metering chips have gradually changed from an option to a cost factor that must be considered.

[0006] Traditional metering chip algorithms primarily use CIC (cascade integrator comb) filters as the main filter structure, such as... Figure 1 As shown in the figure:

[0007] U(t) is the input AC signal, which can be voltage or current.

[0008] An ADC (Analog-Digital-Converter) is a commonly used digital-to-analog converter, often a second-order sigma-delta structure. Its main function is to convert sampled analog signals into digital signals to prepare for subsequent digital filters. The operating frequency of the ADC directly determines the quality of the generated signal, so it usually operates at the MHz level.

[0009] LPF (low-pass filter) is a low-pass filter. Due to its low implementation cost, CIC (Cellular Integrated Circuit) is often the preferred filter structure for low-pass filters. Low-pass filters in different locations can achieve different functions.

[0010] (1) The main purpose of the low-pass filter cascaded after the ADC is to remove the noise generated during the high-frequency sampling process of the ADC and downsample to the specified computing bandwidth.

[0011] (2) The low-pass filter after the multiplier is used to obtain the DC calculation part, which is the measurement results such as power, effective value and so on mentioned in the technical background.

[0012] (3) The low-pass filter after the high-pass filter mainly separates the fundamental component from the full-wave component.

[0013] HPF (High-pass filter) is a high-pass filter (CIC is a low-pass filter. The function of a low-pass filter is to obtain DC. When implemented using 1-CIC, it is equal to the original waveform - DC = high-pass. Therefore, CIC is also commonly used in the variation of high-pass filters). Its main purpose is to remove the DC component mixed in the input AC signal. It is also often called a CIC filter.

[0014] Hilbert filters are phase-shift filters whose main function is to shift the phase of the input signal. As we know from the technical background, phase shifting is required when calculating reactive power.

[0015] Mult (multiplication) is a simple multiplier that performs signal self-multiplication.

[0016] Based on the above traditional architecture, it can be seen that CIC is the main filter in the traditional metering chip architecture, which brings three main problems:

[0017] (1) The filter ripple can cause inconsistent gain changes when the power grid frequency fluctuates, such as Figure 2 As shown. A typical characteristic of CIC is the inconsistent fluctuation of the filter. When the power grid frequency fluctuates, the gain can differ by about -10dB, which brings obvious calculation errors, resulting in a decrease in the performance of the metering chip and the inability to use the metering results directly. Moreover, the larger the range of power grid frequency fluctuation, the worse the consistency of the metering error will be.

[0018] (2) The gain consistency problem of the filter, as explained in the technical background, CIC filters have a large gain, which is related to the filter's operating frequency and downsampling rate. When CIC filters are frequently used in digital systems, they need to be expanded / reduced (shifted), which leads to the frequent discarding of the bit width of intermediate calculation results. Ultimately, even if the input to the system is small, the error fluctuation range will be very different.

[0019] (3) Poor flexibility. As explained in the technical background, the use of CIC requires the working frequency and downsampling rate to be determined in order to confirm the specific gain of the filter. This also means that the use of all CIC filters must be combined with specific scenarios. When the required input bandwidth changes, the working frequency changes or the working clock changes, CIC will become unusable. This is very unfavorable for the complex application scenarios of metering chips and also unfavorable for product iteration.

[0020] Traditional metering chip hardware circuit implementation, such as Figure 3 As shown, it includes:

[0021] Metrology-AFE: Decoding module, the core of which is the algorithm, including ADC / phase calibration / CIC downsampling;

[0022] DSP: It implements various digital filters (CIC / BPF, etc.) required in traditional algorithms through a variety of basic operation combination instructions. The intermediate data and final results of the calculation are stored in SRAM for users to read or calculate.

[0023] Energy_CF: Energy bucket module, which integrates the power calculated by the DSP over time;

[0024] System_Controller: Clock and reset control module;

[0025] UART / SPI: Two common chip communication protocols.

[0026] The hardware implementation based on the above has the following typical characteristics:

[0027] (1) All core digital filter algorithms are decomposed into basic multiplication / addition / shifting by DSP. Therefore, there are requirements for the simplicity of the algorithm implementation and the frequency of the master clock. Otherwise, the system will fail due to the problem of data throughput.

[0028] (2) The processing of analog and digital parts is fully coupled. All analog signal processing and digital part processing are performed in the same DSP. The algorithm resources of each part are fully reused and the area is small enough.

[0029] The above analysis highlights the prominent problems of traditional metrology chip algorithms and architectures as follows:

[0030] (1) The error is unacceptable when the power grid test frequency fluctuates.

[0031] (2) The error is not consistent across different frequency fluctuation ranges.

[0032] (3) In terms of hardware implementation, if the analog part of the ADC is upgraded, or the ADC architecture is changed, or the application market has higher requirements for testing, such as wider bandwidth for signal processing, higher requirements for power data update time, etc., the entire system will need to be replaced, and the time and manpower costs will be enormous.

[0033] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0034] Purpose of the invention: The technical problem to be solved by the present invention is to provide a reconfigurable half-band cascade metering method, chip architecture and chip, which addresses the shortcomings of the prior art.

[0035] To address the aforementioned technical problems, this invention discloses a reconfigurable half-band cascade metering method, chip architecture, and chip.

[0036] The measurement method includes:

[0037] The metering method of the existing CIC architecture is improved by replacing all low-pass filters with half-band filters (HBF) and using the improved metering method to meter the input signal.

[0038] Furthermore, the improved measurement method for measuring the input signal specifically includes:

[0039] Step 1: The input signal is passed sequentially through the sampling circuit module, ADC module, phase calibration module, CIC module, compensation filter module and DC removal module to obtain the full-wave signal;

[0040] Step 2: Pass the full-wave signal through the fundamental-wave full-wave selection module to obtain either the fundamental-wave signal or the full-wave signal;

[0041] Step 3: Calculate the frequency and phase of the input signal using the full-wave signal;

[0042] Step 4: Select the fundamental signal and the full-wave signal to calculate the effective values ​​of current and voltage, active power, reactive power and apparent power respectively.

[0043] Furthermore, the DC-DC converter described in step 1 is used to convert the input signal into a full-wave signal, specifically including:

[0044] A cascaded half-band filter (HBF) is used to extract the DC component from the input signal;

[0045] The DC component is subtracted from the input signal to obtain the full-wave signal.

[0046] Furthermore, the fundamental full-wave selection module described in step 2 is used to generate a fundamental wave signal based on the full-wave signal and to select and output it, specifically including:

[0047] Six cascaded half-band filters (HBFs) are used to filter out harmonics from the full-wave signal to obtain the fundamental signal.

[0048] The input full-wave signal and the fundamental wave signal are connected in parallel, and one of them is selected for output.

[0049] Furthermore, step 3, which involves using the full-wave signal to calculate the frequency and phase of the input signal, specifically includes:

[0050] The full-wave signal is passed sequentially through a bandpass filter (BPF) module and a zero-crossing detection module to obtain the frequency and phase of the input signal.

[0051] Furthermore, the calculation of the effective values ​​of current and voltage in step 4 specifically includes:

[0052] The signal, which is selected as the fundamental signal or the full-wave signal as the input signal, passes through a multiplier, a half-band filter (HBF), a secondary calibration module, a Sqrt module, and a secondary compensation module in sequence to obtain the effective values ​​of current and voltage in the signal.

[0053] Furthermore, the calculation of active power in step 4 specifically includes:

[0054] The signal, which is selected as either the fundamental signal or the full-wave signal as input, passes through a multiplier, a half-band filter (HBF), a secondary calibration module, and a secondary compensation module in sequence to obtain the active power in the signal.

[0055] Furthermore, the calculation of reactive power in step 4 specifically includes:

[0056] The signal, which is selected as the fundamental wave signal or the full wave signal as the input signal, passes through the Hilbert filter, multiplier, half-band filter HBF, secondary calibration module and secondary compensation module in sequence to obtain the reactive power in the signal.

[0057] Furthermore, the calculation of apparent power in step 4 specifically includes:

[0058] The active power and the reactive power are respectively multiplied, then added together using an adder, and finally passed through a Sqrt module to obtain the apparent power.

[0059] Furthermore, the CIC module mentioned in step 2 specifically includes:

[0060] Three cascaded CIC filters and two half-band filters.

[0061] Furthermore, in the CIC module described in step 2, the integration part is implemented in hardware.

[0062] Furthermore, the compensation filter module described in step 1 specifically includes:

[0063] The compensation method using second-order interpolation polynomials has the following transfer function:

[0064]

[0065] Where H(z) represents the input-output ratio in the Laplace transform domain, c is a constant, and z represents the Laplace transform unit; thus, we obtain:

[0066]

[0067] Where z = e jω The circle represents the unit circle as defined by Laplace, || represents the absolute value or amplitude, and ω represents the angular frequency.

[0068] Furthermore, the half-band filter HBF described in step 1 is implemented in hardware, and its transfer function is:

[0069]

[0070] Furthermore, in the DC-DC removal module described in step 1, the number of cascaded half-band filters (HBFs) is set according to the bandwidth.

[0071] Furthermore, in the compensation filter module described in step 1, the constant c is set to 9.75.

[0072] This invention also proposes a reconfigurable half-band cascaded metering chip architecture for implementing the aforementioned metering method, specifically including:

[0073] An analog ADC is used to sample analog signals from the circuit to be measured, convert them into digital signals, and then send them to the first processor.

[0074] The first processor is configured to detect frequency and phase information in the input digital signal and convert the digital signal into an original waveform;

[0075] The output of the first processor is connected to the first SPI module and the first register, respectively, wherein the first SPI module provides the raw waveform of the first processor output to the outside world;

[0076] The first register is used to store the original waveform output by the first processor and send it to the random access memory and the second processor. The random access memory is used to cache waveform data and intermediate results of the processor.

[0077] The second processor is used to calculate the effective values ​​of current and voltage, reactive power, active power and apparent power in the original waveform;

[0078] The second processor is connected to a second register, which is used to store the calculation results of the second processor;

[0079] The second register is connected to the second SPI module, through which the above calculation results are sent to an external MCU;

[0080] The second SPI module is bidirectionally connected to an external MCU and is used to receive operation commands from the external MCU;

[0081] The second SPI module is bidirectionally connected to the third register, which is used to store the configuration file in the architecture.

[0082] Furthermore, the first processor includes: a phase calibration module, a CIC module, a compensation filter module, a DC removal module, a bandpass filter (BPF), a zero-point detection module, and a fundamental full-wave selection module.

[0083] Furthermore, the DC-DC removal module and the fundamental full-wave selection module include cascaded half-band filters (HBF).

[0084] Furthermore, the cascaded half-band filter HBF is implemented using a half-band accelerator, specifically including:

[0085] Using the DSP in the first process, the half-band accelerator is directly invoked using feature instructions to achieve the filtering result.

[0086] Furthermore, the fundamental wave / full wave selection module is used to separate the fundamental wave signal and the full wave signal, and output them as the original waveform.

[0087] Furthermore, the second processor includes: a multiplier, a secondary calibration module, a Sqrt module, a secondary compensation module, a Hilbert filter, and an adder.

[0088] Furthermore, the architecture also includes a fast detection module connected to the first processor, which performs feature detection based on the raw waveform it generates.

[0089] Furthermore, the feature detection includes: overcurrent / undercurrent detection, overvoltage / undervoltage detection, sudden rise / fall detection, and zero-crossing detection.

[0090] Furthermore, the architecture also includes an energy bucket module connected to the second register, which processes the data stored in the second register to obtain average power, average RMS value and energy data, and performs energy accumulation and pulse output.

[0091] The present invention also provides a metering chip, which is obtained using the aforementioned architecture design.

[0092] Beneficial effects:

[0093] 1. This invention solves the problem of large measurement errors caused by frequency fluctuations in traditional metering chips.

[0094] 2. This invention has made structural adjustments at the hardware architecture level to adapt to and verify the feasibility of the metering method, proving that this method and architecture have excellent operating capabilities and extremely low hardware implementation costs in the scenario of power grid frequency fluctuations.

[0095] 3. This invention also has considerable reconfiguration flexibility to cope with complex multi-metering application scenarios. Attached Figure Description

[0096] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0097] Figure 1 This is a schematic diagram of a traditional metering chip architecture.

[0098] Figure 2 This is a schematic diagram of the CIC amplitude-frequency steep slope.

[0099] Figure 3 This is a schematic diagram of the hardware circuit implementation of a traditional metering chip.

[0100] Figure 4 This is a schematic diagram of the reconfigurable half-band cascade metering method in this invention.

[0101] Figure 5 This is a schematic diagram of the CIC filter structure.

[0102] Figure 6 This is a schematic diagram of the in-band amplitude-frequency response of a CIC filter.

[0103] Figure 7 This is a schematic diagram illustrating the implementation method and bit width calculation of the CIC filter.

[0104] Figure 8 This is a schematic diagram of the CIC integrator structure.

[0105] Figure 9 This is a schematic diagram of the CIC differentiator structure.

[0106] Figure 10 This is a schematic diagram of the system frequency characteristics of a CIC filter.

[0107] Figure 11 This is a schematic diagram of the compensation filter implementation structure.

[0108] Figure 12 This is a schematic diagram of the amplitude-frequency response of a half-band filter.

[0109] Figure 13 This is a schematic diagram of a half-band filter implementation.

[0110] Figure 14 This is a schematic diagram of a reconfigurable half-band cascaded metering chip architecture.

[0111] Figure 15 This is a schematic diagram of the amplitude-frequency characteristics of the CIC+compensation filter+half-band filter.

[0112] Figure 16 This is a schematic diagram comparing CIC / HBF errors. Detailed Implementation

[0113] This application proposes a novel metering method and metering chip architecture based on a half-band cascaded digital filtering system. It fundamentally solves the problem of large metering errors caused by frequency fluctuations in traditional metering chips. Furthermore, structural adjustments were made at the hardware architecture level to adapt to and verify the algorithm's feasibility. This demonstrates that the algorithm and architecture exhibit excellent performance and extremely low hardware implementation costs in scenarios with fluctuating power grid frequencies, while also possessing considerable reconfiguration flexibility to handle complex multi-metering application scenarios. The specific technical solution is as follows:

[0114] Part 1, a reconfigurable half-band cascaded metering method, such as Figure 4 As shown, the details are as follows:

[0115] The entire low-pass filter of the traditional metering chip, which is based on the CIC architecture, is replaced with an HBF (half-band filter). The specific method includes the following steps:

[0116] Step 1: The input signal is sequentially passed through a sampling circuit module, an ADC module, a phase calibration module, a CIC module, a compensation filter module, and a DC-DC de-amplification module to obtain a full-wave signal. The DC-DC de-amplification module is used to convert the input signal into a full-wave signal, specifically including:

[0117] A cascaded half-band filter (HBF) is used to extract the DC component from the input signal;

[0118] The DC component is subtracted from the input signal to obtain the full-wave signal.

[0119] Step 2: Pass the full-wave signal through the fundamental full-wave selection module to obtain either a fundamental signal or a full-wave signal; the fundamental full-wave selection module is used to generate a fundamental signal based on the full-wave signal and perform selection output, specifically including:

[0120] Six cascaded half-band filters (HBFs) are used to filter out harmonics from the full-wave signal to obtain the fundamental signal.

[0121] The input full-wave signal and the fundamental wave signal are connected in parallel, and one of them is selected for output.

[0122] Step 3, using the full-wave signal to calculate the frequency and phase of the input signal, specifically includes:

[0123] The full-wave signal is passed sequentially through a bandpass filter (BPF) module and a zero-crossing detection module to obtain the frequency and phase of the input signal.

[0124] Step 4: Select the fundamental signal and the full-wave signal to calculate the effective values ​​of current and voltage, active power, reactive power and apparent power respectively.

[0125] The calculation of active power specifically includes:

[0126] The signal, which is selected as either the fundamental signal or the full-wave signal as input, passes through a multiplier, a half-band filter (HBF), a secondary calibration module, and a secondary compensation module in sequence to obtain the active power in the signal.

[0127] The calculation of the effective values ​​of current and voltage specifically includes:

[0128] The signal, which is selected as the fundamental signal or the full-wave signal as the input signal, passes through a multiplier, a half-band filter (HBF), a secondary calibration module, a Sqrt module (square root module, using successive approximation method), and a secondary compensation module in sequence to obtain the effective values ​​of current and voltage in the signal.

[0129] The calculation of reactive power specifically includes:

[0130] The signal, which is selected as the fundamental wave signal or the full wave signal as the input signal, passes through the Hilbert filter, multiplier, half-band filter HBF, secondary calibration module and secondary compensation module in sequence to obtain the reactive power in the signal.

[0131] The calculation of apparent power specifically includes:

[0132] The active power and the reactive power are respectively multiplied, then added together using an adder, and finally passed through a Sqrt module to obtain the apparent power.

[0133] The basic modules are as follows:

[0134] Sampling circuit: Generally, manganin resistors or Rogowski coils are used to sample electrical signals.

[0135] ADC: Implemented using the traditional 2nd order Sigma-Delta method, with a working clock speed of 6.5536MHz.

[0136] Phase calibration: The phase of the sampled signal is adjusted by delaying the digital register.

[0137] CIC:

[0138] The ADC has a sampling rate of 6.5536MHz. After passing through a cascaded 3rd-order CIC comb filter with a downsampling rate of 128, and two half-band filters (with a fixed downsampling rate of 2), it outputs instantaneous voltage / current values ​​at 12.8kHz. The integration part of the CIC is implemented in hardware, while the differentiation part and subsequent signal processing are implemented using the DSP's basic instruction set. The DSP operates in a clock domain of 26.2144MHz, meaning that the DSP performs calculations for each input sampling point over 26.2144M / (6.5536M / (128*2*2)) = 2048 clock cycles.

[0139] The transfer function of the CIC filter is:

[0140]

[0141] Where R is the delay factor, typically 1 or 2, M is the downsampling rate, and N is the order of the cascade. H(z) represents the input / output ratio in the Laplace transform domain, and z represents the Laplace transform unit.

[0142] Its structure is as follows Figure 5 As shown:

[0143] When R=1, M=128, N=3, and fs=6.5MHz, the in-band amplitude-frequency response of the CIC filter is as follows: Figure 6 As shown, the -3dB point is at 3350Hz, and the in-band amplitude-frequency response is not flat enough. To ensure the metering accuracy requirements within the bandwidth, a compensation filter needs to be added to make the amplitude-frequency response of the digital filter sufficiently flat within the metering bandwidth.

[0144] The implementation method and bit width calculation of CIC filters are as follows: Figure 7 As shown:

[0145] It contains an integrator, a downsampling module, and a differentiating module, wherein:

[0146] Integrators such as Figure 8 As shown, a three-stage cascade is used, with the transfer function of each stage being Y(n) = Y(n-1) + X(n), which is implemented in hardware.

[0147] The differentiator and integrator are symmetrical, such as Figure 9 As shown, a 3-stage cascade is also used, with the transfer function of each stage being Y(n) = X(n) - X(n-1), which is implemented by DSP.

[0148] The CIC filter has a gain of (R*M)^N, therefore it should be extended. log2((R*M) N = N*log2(R*M) bits.

[0149] In this application, the 1-bit ADC code stream 0 and 1 are converted to two's complement 1 and -1 respectively, and the 6.5M (or 3.2M) format is 2-bit data of sfix2_0. The maximum CIC downsampling is M=128, and the delay factor R=1, so the bit width needs to be expanded to input_width+N*log2(R*M)=2+3*log2(128)=23 bits, which is the integrated sfix25_23 (downsampled to 128) data. The low-order bits of the integrated data are padded with 0 to expand it into sfix32_30 for the DSP to perform differentiation and subsequent operations.

[0150] The CIC calculation gain is related to the downsampling and filter operating frequency, which means that repeated use of the filter in the calculation can cause cumulative error problems.

[0151] Compensation filter:

[0152] The CIC compensated filter employs an interpolated second-order polynomial (ISOP) compensation method, and its transfer function is:

[0153]

[0154] When the parameters of the CIC filter are fixed, the parameters of the ISOP filter can be obtained using traditional filter design methods.

[0155] In this design, c is set to 9.75. With the DSP operating frequency at 26MHz (ADC bitstream downsampled from 6.5MHz to 51.2kHz), the system frequency characteristics before and after compensation are as follows: Figure 10 As shown. Compared to the amplitude-frequency response before compensation, the amplitude response within the bandwidth after compensation is flatter and has a larger bandwidth, with the -3dB point at 4750Hz.

[0156] The structure of the compensation filter is as follows Figure 11 As shown, the multiplication and division operations can be implemented using the DSP's shift instructions.

[0157] Half-band filter:

[0158] Because the in-band response of the CIC filter is not flat enough, it is generally not used directly to reduce the bandwidth to the required level. The HBF (Hyperband Filter) has the characteristics of a flat in-band amplitude-frequency response and a halved bandwidth. Therefore, several (two in this patent) HBFs are cascaded after the CIC+COMP to adjust the measurement bandwidth. The HBF is also used in the analysis of the fundamental / DC component. Without considering the influence of interharmonics and even harmonics, extremely accurate fundamental / DC components can be obtained without compensation. The actual half-band filter is a hardware accelerator module, convenient for DSP to call, rather than implemented using a basic instruction set.

[0159] The transfer function of the half-band filter is:

[0160]

[0161] The amplitude-frequency response of a half-band filter is as follows Figure 12 As shown, after the signal passes through the half-band filter, the bandwidth is halved, and the amplitude-frequency response in the passband is flatter than that of CIC.

[0162] The implemented HBF algorithm model is as follows: Figure 13 As shown.

[0163] Multiplying by 1 / 2, 1 / 8, and 9 / 16 can all be achieved by shifting. 9 / 16 = 1 / 2 + 1 / 8 can be broken down into shifting and addition.

[0164] Therefore, the entire half-band filter can be implemented in hardware. A half-band filter needs to store 7 intermediate values. So when the half-band filter is frequently called in the system, the computation part can be fully reused, and the intermediate values ​​are stored in a specific memory to achieve the minimum area cost.

[0165] All low-pass filters used to separate the full-wave, fundamental, and DC components are cascaded in a half-band configuration. Taking a full-wave sampling frequency of 25.6 kHz as an example, with a fundamental frequency of 50 Hz, if the fundamental frequency needs to be sampled at 4 points (4 * 50 = 200 Hz), then the number of cascaded half-band filters is log2(25.6 kHz / 200 Hz) = 7. If it is necessary to further obtain the DC component and place the zero point of the filtered DC at 25 Hz, then the number of cascaded half-band filters is log2(25.6 kHz / 25 Hz) = 9.

[0166] The multiplier, Hilbert filter, secondary correction, secondary compensation, and other components mentioned in the diagram are not fundamentally different from the traditional CIC architecture.

[0167] Of course, the algorithms and architectures using half-band cascading also have their own shortcomings, as follows:

[0168] (1) The computational cost is enormous. The complexity of half-band filters is much higher than that of CIC filters, so the computational cost is very high. Taking an ADC sampling rate of 1.6MHz as an example, assuming that the full-wave sampling rate is 25.6KHz and the chip's operation clock is 6.5536MHz, then the actual number of cycles that can be used for calculation is 6.5536MHz / 25.6KHz = 256.

[0169] Breaking down the half-band filter into each addition and subtraction step, if each step can only perform one basic addition or subtraction, then at least 17 cycles are needed to complete the pure calculation step. The actual hardware calculation requires 25 cycles for data storage and retrieval. Considering that actual metering chips usually have 3 channels sampling in parallel, then at least (17+25)*3=126 cycles are needed to complete the calculation of one half-band. However, the algorithm often needs to cascade at least 6-7 half-bands, which is far greater than the number of clock cycles that can be used in actual calculation.

[0170] (2) High hardware implementation cost. The calculation process requires multiple multiplications / additions, which brings additional hardware overhead and high data throughput requirements. In contrast, CIC only requires extremely simple serial addition.

[0171] (3) The step response time of the half-band filter is longer than that of the CIC, which means that the stabilization time of the metrology results will be longer compared with the traditional architecture.

[0172] From an algorithmic perspective, half-band cascading offers far superior performance and flexibility compared to traditional CIC-based algorithms. However, it fails to address two fundamental issues in terms of hardware implementation: massive computational demands and high hardware implementation costs.

[0173] In actual product implementation, the above two application problems will be fundamentally solved by optimizing the digital design DSP and using the HBF hardware accelerator. The specific technical solution is the second part of this application, as detailed below.

[0174] The second part describes a reconfigurable half-band cascaded metering chip architecture, such as... Figure 14 As shown, it includes:

[0175] Analog ADC: Supports N channels, corresponding to the I(t) / U(t) sampling circuit part of the algorithm, Sigma-Delta ADC implementation.

[0176] CORE_1 (Processor 1): Primarily responsible for phase calibration, CIC filter, compensation filter, and half-band cascade algorithms. It separates the fundamental and full-wave frequencies and removes DC. It can optionally implement a bandpass filter (BPF) algorithm path, performing zero-crossing detection and frequency / phase measurement methods. The half-band cascade algorithm is implemented using a half-band accelerator. The DSP directly calls the half-band accelerator using characteristic instructions and implements the filtering result, as described when discussing half-band filter characteristics. Here, N half-band filters can be cascaded; the DSP only needs to repeatedly call specific instructions to achieve this, without additional area overhead. The remaining CIC filters, compensation filters, etc., are implemented using software instructions.

[0177] FD (Fast Detection): For the sampling points and separated fundamental / full wave data obtained from CORE_1, it can perform characteristic detections specific to the field of electric power measurement, such as overcurrent / undercurrent, overvoltage / undervoltage, sudden rise / fall, and zero-crossing detection. This module is not shown in the algorithm diagram and is a signal coprocessing module independent of the algorithm module.

[0178] SPI(out): The fundamental and full-wave data separated from CORE_1 are actively uploaded to an external receiving module via the IO protocol through the SPI protocol, allowing the software to receive and process the raw waveform data, providing greater flexibility.

[0179] REG_1 (Register 1) stores the data of the original waveform generated by CORE_1. This module can alleviate the problem of data throughput mismatch between CORE_1 and CORE_2.

[0180] SRAM (Random Access Memory): Stores waveform buffer data, intermediate results of DSP operation, etc.

[0181] CORE_2 (Processor 2): Extracts the fundamental / full-wave correlation raw waveform data from REG, implements the multiplication, square root, low-pass, phase reversal, etc. mentioned in the algorithm to obtain all instantaneous effective values / power, and converts the waveform data into actual power / effective value results.

[0182] REG_2 (Register 2): Used to store all measurement calculation results related data for CORE_2, accessible from both external and internal sources.

[0183] EGY (Energy Bucket): This module performs special processing on the instantaneous power / RMS values ​​obtained from the algorithm to obtain average power, average RMS value, and energy, and then performs energy accumulation and pulse output at a specified rate. Like the FD module mentioned above, this module is a co-processing module for the results and is not reflected in the algorithm itself.

[0184] REG_3 (Register 3): A configuration register group for the entire chip, accessible both internally and externally.

[0185] SPI / UART: Dedicated communication modules for external configuration;

[0186] CORE_1 is the hardware implementation part that is the key calculation component of the half-band cascade metering algorithm proposed in this application.

[0187] The above hardware architectures have several key features.

[0188] 1. The sampling channel decoding part of the ADC is separated from the metering data calculation part, and is implemented using two DSPs.

[0189] 2. The interaction between decoding and measurement data is only through an intermediate register.

[0190] 3. All surrounding modules can obtain the raw sampling data processed by CORE_1 for processing (such as FD), and can also obtain the CORE_2 result data processed by the metering chip in the default way for arbitrary processing (such as EGY).

[0191] The above architecture has the following key advantages:

[0192] 1. For mixed-signal chips, analog or digital updates often mean that the entire chip needs to be redeveloped. However, under this hardware architecture, the only modules that are strongly coupled with the analog Sigma-Delta ADC are CIC and phase calibration reflected in the algorithm. When the analog part needs to be upgraded iteratively, the entire architecture can be upgraded simply by replacing the CIC filter with another processing method.

[0193] 2. In the power industry, the original waveform data restored by the mixed-signal method often requires different processing methods under specific environments. Under this hardware architecture, the original default processing method provided by CORE_2 can be used, or the original waveform data can be transmitted to the outside via SPI for further processing. Furthermore, if the default processing algorithm needs to be changed, only the instructions of CORE_2 need to be changed to realize multiple processing methods for the original waveform data.

[0194] 3. The original waveform data usually requires adjustable bandwidth. If the bandwidth of the half-band cascade-based algorithm needs to be changed, it is only necessary to increase or decrease the number of half-band cascades in the CORE_1 algorithm instruction to achieve the goal. It does not require the previous complicated CIC downsampling rate adjustment, gain adjustment, module adjustment, etc.

[0195] All of the above advantages are aimed at achieving product flexibility and reconfigurability.

[0196] Part Three: A Metering Chip

[0197] This invention proposes a chip, a metering chip designed with the above-described architecture, which measures the signal to be measured using the above-described method.

[0198] Part Four, Testing and Verification, specifically includes:

[0199] The algorithm system based on half-band cascading has the following advantages:

[0200] 1. Sufficiently flat passband. A flat passband can solve the inherent problem of power grid frequency fluctuations. Even with a wide range of power grid frequency fluctuations, very high metering accuracy can still be achieved. Algorithm simulations using Matlab, comparing the differences between CIC and HBF, can yield results such as... Figure 15 and Figure 10 The simulation results are shown.

[0201] It can be observed that the gain difference between the two cascaded half-band sampling data from 50Hz to 1000Hz is only 0.0002627-0.007915, while the sampling data obtained by CIC alone has a significant attenuation of 0.2755dB from 50Hz. Therefore, subsequent calculations will need to compensate for the gain loss caused here.

[0202] 2. The filter has no additional gain. The filter's response within the passband is essentially 0dB, eliminating the need for additional discarding or carrying during calculations. This minimizes the impact of intermediate truncation errors and accumulated errors, resulting in excellent error consistency. As shown in Table 1, by implementing a 32-bit computation width algorithm using actual hardware RTL and providing different amplitude excitation inputs, the half-band cascaded system shows almost no error difference, while the CIC system fluctuation error is on the order of ten thousandths.

[0203] Table 1 Relationship between Measurement Range and Error

[0204] Calculate the bit width (32-bit fixed-point number). Half-band system Traditional CIC 1 / 10 range 1％ 2％ 1 / 2 range 1％ 1％ Full scale 1％ 3％

[0205] 3. Sufficient flexibility. The device characteristics of half-band filters make them independent of the filter's operating frequency and have a fixed downsampling rate. Therefore, for a given computing bandwidth, it is sufficient to cascade multiple half-band filters to achieve the required computing bandwidth. The only drawback is that the downsampling rate must be 2N.

[0206] 4. Minimal frequency deviation impact. The system algorithm was simulated using Matlab, taking half the full-wave range and 40% harmonic content. The fundamental frequency error was calculated, i.e., a fluctuation (10%) within the grid frequency range of 45-55Hz. Based on the power error calculated for different systems, Table 2 is as follows:

[0207] Table 2 Relationship between Frequency Deviation and Error

[0208]

[0209]

[0210] like Figure 16 As shown, it can be seen that the traditional CIC architecture is better as it gets closer to 50Hz, and the overall trend is parabolic. However, the error curve proposed in this application is basically linear, and frequency fluctuations have almost no impact on the measurement.

[0211] The above advantages address the calculation error problem caused by power grid frequency fluctuations, while providing sufficient flexibility, making it very suitable for the ever-changing and complex application needs and product iteration requirements in the metering field.

[0212] In its specific implementation, this application provides a computer storage medium and a corresponding data processing unit. The computer storage medium is capable of storing a computer program, which, when executed by the data processing unit, can run the invention's description of a reconfigurable half-band cascade metering method, chip architecture, and chip, as well as some or all of the steps in various embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0213] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented using computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of computer programs, i.e., software products. These computer program software products can be stored in a storage medium and include several instructions to cause a device containing a data processing unit (which may be a personal computer, server, microcontroller, MCU, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0214] This invention provides a reconfigurable half-band cascade metering method, chip architecture, and chip concept and method. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A reconfigurable half-band cascade quantization method, characterized in that, The application relates to an improved metering method of an existing CIC architecture, wherein all low-pass filters are replaced by half-band filters HBF, and the improved metering method is used to meter an input signal. The improved metering method is used to meter the input signal, and the specific method comprises the following steps:

2. The reconfigurable half-band cascade quantization method of claim 1, wherein, Step 1: the input signal is sequentially passed through a sampling circuit module, an ADC module, a phase calibration module, a CIC module, a compensation filter module and a direct current removal module to obtain a full-wave signal; Step 2: the full-wave signal is passed through a fundamental full-wave selection module to obtain a fundamental signal or a full-wave signal; Step 3: the full-wave signal is used to calculate the frequency and phase of the input signal; Step 4: the fundamental signal and the full-wave signal are selected to respectively calculate the current and voltage effective values, active power, reactive power and apparent power. The direct current removal module in step 1 is used to convert the input signal into a full-wave signal, and specifically comprises the following steps:

3. The reconfigurable half-band cascade quantization method of claim 2, wherein, A cascade half-band filter HBF is used to extract the direct current component in the input signal; The direct current component is subtracted from the input signal to obtain the full-wave signal. The fundamental full-wave selection module in step 2 is used to generate a fundamental signal according to the full-wave signal and select the output, and specifically comprises the following steps:

4. The reconfigurable half-band cascade quantization method of claim 2, wherein, Six cascade half-band filters HBF are used to filter the harmonics in the full-wave signal to obtain a fundamental signal; The input full-wave signal and the fundamental signal are connected in parallel, and one of them is selected and output. The full-wave signal is used to calculate the frequency and phase of the input signal in step 3, and specifically comprises the following steps:

5. The reconfigurable half-band cascade quantization method of claim 2, wherein, The full-wave signal is sequentially passed through a band-pass filter BPF module and a zero-crossing point detection module to obtain the frequency and phase of the input signal. The calculation of the current and voltage effective values in step 4 specifically comprises the following steps:

6. The reconfigurable half-band cascade quantization method of claim 2, wherein, The fundamental signal or the full-wave signal is selected as the input signal, and the input signal is sequentially passed through a multiplier, a half-band filter HBF, a secondary calibration module, a Sqrt module and a secondary compensation module to obtain the current and voltage effective values in the signal. The calculation of the active power in step 4 specifically comprises the following steps:

7. The reconfigurable half-band cascade quantization method of claim 2, wherein, The fundamental signal or the full-wave signal is selected as the input signal, and the input signal is sequentially passed through a multiplier, a half-band filter HBF, a secondary calibration module and a secondary compensation module to obtain the active power in the signal. The calculation of the reactive power in step 4 specifically comprises the following steps:

8. The reconfigurable half-band cascade quantization method of claim 2, wherein, The fundamental signal or the full-wave signal is selected as the input signal, and the input signal is sequentially passed through a Hilbert filter, a multiplier, a half-band filter HBF, a secondary calibration module and a secondary compensation module to obtain the reactive power in the signal. The calculation of the apparent power in step 4 specifically comprises the following steps:

9. The reconfigurable half-band cascade quantization method of claim 2, wherein, The active power and the reactive power are respectively passed through multipliers, then added by an adder and passed through a Sqrt module to obtain the apparent power. The CIC module in step 2 specifically comprises the following steps:

10. The reconfigurable half-band cascade quantization method of claim 2, wherein, Three cascade CIC filters and two-stage half-band filters. The integral part in the CIC module in step 2 is realized by hardware.

11. The reconfigurable half-band cascade quantization method of claim 10, wherein, The compensation filter module in step 1 specifically comprises the following steps:

12. The reconfigurable half-band cascade quantization method of claim 2, wherein, An interpolation second-order polynomial compensation method is adopted, and the transfer function is as follows: ​ Wherein, H(z) represents the input-output ratio of Laplace transform domain, c is a constant, and z represents the Laplace transform unit; obtain: where z = e jω denotes the unit circle defined by Laplace, | | denotes the absolute value or amplitude, and ω denotes the angular frequency.

13. The reconfigurable half-band cascade quantization method of claim 1, wherein, The half-band filter HBF described in step 1 is implemented using hardware, and its transfer function is:

14. The reconfigurable half-band cascade quantization method of claim 3, wherein, In the direct current removal module described in step 1, the number of cascaded half-band filters HBF is set according to the bandwidth.

15. The reconfigurable half-band cascade quantization method of claim 2, wherein, In the compensation filter module described in step 1, the constant c is taken as 9.

75.

16. A reconfigurable half-band cascade meter chip architecture, comprising: For implementing the metering method of any one of claims 1 to 13, specifically comprising: an analog ADC for sampling the analog signal of the circuit to be metered and converting it into a digital signal and sending it to the first processor; the first processor for detecting the frequency and phase information in the input digital signal and converting the digital signal into an original waveform; the output of the first processor is connected with a first SPI module and a first register, wherein the first SPI module provides the original waveform output by the first processor to the outside; the first register is used to save the original waveform output by the first processor and send it to a random memory and a second processor, wherein the random memory is used to cache waveform data and intermediate results of the processor; the second processor is used to calculate the current and voltage effective value, reactive power, active power and apparent power in the original waveform; the second processor is connected with a second register, and the second register is used to store the calculation results of the second processor; the second register is connected with a second SPI module, and the calculation results are sent to an external MCU through the second SPI module; the second SPI module is bidirectionally connected with the external MCU, and is used to accept operation commands from the external MCU; the second SPI module is bidirectionally connected with a third register, and the third register is used to save configuration files in the architecture.

17. The reconfigurable half-band cascade metrology core architecture of claim 16, wherein, The first processor comprises a phase calibration module, a CIC module, a compensation filter module, a direct current removal module, a band-pass filter BPF, a zero point detection module and a fundamental full wave selection module.

18. The reconfigurable half-band cascade metrology core architecture of claim 17, wherein, The direct current removal module and the fundamental full wave selection module comprise cascaded half-band filters HBF.

19. The reconfigurable half-band cascade metrology core architecture of claim 18, wherein, The cascaded half-band filters HBF are implemented by a half-band accelerator, specifically comprising: using the DSP in the first processing, the characteristic instruction is directly called to realize the filtering result.

20. The reconfigurable half-band cascade metrology core architecture of claim 17, wherein, The fundamental full wave selection module is used to separate the fundamental signal and the full wave signal and output as an original waveform.

21. The reconfigurable half-band cascade metrology core architecture of claim 16, wherein, The second processor comprises a multiplier, a secondary calibration module, a Sqrt module, a secondary compensation module, a Hilbert filter and an adder.

22. The reconfigurable half-band cascade metrology chip architecture of claim 16, wherein, The architecture further comprises a fast detection module connected with the first processor, which performs feature detection according to the original waveform generated by the first processor.

23. The reconfigurable half-band cascade metrology core architecture of claim 22, wherein, The feature detection comprises overcurrent and undercurrent, overvoltage and undervoltage, sudden rise and sudden drop, and zero-crossing detection.

24. The reconfigurable half-band cascade metrology chip architecture of claim 16, wherein, The architecture further comprises an energy bucket module connected with the second register, which is used to process the data saved in the second register to obtain average power, average effective value and energy data, and perform energy accumulation and pulse output.

25. A metrology chip, comprising: The architecture design of any one of claims 16-24 is used.

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