Reference unit for eFuse reading module and reference resistance setting method thereof
By using a reference cell composed of AA fuses, the reference resistor is dynamically set to the midpoint of the resistance before and after fuse programming. This solves the comparison deviation problem caused by the inability of the traditional eFuse reference resistor to track changes, improves the read reliability of the eFuse, and simplifies the design.
Patent Information
- Application Number
- CN202511396896.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-26
- Publication Date
- 2026-01-06
AI Technical Summary
Traditional eFuse reference resistors cannot track process and temperature changes, leading to output deviations in the comparator circuit and affecting the reliability of the eFuse.
The reference unit, constructed using AA fuses, dynamically sets the reference resistor to the midpoint of the fuse's resistance before and after programming through a series-parallel structure. This ensures that the same change occurs under different processes and temperatures, avoiding comparison deviations.
It improves the read reliability of eFuse under various process angles and temperature conditions, simplifies the design by eliminating the need for additional calibration steps, and saves chip area.
Smart Images
Figure CN121281591A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, and in particular to a reference cell for an eFuse read module and a method for setting its reference resistor. Background Technology
[0002] An eFuse is a programmable device based on the principle of electron migration (EM). By applying a programming current, the fuse undergoes a physical structural change (melting), thus achieving non-volatile information storage. The eFuse's read function is implemented by its read module, which is responsible for converting the fuse's resistance value into the corresponding logic level "0" or "1". Its typical operating principle involves comparing the resistance of the fuse under test with a reference resistance provided by an internal reference unit using a comparator circuit such as a sense amplifier (SA), and amplifying the voltage difference to output a definite logic state.
[0003] In practical circuits, the stability of the reference resistor is crucial to the accuracy of read operations. However, traditional reference resistors are typically fixed in value and are susceptible to fluctuations due to process variations and temperature changes. These fluctuations can cause a shift in the judgment threshold of the comparator circuit, leading to read errors and significantly reducing the overall reliability of the eFuse.
[0004] AA fuses use a diffusion layer and its metal silicide layer as the fuse medium, and their programming mechanism is primarily based on electromigration. Compared to fuses made of other materials, AA fuses rely mainly on electromigration during efuse programming, exhibiting a normal distribution of resistance both before and after fusing. Conventional efuse fuses use polycrystalline silicon or metal materials, with initial resistance values between 10-200 ohms, but their post-programmed resistance values range widely (from a few kilohms to over 100 megohms). AA fuses have an initial resistance value between 100 and 200 ohms, while their post-programmed resistance is generally less than 2 kilohms, exhibiting a normal distribution. Figure 1 and Figure 2 As shown.
[0005] like Figure 3 As shown, a typical eFuse is usually organized in a matrix, consisting of word lines (WLn), bit lines (BLn), and fuse units. The bit line setting control signal (BLCn) is used for power supply, and each bit line is connected to the corresponding sensitive amplifier module (SAn) to complete the conversion of resistance to logic value.
[0006] A typical voltage-type SA module is as follows: Figure 4As shown, this module includes a reference unit, two bias units, and a comparator amplifier Amp. The reference unit consists of a reference resistor Rref and an NMOS transistor N2. The two bias units each consist of two bias resistors R and PMOS transistors P1 and P2 respectively. The fuse resistor Rm and the NMOS transistor N1 form the fuse unit under test. Figure 4 In this diagram, RD and RDb are a pair of inverted read control signals, and WL is the word line setting control signal. The working principle of this voltage-type SA module is as follows: when RDb is set to 0, WL and RD are set to 1, forming two current paths from the power supply VDD to ground VSS, generating two voltage dividers V related to the fuse resistor Rm and the reference resistor. BL and V REF After being compared by an amplifier, the logic result Q is output.
[0007] However, in traditional methods, the reference resistor Rref is a fixed resistor, which cannot track process and temperature changes, and is prone to causing V BL With V REF Deviations between the two can lead to deviations in the output of the comparator circuit, affecting the reliability of efuse.
[0008] Based on this, those skilled in the art have made improvements to the voltage-type SA module, such as... Figure 5 As shown, Figure 5 The illustration shows a 4-to-1 reference resistor selection design for the reference unit, providing four different reference resistor values to generate different comparison reference voltages Vref. This approach aims to address the impact of different process and temperature variations on the amplifier's correct output. However, this is still a "static" compensation method, unable to track dynamic temperature changes during chip operation in real time, requiring additional calibration steps to determine the optimal resistor level, and increasing chip area and design complexity (requiring the addition of multiple resistors and switching transistors). Summary of the Invention
[0009] The purpose of this invention is to provide a reference cell for an eFuse read module and a method for setting its reference resistor, so as to avoid the output deviation of the comparator circuit caused by the inability of the traditional fixed reference resistor to track changes, and to improve the read reliability of eFuse under various process angles and temperature conditions.
[0010] To achieve the above objectives, the present invention provides a reference cell for an eFuse read module, comprising: a first fuse pair, a second fuse pair, a PMOS transistor, an NMOS transistor, an inverter, and an OR logic gate;
[0011] The first fuse pair includes a first fuse and a second fuse. One end of the first fuse and one end of the second fuse are connected to the reference voltage output port, and the other end of the first fuse and the other end of the second fuse are connected to the drain of the PMOS transistor.
[0012] The second fuse pair includes a third fuse and a fourth fuse. One end of the third fuse and one end of the fourth fuse are connected to the drain of the NMOS transistor, and the other end of the third fuse and the other end of the fourth fuse are connected to the drain of the PMOS transistor.
[0013] The PMOS transistor has a gate terminal connected to a setting control signal and a source terminal connected to a power supply port.
[0014] The inverter has its input terminal connected to the setting control signal and its output terminal connected to one input terminal of the OR logic gate.
[0015] The OR logic gate has another input terminal connected to a read control signal, and its output terminal connected to the gate terminal of the NMOS transistor, while the source terminal of the NMOS transistor is grounded.
[0016] Among them, the first fuse, the second fuse, the third fuse and the fourth fuse are all AA fuses.
[0017] Optionally, the reference resistor of the reference cell is the equivalent resistance between the reference voltage output port and the drain terminal of the PMOS transistor.
[0018] Optionally, the reference resistance of the reference unit has a normal distribution characteristic.
[0019] Based on the same inventive concept, the present invention also provides a method for setting a reference resistor according to the reference cell for the eFuse read module as described above, comprising the following steps:
[0020] Provide the initial state; the resistance values of the first fuse, second fuse, third fuse, and fourth fuse are all the initial resistance values.
[0021] Entering the setting mode, the setting control signal is set to low level, a programming high voltage is applied to the power port, and the reference voltage output port is in a floating state. At this time, both the PMOS transistor and the NMOS transistor are turned on, and the resistance values of the third fuse and the fourth fuse change from the initial value to the programmed resistance value.
[0022] Exit the settings mode and set the settings control signal to high level.
[0023] Optionally, since the reference voltage output port is floating and no current flows through the first fuse and the second fuse, their resistance values remain at the initial resistance values.
[0024] Optionally, the reference resistance of the reference unit is the series value of the parallel resistance of the first fuse pair and the parallel resistance of the second fuse pair.
[0025] Optionally, the resistance value of the reference resistor in the reference unit is calculated as follows:
[0026]
[0027] Where Ro is the initial value of the resistor, and Rp is the value of the resistor after programming.
[0028] Based on the same inventive concept, the present invention also provides an eFuse read module, comprising:
[0029] The reference voltage is generated based on the reference unit for the eFuse read module as described above;
[0030] Bit line path, including the fuse resistor to be tested, used to generate bit line voltage;
[0031] The comparison amplification module has two input terminals connected to the bit line voltage and the reference voltage, respectively, for comparing the two and outputting a logic result.
[0032] Optionally, the comparison amplification module is a cross-coupled inverter structure with control.
[0033] Optionally, the operating state of the comparison amplification module is controlled by a pair of inverted setting control signals EN and ENb:
[0034] When EN=0 and ENb=1, the comparison amplification module is in sampling mode and can sample the bit line voltage and the reference voltage.
[0035] When EN=1 and ENb=0, the comparison amplification module is in the amplification comparison state, which can amplify the voltage difference between the bit line voltage and the reference voltage and output the logic result.
[0036] The reference cell and its reference resistor setting method for an eFuse read module provided by this invention have at least the following beneficial effects:
[0037] 1) Dynamic tracking: This invention utilizes the characteristic that the resistance value of AA fuses is normally distributed both at the initial value and after programming. Through circuit design, the resistance value of the reference resistor is dynamically set to the midpoint between the resistance before and after programming. The reference resistor is in the same process and temperature environment as the fuse under test, and can change in the same direction and to the same degree, thus fundamentally eliminating comparison deviation.
[0038] 2) High reliability: It avoids the output deviation of the comparator circuit caused by the inability of the traditional fixed reference resistor to track changes, and greatly improves the read reliability of eFuse under various process angles and temperature conditions;
[0039] 3) No complex calibration required: Compared with existing multi-level reference resistor value selection schemes, this invention can complete the process in one go, without the need for additional complex calibration circuits and steps, which simplifies the design and saves chip area. Attached Figure Description
[0040] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0041] Figure 1 Resistance value distribution diagram before programming AA fuse;
[0042] Figure 2 Resistance value distribution diagram after programming AA fuse;
[0043] Figure 3 This is a schematic diagram of the unit matrix of a standard efuse.
[0044] Figure 4 This is a circuit diagram of a conventional voltage-type SA module;
[0045] Figure 5 This is a circuit diagram of a conventional voltage-type SA and a reference cell;
[0046] Figure 6 A circuit diagram of a reference unit provided in an embodiment of the present invention;
[0047] Figure 7 This is a schematic diagram illustrating how the reference resistance value of a reference unit is set according to an embodiment of the present invention.
[0048] Figure 8 The circuit diagram of the eFuse read module provided in an embodiment of the present invention is shown. Detailed Implementation
[0049] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the purpose of the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only used to complement the content disclosed in the specification, for those skilled in the art to understand and read, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, if they are the same as or similar to the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.
[0050] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly stated. As used herein, the term “or” is generally used to mean “and / or” unless otherwise expressly stated. As used herein, the term “a number” is generally used to mean “at least one” unless otherwise expressly stated. As used herein, the term “at least two” is generally used to mean “two or more” unless otherwise expressly stated.
[0051] like Figure 6 As shown, this embodiment of the invention provides a reference cell for an eFuse read module, including: a first fuse pair, a second fuse pair, a PMOS transistor P1, an NMOS transistor N1, an inverter, and an OR logic gate;
[0052] The first fuse pair includes a first fuse R1 and a second fuse R2, with one end of the first fuse R1 and one end of the second fuse R2 connected together to the reference voltage output port V. REF The other end of the first fuse R1 and the other end of the second fuse R2 are connected together to the drain of the PMOS transistor P1;
[0053] The second fuse pair includes a third fuse R3 and a fourth fuse R4. One end of the third fuse R3 and one end of the fourth fuse R4 are connected to the drain of the NMOS transistor N1, and the other end of the third fuse R3 and the other end of the fourth fuse R4 are connected to the drain of the PMOS transistor P1.
[0054] PMOS transistor P1 has its gate terminal connected to the setting control signal REFb and its source terminal connected to the power supply port VDDQ.
[0055] An inverter whose input is connected to the setting control signal REFb and whose output is connected to one input of an OR logic gate;
[0056] Or logic gate, whose other input is connected to the read control signal RD, and whose output is connected to the gate of NMOS transistor N1, and the source of NMOS transistor N1 is grounded;
[0057] Among them, the first fuse R1, the second fuse R2, the third fuse R3 and the fourth fuse R4 are all AA fuses.
[0058] The AA fuse utilizes a diffusion layer and its metal silicide layer as the fuse medium. Unlike fuses made of other materials, the AA fuse primarily relies on electromigration during eFuse programming, exhibiting a normal distribution of resistance values both before and after melting. This invention uses the median resistance value of the AA fuse before and after melting as a reference resistance value. Because this value matches the actual melted state of the fuse and undergoes the same degree of change under different process characteristics and temperatures, compared to conventional fixed reference resistors, the reference unit provided by this invention avoids the output deviation of the comparator circuit caused by the inability of traditional fixed reference resistors to track changes, greatly improving the read reliability of eFuse under various process angles and temperature conditions.
[0059] In this embodiment, the reference resistor of the reference unit is the reference voltage output port V. REF The equivalent resistance between the P1 drain terminal and the PMOS transistor, and this reference resistance has a normal distribution characteristic.
[0060] Before programming, the initial resistance values of all AA fuses are normally distributed around a central value (e.g., 100-200Ω). After programming, due to the subtle physical factors affecting the programming process itself, their resistance values will also be normally distributed around a new central value. The reference unit of this invention is directly composed of four AA fuses connected in a specific series-parallel structure. After setup, its reference resistance is: Rref = (R1 / / R2) + (R3 / / R4) = (Ro / 2) + (Rp / 2), where: Ro is the initial resistance of the first resistor R1 and the second resistor R2 (remaining in an unprogrammed state), and its value has a normal distribution; Rp is the programmed resistance of the third resistor R3 and the fourth resistor R4, and its value also has a normal distribution. Therefore, the reference resistance Rref not only has a value that is the median before and after programming, but its statistical distribution characteristics are also consistent with those of a single AA fuse (normal distribution). This allows the reference resistance to perfectly "track" the changes in the fuse under test, ultimately greatly improving the reliability of the read operation.
[0061] Based on the same inventive concept, such as Figure 7 As shown, this embodiment of the invention also provides a method for setting the reference resistor of the reference cell for the eFuse read module as described above, including the following steps:
[0062] Provide the initial state, the resistance values of the first fuse R1, the second fuse R2, the third fuse R3 and the fourth fuse R4 are all the initial resistance values;
[0063] Enter setup mode, set the setup control signal REFb to low level, apply a programming high voltage to the power supply port VDDQ, and set the reference voltage output port V... REF When in a floating state, both PMOS transistor P1 and NMOS transistor N1 are turned on. Current flows from the power supply port VDDQ through the third fuse R3 and the fourth fuse R4, through the NMOS transistor N1 to ground. The resistance values of the third fuse R3 and the fourth fuse R4 change from the initial value to the programmed resistance value Rp.
[0064] Exit the setup mode and set the setup control signal REFb to high.
[0065] In this embodiment, the first fuse R1 and the second fuse R2 are connected to the reference voltage output port V. REF When floating in the air with no current flowing through it, its resistance value remains at the initial resistance value Ro.
[0066] In this embodiment, the reference resistance of the reference unit is the series value of the parallel resistance of the first fuse pair and the parallel resistance of the second fuse pair, that is, the total resistance between node a and node b. The first resistor R1 and the second resistor R2 are connected in parallel, the third resistor R3 and the fourth resistor R4 are connected in parallel, and the first fuse pair and the second fuse pair are connected in series.
[0067] In this embodiment, the resistance value Rref of the reference resistor of the reference unit is calculated as follows:
[0068]
[0069] Where Ro is the initial resistance value and Rp is the resistance value after programming.
[0070] Since the reference resistor setting method provided by this invention belongs to the same inventive concept as the reference unit for the eFuse read module described above, the reference resistor setting method provided by this invention has all the advantages of the reference unit for the eFuse read module described above. Therefore, the beneficial effects of the reference resistor setting method provided by this invention will not be described in detail here.
[0071] Based on the same inventive concept, such as Figure 8 As shown, this embodiment of the invention also proposes an eFuse read module, comprising:
[0072] A reference unit for an eFuse read module according to any one of claims 1-3, used to generate a reference voltage Vref;
[0073] The bit line path includes the resistor Rm of the fuse to be tested, which is used to generate the bit line voltage VBL;
[0074] The comparator amplifier module SA has two input terminals connected to the bit line voltage VBL and the reference voltage Vref, respectively, to compare the two and output the logic result Q.
[0075] Preferably, the comparator amplification module SA is a cross-coupled inverter structure with control, which is composed of PMOS transistors P0 to P2 and NMOS transistors N0 to N2.
[0076] Preferably, the operating state of the comparator amplification module SA is controlled by a pair of inverted setting control signals REFbEN and ENb:
[0077] When EN=0 and ENb=1, the comparator amplifier module SA is in sampling mode and can sample the bit line voltage VBL and the reference voltage Vref.
[0078] When EN=1 and ENb=0, the comparator amplification module SA is in the amplification and comparison state, which can amplify the voltage difference between the bit line voltage VBL and the reference voltage Vref and output the logic result Q.
[0079] In summary, this invention provides a reference unit for an eFuse read module and a method for setting its reference resistor. The reference resistor value is the midpoint between the resistance values of the AA fuse before and after it blows. Since it is the same as the actual state of the fuse after it blows, it will change to the same extent under different process characteristics and temperatures. Therefore, compared with conventional fixed reference resistors, the reference unit provided by this invention avoids the output deviation of the comparison circuit caused by the inability of traditional fixed reference resistors to track changes, and greatly improves the read reliability of eFuse under various process angles and temperature conditions.
[0080] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.
Claims
1. A reference unit for an eFuse read module, characterized in that, include: The system consists of a first fuse pair, a second fuse pair, a PMOS transistor, an NMOS transistor, an inverter, and an OR logic gate. The first fuse pair includes a first fuse and a second fuse. One end of the first fuse and one end of the second fuse are connected to the reference voltage output port, and the other end of the first fuse and the other end of the second fuse are connected to the drain of the PMOS transistor. The second fuse pair includes a third fuse and a fourth fuse. One end of the third fuse and one end of the fourth fuse are connected to the drain of the NMOS transistor, and the other end of the third fuse and the other end of the fourth fuse are connected to the drain of the PMOS transistor. The PMOS transistor has a gate terminal connected to a setting control signal and a source terminal connected to a power supply port. The inverter has its input terminal connected to the setting control signal and its output terminal connected to one input terminal of the OR logic gate. The OR logic gate has another input terminal connected to a read control signal, and its output terminal connected to the gate terminal of the NMOS transistor, while the source terminal of the NMOS transistor is grounded. Among them, the first fuse, the second fuse, the third fuse and the fourth fuse are all AA fuses.
2. The reference unit for the eFuse read module according to claim 1, characterized in that, The reference resistor of the reference unit is the equivalent resistance between the reference voltage output port and the drain terminal of the PMOS transistor.
3. The reference unit for the eFuse read module according to claim 1, characterized in that, The reference resistance of the reference unit has a normal distribution characteristic.
4. A method for setting a reference resistor for a reference cell in an eFuse read module according to any one of claims 1-3, characterized in that, Includes the following steps: Provide the initial state; the resistance values of the first fuse, second fuse, third fuse, and fourth fuse are all the initial resistance values. Entering the setting mode, the setting control signal is set to low level, a programming high voltage is applied to the power port, and the reference voltage output port is in a floating state. At this time, both the PMOS transistor and the NMOS transistor are turned on, and the resistance values of the third fuse and the fourth fuse change from the initial value to the programmed resistance value. Exit the settings mode and set the settings control signal to high level.
5. The reference resistor setting method according to claim 4, characterized in that, Since the first fuse and the second fuse are floating at the reference voltage output port and no current flows through them, their resistance values remain at the initial resistance values.
6. The reference resistor setting method according to claim 4, characterized in that, The reference resistance of the reference unit is the series value of the parallel resistance of the first fuse pair and the parallel resistance of the second fuse pair.
7. The reference resistor setting method according to claim 6, characterized in that, The resistance value of the reference resistor in the reference unit is calculated as follows: Where Ro is the initial value of the resistor, and Rp is the value of the resistor after programming.
8. An eFuse read module, characterized in that, include: The reference unit for the eFuse read module according to any one of claims 1-3 is used to generate a reference voltage; Bit line path, including the fuse resistor to be tested, used to generate bit line voltage; The comparison amplification module has two input terminals connected to the bit line voltage and the reference voltage, respectively, for comparing the two and outputting a logic result.
9. The eFuse read module according to claim 8, characterized in that, The comparison amplification module is a cross-coupled inverter structure with control.
10. The eFuse read module according to claim 8, characterized in that, The operating state of the comparison amplification module is controlled by a pair of inverted setting control signals EN and ENb: When EN=0 and ENb=1, the comparison amplification module is in sampling mode and can sample the bit line voltage and the reference voltage. When EN=1 and ENb=0, the comparison amplification module is in the amplification comparison state, which can amplify the voltage difference between the bit line voltage and the reference voltage and output the logic result.