Error detection during iterative decoding

Abstract

A system and related method includes a memory and processing circuitry to receive data and corresponding expected error detection code values. The processing circuitry processes data in the at least two portions by calculating and storing error detection code values for the respective portions in the memory. The processing circuitry is then to calculate a total error detection code value based on the respective error detection code values of the at least two portions. When the total error detection code value does not match the expected error detection code value, the processing circuitry is to correct the at least one portion and to correct the at least one portion by calculating an updated error detection code value for a respective one of the corrected portions and calculating an updated total error detection code value based on the updated error detection code value for each corrected portion and the stored error detection code value. The corrected portion is processed.

Description

Technical Field

[0001] This disclosure relates to systems and methods for processing error detection code (e.g., cyclic redundancy check (CRC)) checksums by iteratively updating or correcting portions of data codewords. Summary of the Invention

[0002] According to this disclosure, systems and methods are provided for processing error-detection checksums—such as Cyclic Redundancy Check (CRC)—by iteratively updating portions of data codewords in a system—such as a storage device (e.g., a solid-state drive device). Cyclic Redundancy Check (CRC) is a linear error-detection code that verifies the value of data by expanding the data with additional data without adding useful data information. The systems and methods disclosed herein enable iterative updates or corrections of memory usage and data portions to reduce the amount of latency and power consumption in processing error-detection checksums.

[0003] In some embodiments, the system (e.g., a storage device) is provided with memory and processing circuitry communicatively coupled to each other. In some embodiments, the system may be distributed between the storage device and another device separate from the storage device (e.g., a host device, such as a storage controller device), such that the host device provides processing circuitry to implement at least some of the functionalities described herein. In some embodiments, the processing circuitry receives data and an expected error detection code value corresponding to the data. The processing circuitry processes data in at least two portions by calculating the error detection code value for each corresponding portion and storing the error detection code value for each corresponding portion in memory. The processing circuitry further calculates a total error detection code value based on each error detection code value for each corresponding portion and compares the total error detection code value with the expected error detection code value. In some embodiments, when the total error detection code value does not match the expected error detection code value, the processing circuitry corrects at least one of the data portions to generate at least two corrected portions. The processing circuit further processes the at least two corrected portions of the data by calculating updated error detection code values ​​for corresponding portions in the corrected portions, and calculating an updated total error detection code value based on the updated error detection code values ​​for the corresponding portions in the corrected portions and the stored error detection code values. In some embodiments, the updated total error detection code value does not match the expected error detection code value, and therefore the processing circuit is configured to correct at least one portion of the data and recalculate the updated total error detection code value until the updated total error detection code value matches the expected error detection code value. Attached Figure Description

[0004] The following description includes a discussion of the figures, which are illustrations given in a manner that exemplifies implementations of embodiments of the present disclosure. The figures should be understood as examples and not as limitations. As used herein, references to one or more “embodiments” should be understood as describing specific features, structures, and / or characteristics included in at least one implementation. Therefore, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0005] Figure 1 An illustrative diagram of a system having a storage device and a memory according to some embodiments of the present disclosure is shown; Figure 2 An illustrative progression of the CRC checksum process for data divided into four parts according to some embodiments of this disclosure is shown; Figure 3 A flowchart illustrating illustrative steps for processing a CRC checksum by iteratively updating portions of a data codeword, according to some embodiments of the present disclosure, is shown. Figure 4 This illustration shows an embodiment of the present disclosure for processing by calculating and storing error detection code values ​​for each part of the data. Figure 3 A flowchart illustrating the steps of data in at least two portions of the data shown; Figure 5 The present disclosure illustrates some embodiments of processing by determining and storing error detection code states corresponding to appropriate portions of data. Figure 3 A flowchart illustrating the steps of data in at least two portions of the data shown; Figure 6 At least one of at least two portions of the data for correction according to some embodiments of the present disclosure is shown to generate Figure 3 A flowchart illustrating the steps of at least two corrected portions shown; Figure 7 Some embodiments of the present disclosure are shown for correction. Figure 3 A flowchart illustrating the steps of setting the error detection code state corresponding to each of the at least two corrected portions of the data shown to a correct error detection code state; Figure 8 Some embodiments of the present disclosure are shown for processing Figure 3 A flowchart illustrating the steps of the at least two corrected portions of the data shown; Figures 9-11A flowchart illustrating illustrative steps for determining the rewound error detection code state of a data codeword, according to some embodiments of this disclosure, is shown; and Figure 12 A flowchart illustrating illustrative steps for updating the error detection code status of an N-bit full codeword according to some embodiments of this disclosure is shown. Detailed Implementation

[0006] According to this disclosure, systems and methods are provided for iterative error detection code value (e.g., checksum) processing on storage devices (e.g., solid-state drive (SSD) devices). In some embodiments, the error detection code value is associated with a corresponding data codeword and processed as a whole data codeword. By processing the entire data codeword, the error detection code value associated with the data codeword is calculated from the beginning to the end of the data codeword. When an error is detected, the data codeword is corrected, and the entire corrected data codeword is reprocessed. The processing of the error detection code value does not terminate until the last data bit of the corrected data codeword has been processed, which may result in longer redundant processing time and unnecessary power consumption.

[0007] When the error detection code value is a linear error detection code value (e.g., a CRC checksum), the process of correcting and calculating the updated total error detection code value (such as the CRC checksum) can be completed sequentially. However, in some instances of corrupted data, there may only be one error at the beginning of the data codeword, and the processing circuitry will unnecessarily continue to perform CRC checksum calculations on the rest of the data codeword.

[0008] The process of correcting and calculating the updated total error detection code value can also be performed iteratively, where the data codeword is divided into at least two parts. The system's processing circuitry can process each part, storing the error detection code value for each corresponding part in memory. Therefore, when a corrupted or erroneous part of the data is corrected, the processing circuitry recalculates the error detection code value for the corrupted part and then determines the updated total error detection code value by using the error detection code values ​​for each corresponding uncorrupted part stored in memory.

[0009] Performing the process iteratively allows the processing circuitry to terminate the process at the end of an iteration or in the middle of a data codeword. This increases the likelihood of reducing the number of iterations required to perform the error detection checksum, thereby improving the throughput of the processing circuitry and reducing system latency and power consumption. Additionally, by storing the error detection code value of at least a portion of the data in memory, the methods and systems disclosed herein reduce redundant and unnecessary processing performed by the processing circuitry.

[0010] For the purposes of brevity and clarity, the features disclosed herein are presented in the context of an SSD having processing circuitry and memory. However, the principles of this disclosure can be applied to any other suitable context in which iterative error detection code checksum processing is used. The storage device may include processing circuitry and memory, and the processing circuitry and memory are communicatively coupled via a network bus or interface. In some embodiments, the processing circuitry receives data that may be driven from a source outside the storage device on the network bus or interface, or may be transferred from within the storage device (i.e., from memory). In particular, this disclosure provides systems and methods that utilize the temporal locality of previously computed data stored in memory. Computations of recently processed partial error detection code values ​​are considered temporally local and can be quickly accessed to aid in incomplete operations of the storage device. Additionally, when processing error detection code values, iterative processing of segmented data reduces overall latency and power consumption and increases throughput by enabling the storage device to terminate the process after processing several corrected data portions.

[0011] For example, an SSD device with processing circuitry receives data that is processed by the processing circuitry in at least two parts. The received data includes a corresponding error detection code and an expected error detection code value. The processing circuitry uses the expected error detection code value to verify the integrity of the received data and ensure that the received data is valid. Invalid data may cause additional errors, which may affect the performance or operation of the storage device. In some instances, the data may have become corrupted during transmission or storage, and therefore the error detection code is used to ensure that the data received by the processing circuitry is the same as when the data was initially stored in memory or transmitted from the source. In some cases of this example, a portion of the data and the corresponding portion of the error detection code value have become corrupted during data transmission. To detect this error, the processing circuitry calculates and compares the total error detection code value with the expected error detection code value. When the two values ​​do not match, the processing circuitry determines that at least one portion of the data is corrupted and must be corrected.

[0012] In some embodiments, each portion of the data corresponds to an error detection code state, which indicates whether the corresponding portion of the data has been corrupted. The error detection code state for each portion can be either a correct error detection code state or an incorrect error detection code state. In some implementations, each error detection code state is a single bit, which reduces the amount of memory required compared to storing the error detection code value for each portion of the data.

[0013] In some embodiments, the processor of the processing circuit may be a highly parallelized processor capable of rapidly processing high-bandwidth incoming data (e.g., by starting simultaneous processing of data portions before completing previous data portions).

[0014] In some embodiments, the systems and methods disclosed herein may refer to storage device systems (e.g., SSD storage systems) that include storage devices, such as solid-state drive devices, that are communicatively coupled to processing circuitry via a network bus or interface.

[0015] An SSD is a data storage device that uses integrated circuit components as memory to permanently store data. SSDs have no moving mechanical parts, a feature that distinguishes them from traditional electromechanical disks such as hard disk drives (HDDs) or floppy disks, which contain rotating disks and removable read / write heads. Compared to HDDs, SSDs are typically more resistant to physical shocks, operate quietly, have lower access times, and lower latency.

[0016] Many types of SSDs use NAND-based flash memory, which retains data without power and incorporates a type of non-volatile storage technology. The Quality of Service (QoS) of an SSD can be correlated with predictable low latency and consistent high input / output operations per second (IOPS) when serving read / write input / output (I / O) workloads. This means that latency or I / O command completion times need to be within specified ranges without unexpected outliers. Throughput or I / O rates may also need to be strictly regulated without causing sudden drops in performance levels.

[0017] By reference Figures 1-12 This will allow for a better understanding of the subject matter of this disclosure.

[0018] Figure 1 An illustrative diagram of a system 100 having a storage device 102 with processing circuitry 104 and memory 106 according to some embodiments of the present disclosure is shown. In some embodiments, the storage device 102 may be a solid-state storage device (e.g., a solid-state drive device). In some embodiments, the processing circuitry 104 may include a processor or any suitable processing unit. In some embodiments, the memory 106 may be non-volatile memory. It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, in addition to or instead of an SSD, the storage device 102 may include a hard disk drive (HDD) device.

[0019] In some embodiments, processing circuitry 104 is configured to receive data 108, which includes expected error detection code values ​​for data integrity verification. In some embodiments, data 108 is transmitted to processing circuitry 104 on a network bus or interface. In some embodiments, data 108 is transmitted from an external source (e.g., a host). In some embodiments, processing circuitry 104 receives data (e.g., data 108) from both internal and external sources of storage device 102. A temporary memory (e.g., a cache or queue) may also be present within processing circuitry 104, configured to store any incomplete data to be processed by processing circuitry 104.

[0020] Additionally, storage device 102 includes memory 106. In some embodiments, memory 106 includes any one or more non-volatile memories, such as phase-change memory (PCM), PCM and switching (PCMS), ferroelectric random access memory (FeRAM) or ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), memristors, spin-transfer torque magnetoresistive random access memory (STT-MRAM), and any other suitable non-volatile memory, or any combination thereof. In some embodiments, memory 106 includes any one or more volatile memories, such as flip-flops, register memory, static random access memory (SRAM), dynamic random access memory (DRAM), and any other suitable volatile memory, or any combination thereof. In some embodiments, processing circuitry 104 is communicatively coupled to memory 106 to store and access data, such as error detection code values ​​of portions of processed data. In some embodiments, a data bus interface is used to transmit data 108 or addresses associated with data 108. A data bus between memory 106 and processing circuitry 104 provides a network bus for reading or writing data (e.g., error detection code values) through memory 106. In some embodiments, the processor or processing unit of processing circuitry 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor, also referred to herein as processing circuitry 104, may include any suitable software, hardware, or both for controlling memory 106 and processing circuitry 104. In some embodiments, storage device 102 may further include a multi-core processor. Memory 106 may also include hardware elements for non-transitory storage of instructions, commands, or requests.

[0021] Processing circuit 104 is configured to iteratively process portions of data 108, some of which may contain errors and need to be corrected. Additionally, processing circuit 104 calculates and stores the error detection code value for each corresponding portion. Once the error is corrected, processing circuit 104 can calculate an updated error correction code value for the corrupted portion and reuse the stored error detection code value for each uncorrupted portion to determine an updated total error detection code value. This process, performed by processing circuit 104, utilizes the temporal locality of previously calculated error detection code values ​​for at least one portion of the data to reduce the overall delay and power consumption of the error detection code checksum process.

[0022] In some embodiments, the expected error detection code value corresponding to data 108 includes the expected linear error detection code corresponding to data 108. In some embodiments, the expected linear error detection code corresponding to data 108 includes the low-density parity-check (LDPC) code corresponding to data 108.

[0023] Storage devices (e.g., SSD devices) may include one or more non-volatile memory die packages, wherein each die includes a memory cell. In some embodiments, memory cells are organized into pages, and pages are organized into blocks. Each memory cell may store one or more bits of information.

[0024] It will be understood that although system 100 depicts an embodiment according to this disclosure in which storage device 102 is configured to have iterative error detection code checksum processing capability, any other suitable device may have iterative error detection code checksum processing capability in a similar manner.

[0025] For the purposes of clarity and brevity, and without limitation, this disclosure is provided in the context of iterative error-detecting code checksum processing, which provides the features and functionality disclosed herein. The iterative error-detecting code checksum process can be configured by any suitable software, hardware, or both to implement such features and functionality. The iterative error-detecting code checksum processing can be implemented at least in part in, for example, storage device 102 (e.g., as part of processing circuitry 104, or on which efficiency can be improved at high data structure depths). For example, for a solid-state storage device (i.e., storage device 100), the iterative error-detecting code checksum processing can be implemented in processing circuitry 104.

[0026] Figure 2 An illustrative progression of a CRC checksum process 200 for data divided into four parts (e.g., first part 204, second part 205, third part 207, and fourth part 208) according to some embodiments of this disclosure is shown. Although Figure 2The progress shown is for CRC checksum process 200, but the progress shown can be used for any form of error detection code (e.g., linear error detection code). Additionally, each stage of the progress includes a data codeword 202 or a portion of a data codeword, and a corresponding CRC value 203.

[0027] First, the entire data codeword 201 (e.g., data 108) is received by the processing circuit 104. In this implementation, the received data codeword 201 is 33 bytes long. In some embodiments, each byte of the data codeword (i.e., byte 1 to byte 33) may contain a value in the range of 0 to 255. However, this disclosure is not limited to a data codeword of 33 bytes in length. The data codeword includes two corrupted bytes of data, a first corrupted byte 206 and a second corrupted byte 209. Additionally, although not shown, the corresponding expected CRC checksum value is received along with the data codeword 201 and will be used to verify the validity of the data codeword 201.

[0028] Process 200 divides the entire data codeword 201 into four data portions via processing circuit 104, including a first data portion 204, a second data portion 205, a third data portion 207, and a fourth data portion 208. As currently segmented, a first corrupted byte 206 is located within the second data portion 205, and a second corrupted byte 209 is located within the fourth data portion 208. In some embodiments, each portion of the data corresponds to an error detection code state, which indicates whether the corresponding portion of the data is corrupted. The error detection code state of each portion can be either a correct error detection code state or an incorrect error detection code state. Process 200 iteratively processes each portion of the data (e.g., 204, 205, 207, 208) via processing circuit 104 and determines the CRC checksum value for each corresponding portion. Processing circuit 104 stores the CRC checksum value for each corresponding portion in memory 106. The processing circuit 104 then determines the total CRC checksum value as the sum of the CRC checksum values ​​of each corresponding portion of the data (e.g., 204, 205, 207, 208). The processing circuit 104 compares the total CRC checksum value with the expected CRC checksum value. The processing circuit 104 may determine that the total CRC checksum value does not match the expected CRC checksum value because at least one of the portions of the data contains corrupted bytes of data (e.g., second portion 205 and fourth portion 208).

[0029] As part of process 200, processing circuit 104 then corrects the first corrupted byte 206 and the second corrupted byte 209 of the data. In some embodiments, processing circuit 104 requests the retransmission of at least one portion of the data in order to correct said at least one portion of the data. Once the corrupted portions of the data (e.g., the second portion 205 and the fourth portion 208 of the data) are corrected, processing circuit 104 receives the corrected second portion 210 and the corrected fourth portion 212 of the data. The corrected second portion 210 of the data contains the corrected byte 211 of the data at the same byte address as the corrupted first byte 206 of the data in the second portion 205. Furthermore, the corrected fourth portion 212 of the data contains the corrected data byte 213 at the same byte address as the corrupted second byte 209 of the data in the fourth portion 208. In some embodiments, once the corresponding portions of the data are corrected, the error detection code state corresponding to the corresponding portions of the data is set to the correct error detection code state.

[0030] Once the damaged portion is corrected, processing circuit 104 determines an updated CRC checksum value for each corrected portion (e.g., the corrected second portion 210 and the corrected fourth portion 212 of the data). Processing circuit 104 determines an updated total CRC checksum value based on the updated CRC checksum values ​​of each of the corrected portions 210, 212 of the data, and the stored CRC checksum values ​​of each of the first portion 204 and the third portion 207 of the data. Process 200 completes for data codeword 201 when processing circuit 104 determines that the updated total CRC checksum value matches the expected CRC checksum value.

[0031] Figure 3 A flowchart 300 illustrates illustrative steps for processing a CRC checksum by partially iteratively updating portions of a data codeword, according to some embodiments of the present disclosure. In some embodiments, the referenced storage device, processing circuitry, and memory may be implemented as storage device 102, processing circuitry 104, and memory 106, respectively. In some embodiments, process 300 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0032] At step 302, processing circuitry 104 receives data (e.g., data 108) and a corresponding expected error detection code value. In some embodiments, the data is received by processing circuitry 104 via a network bus or interface. The expected error detection code value is used by processing circuitry 104 when verifying the integrity of the data. Processing circuitry 104 is capable of checking whether the state of the received data is the same as its state when it was transmitted or stored in memory. The data (e.g., data 108) includes the expected error detection code value. For example, the expected error detection code value may be wrapped in a header field of the received data. In some embodiments, storage device 102 receives more than one piece of data. At least one of the received data may be stored in memory, such as a cache or queue, or any form of volatile memory. In some embodiments, processing circuitry 104 may include a multi-core processor capable of performing iterative error detection code checksums on more than one codeword.

[0033] At step 304, processing circuitry 104 processes data in at least two portions. In some embodiments where the data is 33 bytes long, processing circuitry 104 may process the data into up to 264 portions, such that the minimum size of a portion is a single bit. In some embodiments, the maximum number of portions of data may be defined as the codeword size or the total number of bits of data divided by the minimum size of a portion (e.g., a single bit). To process each portion, processing circuitry 104 is configured to calculate an error detection code value for the corresponding portion and store the calculated error detection code value for the corresponding portion in memory 106. Figure 2 As seen in process 200, the data can be processed into four parts; however, it can be further subdivided into smaller parts. The added granularity from subdividing into smaller parts increases the number of partial iterations required to process the entire data codeword (e.g., data 108). However, smaller data parts result in less latency than larger parts, and therefore the processor can operate at a higher frequency. In some embodiments, each part of the data has a similar equivalent length, which can be measured in bytes or bits. In some embodiments, when processing at least two parts comprising a first part of a first length and a second part of a second length, processing circuitry 104 can determine that the second length is greater than the first length. Processing circuitry 104 then pads the first part with zeros so that the first part has a similar equivalent length to the second part. At step 306, once each part has been processed, processing circuitry 104 has processed the entire data codeword and can calculate the total error detection code value.

[0034] At step 306, processing circuitry 104 calculates a total error detection code value based on the corresponding error detection code values ​​of the at least two portions of the data (e.g., data 108). In some embodiments, the error detection code transmitted with the data (e.g., data 108) is a linear error detection code, such as a CRC code, which allows the error detection code values ​​of each corresponding portion of the data to be summed to calculate the total error detection code value. In some embodiments, the total error detection code value is stored in memory 106. Processing circuitry 104 uses the total error detection code value when verifying data integrity by comparing the total error detection code with an expected error detection code value, as shown at step 308.

[0035] At step 308, the processing circuitry determines whether the total error detection code value matches the expected error detection code value included with the transmitted data (e.g., data 108). When the total error detection code value matches the expected error detection code value, the processing circuitry 104 can reliably verify that the data was not corrupted during transmission over the network bus or interface before being received by the processing circuitry 104. In such an instance, the error detection code checksum process is completed for that data codeword. In contrast, when the total error detection code value does not match the expected error detection code value, the processing circuitry 104 determines that at least one corrupted or erroneous portion of the data exists. Therefore, at step 310, the processing circuitry 104 then corrects at least one portion of the data to have a valid data codeword for further processing.

[0036] At step 310, the processing circuitry is configured to correct at least one of the at least two portions of the data (e.g., data 108) to generate at least two corrected portions. In some embodiments, the processing circuitry 104 is configured to request a portion of the data to be retransmitted. This enables the processing circuitry 104 to request a portion of the data to replace the corrupted portion with the corrected portion of the data. In some embodiments, the processing circuitry 104 is configured to request the retransmission of the entire data codeword. Additionally, this disclosure is not limited to data correction via data retransmission. In some embodiments, the LDPC decoder may be used to determine that a particular data bit or subset of the data is incorrect, and therefore the particular data bit or subset of the data should be flipped. At step 312, the processing circuitry 104 corrects at least one portion of the data and then processes the corrected portion of the data.

[0037] At step 312, processing circuitry 104 processes at least two corrected portions. Processing circuitry 104 calculates an updated error detection code value for a corresponding one of the at least two corrected portions. In some embodiments, processing circuitry 104 is configured to then calculate an updated total error detection code value based on each of the updated error detection code values ​​for the corresponding portions of the at least two corrected portions and each error detection code value stored in memory 106. Then, at step 308, processing circuitry 104 determines whether the updated total error detection code value matches the expected total error detection code value. If the updated total error detection code value matches the expected total error detection code value, the data (e.g., data 108) has been corrected and verified as valid data. However, in some embodiments, at least one corrupted portion of the data may still exist, causing the updated total error detection code value to not match the expected total error detection code value. In some embodiments, the retransmitted data seen at step 310 may have been corrupted during retransmission. The process will continue to proceed sequentially through steps 308, 310, and 312 until the updated total error detection code value matches the expected total error detection code value.

[0038] Figure 4 A flowchart of a process 400 according to some embodiments of the present disclosure is shown, including processing by calculating and storing error detection code values ​​for each part of the data. Figure 3 The illustrated steps of the data in at least two portions shown. For example... Figure 3 As seen in the diagram, process 400 may also be referred to as step 304. In some embodiments, the referenced storage device, processing circuitry, and memory may be implemented as storage device 102, processing circuitry 104, and memory 106, respectively. In some embodiments, process 400 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0039] At step 402, processing circuit 104 is configured to calculate the error detection code value for the corresponding portion. In some embodiments, processing circuit 104 may calculate the error detection code value for the corresponding portion of the data by using a hash function (i.e., using polynomial division), fingerprint, matrix multiplication, linear feedback shift register, or randomization function. At step 404, once processing circuit 104 has calculated the error detection code value for the corresponding portion of the data, processing circuit 104 stores the calculated error detection code value for the corresponding portion in memory 106.

[0040] At step 404, processing circuit 104 stores the error detection code value for each corresponding portion into memory 106. Storing the error detection code value for each portion of data 108 into memory allows processing circuit 104 to utilize the previously calculated error detection code value when a portion of data 108 is determined to be corrupted and needs to be corrected. By accessing the previously calculated error detection code value for at least one portion of the data, the overall delay and power consumption of the error detection code checksum process can be reduced.

[0041] Figure 5 A flowchart of process 500 according to some embodiments of the present disclosure is shown, including processing by determining and storing error detection code states corresponding to relevant portions of data. Figure 3 The illustrated steps of the data in at least two portions shown. For example... Figure 3 As seen in the diagram, process 500 can also be referred to as step 304. In some embodiments, the referenced storage device, processing circuitry, and memory can be implemented as storage device 102, processing circuitry 104, and memory 106, respectively. In some embodiments, process 500 can be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0042] At step 502, processing circuitry 104 is configured to determine the error detection code state corresponding to a specific portion of the data. The error detection code state can be either a correct error detection code state or an incorrect error detection code state. In some cases, an incorrect error detection code state is determined to correspond to that portion of the data when a portion of the data is corrupted and needs to be corrected. When the error detection code state of the corresponding portion of the data is an incorrect error detection code state, the corresponding portion of the data is corrected before the data codeword is traversed to other portions of the data corresponding to the incorrect error detection code state. In some embodiments, the error detection code state can be implemented as a bit flip, using a single bit to indicate the error detection code state of the corresponding portion of the data. In some embodiments, the LDPC decoder can determine that a specific data bit is incorrect and should be flipped. Once processing circuitry 104 has determined the error detection code state corresponding to the corresponding portion of the data, at step 504, processing circuitry 104 stores the error detection code state corresponding to the corresponding portion in memory 106.

[0043] At step 504, processing circuit 104 stores the error detection code state corresponding to the respective portion in memory 106. Storing the error detection code state of a portion of data 108 in memory enables processing circuit 104 to determine each portion of the data corresponding to a data codeword with an incorrect error detection code state, and to correct each of these determined portions of the data faster than calculating a total error detection code value based on the corrected portions of the data stored in memory 106 and any error detection code values. By using a single bit error detection code state for each portion of the data, the amount of memory 106 required is reduced compared to storing error detection code values.

[0044] Figure 6 A flowchart of process 600 according to some embodiments of the present disclosure is shown, including at least one of at least two portions for correcting data to generate Figure 3 The illustrative steps of at least two corrected portions are shown. (As...) Figure 3 As seen in the diagram, process 600 may also be referred to as step 310. In some embodiments, the referenced storage device, processing circuitry, and memory may be implemented as storage device 102, processing circuitry 104, and memory 106, respectively. In some embodiments, process 600 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0045] At step 602, processing circuitry 104 requests the retransmission of a portion of data 108. In some embodiments, processing circuitry 104 receives data 108 from both internal and external sources of storage device 102. Processing circuitry 104 is configured to send a request to the source of data 108 for a portion of the data 108 to be retransmitted. In some embodiments, processing circuitry is configured to send a request for the entire data codeword to be retransmitted. After processing circuitry 104 sends a request for at least a portion of the data to be retransmitted from the source, at step 604, processing circuitry 104 receives the requested data.

[0046] At step 604, processing circuitry 104 is configured to receive a retransmission portion of data 108. In some embodiments, the retransmission portion of the data is received by processing circuitry 104 from a network bus or interface. In some embodiments, processing circuitry receives the entire data codeword that has been requested to be retransmitted. In some embodiments, the received retransmission portion of the data is stored in memory, such as a cache or queue, or any form of volatile memory, before further processing.

[0047] Figure 7 A flowchart of process 700 according to some embodiments of the present disclosure is shown, including methods for correction. Figure 3The illustrated steps involve setting the error detection code state corresponding to each of the at least two corrected portions of the data to a correct error detection code state. For example... Figure 3 As seen in the diagram, process 700 can also be referred to as step 310. In some embodiments, the referenced storage device, processing circuitry, and memory can be implemented as storage device 102, processing circuitry 104, and memory 106, respectively. In some embodiments, process 700 can be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0048] At step 702, processing circuit 104 selects at least one portion of the at least two portions corresponding to an incorrect error detection code state. In some embodiments, processing circuit 106 uses a matrix to traverse the data codeword by either forward traversal or backward / reverse traversal. In some implementations, an update matrix may be used to traverse the portions of data corresponding to the incorrect error detection code state and to be corrected. In some embodiments, the update matrix may be used to step through each portion of the data, or the update matrix may be updated by matrix multiplication to traverse specific portions of the data. At step 704, after processing circuit 104 selects at least one portion of the at least two portions corresponding to the incorrect error detection code state, processing circuit 104 corrects the selected at least one portion corresponding to the incorrect error detection code state to generate at least two corrected portions.

[0049] At step 704, processing circuitry 104 is configured to correct at least one selected portion corresponding to an incorrect error detection code state to generate at least two corrected portions. In some embodiments, processing circuitry 104 may correct a portion of data corresponding to an incorrect error detection code state using the same process as shown in process 700. After processing circuitry 104 corrects at least one selected portion corresponding to an incorrect error detection code state to generate at least two corrected portions, at step 706, processing circuitry 104 sets the error detection code state corresponding to each of the at least two corrected portions to a correct error detection code state.

[0050] At step 706, processing circuitry 104 is configured to set the error detection code state corresponding to each of the at least two corrected portions to a correct error detection code state. In some embodiments, processing circuitry 104 continues to traverse the data codeword, correcting other portions of the data corresponding to incorrect error detection code states, until no portions of the data codeword correspond to incorrect error detection code states exist. In some implementations, an entire codeword error detection code state may exist, indicating whether any portion of the data within the data codeword corresponds to an incorrect error detection code state.

[0051] Figure 8A flowchart of a process 800 according to some embodiments of the present disclosure is shown, including processes for... Figure 3 Illustrative steps for at least two corrected portions of the data shown. For example... Figure 3 As seen in the diagram, process 800 may also be referred to as step 312. In some embodiments, the referenced storage device, processing circuitry, and memory may be implemented as storage device 102, processing circuitry 104, and memory 106, respectively. In some embodiments, process 800 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0052] At step 802, processing circuit 104 calculates updated error detection code values ​​for corresponding portions of the two corrected portions of data 108. In some embodiments, processing circuit 104 calculates updated error detection code values ​​for the corresponding corrected portions of data 108 in a manner similar to how error detection code values ​​are calculated (e.g., ...). Figure 4 (As seen in step 402). In some embodiments, processing circuitry 104 rewrites the error detection code value of the corrected portion of data 108 at address 106 using the updated error detection code value of the corrected portion of the data. At step 804, processing circuitry 104 is then configured to calculate an updated total error detection code value based on at least each of the updated error detection code values.

[0053] At step 804, processing circuitry 104 is configured to calculate an updated total error detection code value based on the updated error detection code values ​​of corresponding portions of the at least two corrected portions and the error detection code values ​​stored in memory 106. In some embodiments, the error detection code values ​​are linear error detection code values, such as CRC checksums. In some implementations using linear error detection code values, processing circuitry 104 calculates the updated total error detection code value by summing the updated error detection code values ​​of the at least one corrected portion and the stored error detection code values ​​of each undamaged portion. In other implementations using linear error detection code values, processing circuitry 104 calculates the updated total error detection code value by summing the total error detection code values ​​stored before the most recent partial correction, and by calculating each difference between the updated error detection code value and the stored error detection code values ​​of the corresponding damaged portions of the data.

[0054] Figures 9-11A flowchart (e.g., 900, 1000, and 1100) is shown, illustrating the process (e.g., 912, 1014, and 1112) including illustrative steps for determining the backward error detection code states (e.g., 912, 1014, and 1112) of a data codeword according to some embodiments of this disclosure. The use of error detection code states for each portion of data enables processing circuitry 104 to determine each portion of data corresponding to an incorrect error detection code state, correct each of these determined data portions, and calculate a total error detection code value based on the corrected portions of the data and any error detection code values ​​stored in memory 106. By storing the error detection code states of individual bits for access, rather than the error detection code values ​​for each portion of the data, the required total memory can be reduced.

[0055] The flowchart of process 900 includes a fixed NxN matrix 902, which can be used to determine an updated NxN matrix 906. In some implementations, N is the number of bits in the error detection code state (e.g., 908 and 912). The fixed NxN matrix 902 can be stored in memory 106 and used to iterate backward one step, where one step refers to a fixed distance between two bit positions in the data codeword. In some implementations, to step over multiple parts of the data, the fixed NxN matrix 902 can be multiplied by 904 to generate an updated NxN matrix 906. In some implementations, the updated NxN matrix 906 can be multiplied by 904 to further update the updated NxN matrix 906. Process 900 illustrates generating a backward NxN error detection code state 912 by multiplying the updated NxN matrix 906 and the N-bit error detection code state 908 by 910.

[0056] The flowchart of process 1000 illustrates the simplified logic for generating the reversed N-bit error detection code state 1014 using fewer logic gates required. Process 1000 shows the first row 1006 of the updated NxN matrix 1008, where the first row 1006 is used to determine any subsequent rows of the updated NxN matrix 1008. The first row 1006 is multiplied by the fixed NxN matrix 1002 by 1004 to generate the second row, which is used to update the NxN matrix 1008 and generate the third row. Process 1000 then shows the generation of the reversed N-bit error detection code state 1014 by multiplying the updated NxN matrix 1008 and the N-bit error detection code state 1010 by 1010.

[0057] The flowchart of process 1100 illustrates the unordered reverse logic, including a lookup table 1102, which can be used to determine the corresponding row (i.e., the first row 1104) of the updated NxN matrix 1106. In some embodiments, this logic may include a multiplier to reduce the number of rows stored in lookup table 1102. For example, the multiplier allows each odd-numbered row to be stored in lookup table 1102, and any subsequent rows can be determined by matrix multiplication of the fixed NxN matrix. Process 1100 then illustrates generating the reversed N-bit error detection state 1112 by multiplying the updated NxN matrix 1008 and the N-bit error detection state 1108 by 1110.

[0058] Figure 12 A flowchart of process 1200 according to some embodiments of the present disclosure is shown, including illustrative steps for updating the N-bit full codeword error detection state 1208. Process 1200 shows updating the N-bit full codeword error detection state by adding 1204 of the reversed N-bit error detection state 1202 (such as 912, 1014, and 1112) to the previous N-bit full codeword error detection state. After updating the N-bit full codeword error detection state 1208 with the reversed N-bit error detection state 1202, processing circuitry 104 can determine whether there is any additional portion of data corresponding to an incorrect error detection state. If any bit in the N-bit full codeword error detection state 1208 indicates an incorrect error detection state, processing circuitry 104 proceeds to further data portion correction.

[0059] The terms “an embodiment,” “an embodiment,” “(multiple) embodiments,” “the embodiment,” “the embodiment,” “one or more embodiments,” “some embodiments,” and “an embodiment” mean “one or more (but not all) embodiments”, unless otherwise expressly specified.

[0060] The terms “including,” “comprising,” “having,” and their variations mean “including, but not limited to,” unless otherwise expressly specified.

[0061] The enumerated list of items does not imply that any or all items are mutually exclusive unless otherwise explicitly stated.

[0062] The terms “a,” “an,” and “the” mean “one or more” unless otherwise explicitly specified.

[0063] Devices communicating with each other do not need to communicate continuously unless otherwise expressly specified. Additionally, devices communicating with each other may communicate directly or indirectly through one or more intermediaries.

[0064] The description of embodiments having several components that communicate with each other does not imply a requirement for all such components. Instead, a wide variety of optional components are described to illustrate a wide range of possible embodiments. Furthermore, although process steps, method steps, or algorithms may be described in sequential order, such processes, methods, and algorithms may be configured to operate in an alternating order. In other words, any order or sequence of steps that can be described does not necessarily indicate a requirement to perform those steps in that order. The steps of the process described herein can be performed in any actual order. Furthermore, some steps may be performed simultaneously.

[0065] When a single device or article of manufacture is described herein, it will be readily apparent that more than one device / article of manufacture (whether or not they cooperate) may be used in place of the single device / article. Similarly, when more than one device or article of manufacture (whether or not they cooperate) is described herein, it will be readily apparent that a single device / article of manufacture may be used in place of the more than one device or article of manufacture, or that a different number of devices / articles may be used in place of the number of devices or programs shown. The functionality and / or features of a device may alternatively be embodied by one or more other devices that are not explicitly described as having such functionality / features. Therefore, other embodiments do not need to include the device itself.

[0066] The figures illustrate specific events occurring in a particular order, as shown by at least specific operations. In alternative embodiments, specific operations may be performed, modified, or removed in a different order. Furthermore, steps may be added to the above logic, still conforming to the described embodiments. Further, the operations described herein may occur sequentially, or specific operations may be processed in parallel. Even further, operations may be performed by a single processing unit or distributed processing units.

[0067] The foregoing description of various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise forms disclosed. In light of the above teachings, many modifications and variations are possible.

Claims

1. A method comprising: (a) receiving data and an expected error detection code value corresponding to the data; (b) processing the data in at least two portions, wherein the processing of each of the at least two portions comprises: calculating an error detection code value for the respective portion; and storing the error detection code value for the respective portion in a memory; (c) calculating a total error detection code value based on the respective error detection code values of the at least two portions; (d) when the total error detection code value or an updated total error detection code value does not match the expected error detection code value: correcting at least one of the at least two portions to generate at least two corrected portions; and processing the at least two corrected portions, wherein processing the at least two corrected portions comprises: calculating an updated error detection code value for a respective one of the at least two corrected portions; and calculating an updated total error detection code value based on the updated error detection code value and the stored error detection code value for the respective portion of the at least two corrected portions; and (e) repeating (d) until the updated total error detection code value matches the expected error detection code value.

2. The method of claim 1, wherein correcting at least one of the at least two portions to generate at least two corrected portions comprises: requesting a retransmission of a portion of the data; and receiving the retransmitted portion of the data.

3. The method of claim 1, wherein receiving the data and the expected error detection code value corresponding to the data comprises receiving an expected linear error detection code value corresponding to the data.

4. The method of claim 3, wherein receiving the expected linear error detection code value corresponding to the data comprises receiving a low density parity check codeword corresponding to the data.

5. The method of claim 1, wherein the at least two portions have similar equivalent lengths.

6. The method of claim 1, wherein processing the data in the at least two portions further comprises: determining that a first portion of the at least two portions has a first length and a second portion of the at least two portions has a second length, the second length being greater than the first length; and padding the first portion of the at least two portions with zeros such that the first portion has a length similar to an equivalent length of the second length.

7. The method of claim 1, wherein the processing of each of the at least two portions further comprises: determining an error detection code status corresponding to the respective portion, wherein the error detection code status is one of (a) a correct error detection code status and (b) an incorrect error detection code status; and storing the error detection code status corresponding to the respective portion in the memory.

8. The method of claim 7, wherein correcting at least one of the at least two portions to generate the at least two corrected portions comprises: selecting at least one of the at least two portions corresponding to an incorrect error detection code status; correcting the selected at least one of the at least two portions corresponding to the incorrect error detection code status to generate the at least two corrected portions; and setting the error detection code status corresponding to each of the at least two corrected portions to a correct error detection code status. ​ ​ ​ ​ 9. The method of claim 1, wherein storing the error detection code value of the respective portion in the memory comprises overwriting a previously stored error detection code value for the portion.

10. The method of claim 1, wherein computing the updated overall error detection code value based on the updated error detection code value and the stored error detection code value of the respective portion of the at least two corrected portions comprises: determining a difference between the updated error detection code value and the stored error detection code value of the updated portion; and computing the updated overall error detection code value based on the difference between the updated error detection code value and the stored error detection code value of the updated portion and the stored error detection code values of the at least two portions.

11. A system comprising: a memory; and processing circuitry configured to: (a) receive data and an expected error detection code value corresponding to the data; (b) process the data in at least two portions, wherein the processing of each of the at least two portions comprises: computing an error detection code value of the respective portion; and storing the error detection code value of the respective portion in the memory, (c) compute an overall error detection code value based on the respective error detection code values of the at least two portions; (d) when the overall error detection code value or an updated overall error detection code value does not match the expected error detection code value: correct at least one of the at least two portions to generate at least two corrected portions; and process the at least two corrected portions, wherein processing the at least two corrected portions comprises: computing an updated error detection code value for a respective one of the at least two corrected portions; and computing an updated overall error detection code value based on the updated error detection code value and the stored error detection code value of the respective portion of the at least two corrected portions; and (e) repeat (d) until the updated overall error detection code value matches the expected error detection code value.

12. The system of claim 11, wherein to correct at least one of the at least two portions to generate at least two corrected portions, the processing circuitry is to: request a retransmission of a portion of the data; and receive the retransmitted portion of the data.

13. The system of claim 11, wherein the expected error detection code value corresponding to the data comprises an expected linear error detection code value corresponding to the data.

14. The system of claim 13, wherein the expected linear error detection code value corresponding to the data comprises a low density parity check codeword corresponding to the data.

15. The system of claim 11, wherein the at least two portions have similar equivalent lengths.

16. The system of claim 11, wherein to process the data in at least two portions, the processing circuitry is further to: determine that a first portion of the at least two portions has a first length and a second portion of the at least two portions has a second length, the second length being greater than the first length; and pad the first portion of the at least two portions with zeros such that the first portion has a length similar to an equivalent length of the second length.

17. The system of claim 11, wherein to process each of the at least two portions, the processing circuitry is further to: ​ determining an error detection code status for the respective portion, wherein the error detection code status is one of (a) a correct error detection code status and (b) an incorrect error detection code status; and storing the error detection code status for the respective portion in memory.

18. The system of claim 17, wherein to correct at least one of the at least two portions to generate the at least two corrected portions, the processing circuit is to: select at least one of the at least two portions that corresponds to an incorrect error detection code status; correct the selected at least one of the at least two portions that corresponds to an incorrect error detection code status to generate at least two corrected portions; and set the error detection code status corresponding to each of the at least two corrected portions to a correct error detection code status.

19. The system of claim 11, wherein to store the error detection code value for the respective portion in memory, the processing circuit is to overwrite a previously stored error detection code value for the portion.

20. The system of claim 11, wherein to calculate an updated overall error detection code value based on the updated error detection code value and the stored error detection code value for the respective portion of the at least two corrected portions, the processing circuit is to: determine a difference between the updated error detection code value and the stored error detection code value for the updated portion; and calculate the updated overall error detection code value based on the difference between the updated error detection code value and the stored error detection code value for the updated portion and the stored error detection code values for the at least two portions.

21. A non-transitory computer-readable medium having encoded thereon non-transitory computer-readable instructions that, when executed by a processing circuit, cause the processing circuit to: (a) receive data and an expected error detection code value corresponding to the data; (b) process the data in at least two portions, wherein the processing of each of the at least two portions comprises: calculating an error detection code value for the respective portion; and storing the error detection code value for the respective portion in memory; (c) calculate an overall error detection code value based on the respective error detection code values for the at least two portions; (d) when the overall error detection code value or an updated overall error detection code value does not match the expected error detection code value: correct at least one of the at least two portions to generate at least two corrected portions; process the at least two corrected portions, wherein processing the at least two corrected portions comprises: calculating an updated error detection code value for a respective one of the at least two corrected portions; and calculating an updated overall error detection code value based on the updated error detection code value and the stored error detection code value for the respective portion of the at least two corrected portions; and (e) repeat (d) until the updated overall error detection code value matches the expected error detection code value.

22. The non-transitory computer-readable medium of claim 21, wherein to correct at least one of the at least two portions to generate at least two corrected portions, the processing circuit is to: request a retransmission of a portion of the data; and receive the retransmitted portion of the data. ​ ​ 23. The non-transitory computer-readable medium of claim 21, wherein the expected error detection code value corresponding to the data comprises an expected linear error detection code value corresponding to the data.

24. The non-transitory computer-readable medium of claim 23, wherein the expected linear error detection code value corresponding to the data comprises a low density parity check codeword corresponding to the data.

25. The non-transitory computer-readable medium of claim 21, wherein the at least two portions have similar equivalent lengths.

26. The non-transitory computer-readable medium of claim 21, wherein to process the data in the at least two portions, the processing circuitry is further to: determine that a first portion of the at least two portions has a first length and a second portion of the at least two portions has a second length, the second length being greater than the first length; and pad the first portion of the at least two portions with zeros such that the first portion has a length similar to an equivalent of the second length.

27. The non-transitory computer-readable medium of claim 21, wherein to process each of the at least two portions, the processing circuitry is further to: determine an error detection code state corresponding to the respective portion, wherein the error detection code state is one of (a) a correct error detection code state and (b) an incorrect error detection code state; and store the error detection code state of the respective portion in the memory.

28. The non-transitory computer-readable medium of claim 27, wherein to correct at least one of the at least two portions to generate the at least two corrected portions, the processing circuitry is to: select at least one of the at least two portions that corresponds to the incorrect error detection code state; correct the selected at least one of the at least two portions that corresponds to the incorrect error detection code state to generate the at least two corrected portions; and set the error detection code state corresponding to each of the at least two corrected portions to the correct error detection code state.

29. The non-transitory computer-readable medium of claim 21, wherein storing the error detection code value of the respective portion in the memory comprises: overwriting a previously stored error detection code value for the portion.

30. The non-transitory computer-readable medium of claim 21, wherein to compute the updated overall error detection code value based on the updated error detection code value and the stored error detection code value of the respective portion of the at least two corrected portions, the processing circuitry is to: determine a difference between the updated error detection code value and the stored error detection code value of the updated portion; and compute the updated overall error detection code value based on the difference between the updated error detection code value and the stored error detection code value of the updated portion and the stored error detection code values of the at least two portions.

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