Optimization for digital processing systems

Abstract

The invention relates to optimization for a digital processing system. Systems and methods are provided for reducing quantization errors, including a method of optimizing a routine for a hardware-based processing system having a fixed length two complement binary representation, the method comprising: receiving a sequence of instructions arranged to execute the routine, where the sequence of instructions comprises a set of arithmetic operations, wherein the output of the arithmetic operation exceeds the precision of the hardware-based processing system; identifying one or more pairs of instruction subsets in the instruction sequence, each pair of subsets having a corresponding equivalent truncation error; an optimized routine is generated by modifying one of the subsets of each pair to reverse one or more input symbols of the subset and modifying the instruction sequence to compensate for the inversion.

Description

TECHNICAL FIELD

[0001] The present invention relates to the optimization of computer-implemented computations for digital processing systems having fixed-precision. BACKGROUND

[0002] It is well known that modern digital processing systems almost universally use binary representations having a fixed number of binary digits to process numbers. This fixed number of binary digits is typically a multiple of the underlying word size of the digital processing system, and thus represents an architectural constraint of the binary processing system itself. Common examples of such fixed-length binary number types include "short integers" that are 16 bits long and "long integers" that are typically 32 bits long. Decimal numbers are typically represented using fixed-point or floating-point binary representations, again having a fixed number of binary digits. Examples include 32-bit long single-precision floating-point format numbers and 64-bit long double-precision floating-point format numbers.

[0003] Thus, in order to process decimal fractions of arbitrary precision, it is necessary to use quantization to represent such decimal fractions as fixed-length binary numbers. Quantization is the process of reducing the precision of data, similar to reducing the number of decimal digits (often referred to as the least significant bits) in a decimal number (i.e., 2.431 can be quantized to 2.43 or 2.4, etc.), and this typically occurs along the chain of computations of an algorithm, as many operation results exceed the allowed number of bits, necessitating the quantization of their values to fit the machine data size. Quantization can be performed by simply removing the least significant bits (truncation) or by rounding the number before removing the bits (rounding). Both approaches have drawbacks. While truncation is inexpensive in terms of hardware and processing overhead, it produces cumulative errors. This can lead to large errors in the overall output of a complex computation, as individual truncation errors accumulate across the multiple arithmetic operations that make up the computation.

[0004] A rounding scheme can be chosen that results in an average error of zero or close to zero. The round-to-nearest scheme is a common example of a rounding scheme whose average error is zero or close to zero. This scheme tends to minimize the errors resulting from quantization in the overall output of a complex computation, as individual rounding errors tend to cancel out across the multiple arithmetic operations that make up the computation. However, this rounding scheme requires the implementation of additional arithmetic operations. This scheme incurs computational overhead, and in computations implemented in hardware, also incurs additional hardware cost due to the requirement of additional hardware elements, such as additional adders. SUMMARY

[0005] The present disclosure aims to address the quantization issues discussed above. To this end, a new truncation operation is described, which has an average error of opposite sign (or polarity) compared to the average error obtained by existing truncation techniques. An optimization scheme is proposed to combine this new double sign-reversing truncation operation with existing truncation operations to cancel out the truncation error in arbitrary computations. In this way, a software or hardware routine implementing arbitrary computations can be optimized for a digital processing machine with a certain fixed bit-length requirement.

[0006] The methods and systems described herein thus enable improving the performance of embedded code and reducing the energy footprint of computing application specific integrated circuits. They also enable improving the computational efficiency of software routines.

[0007] In a first aspect, a method of optimizing a routine (or computation or algorithm) for a hardware-based processing system is provided. The routine can be a software routine, or can be a hardware description language routine. The hardware-based processing system has a two’s complement binary representation. Operations implemented on the hardware-based processing system are typically affected by a respective fixed binary length of the operand values (or variables). The fixed length can vary from operation to operation. The fixed length can vary from variable type to variable type. Alternatively, the fixed length can be fixed for all operations (or all variables of a particular type). For example, the hardware-based processing system can have (or be specified to have) a fixed length two’s complement binary representation.

[0008] The method comprises: receiving an instruction sequence arranged to execute the routine, wherein the instruction sequence comprises a set of arithmetic operations, wherein the output of an arithmetic operation exceeds the precision of the hardware-based processing system; identifying one or more pairs of subsets of instructions in the instruction sequence, the subsets in each pair having a respective comparable truncation error; generating an optimized routine by modifying one of the subsets in each pair to reverse the sign of one or more inputs of said subset and modifying the instruction sequence to compensate for said reversal. The modification can be considered to cancel out the truncation error between each pair of subsequences.

[0009] The step of modifying the instruction sequence can comprise modifying the instruction sequence to reverse the sign of the output of each subsequence having a reversed sign input.

[0010] The instruction sequence can comprise at least one instruction to sum the outputs of a respective pair of subsets, and the modification of the instruction sequence comprises replacing each instruction to sum the outputs with an instruction to compute the difference of the outputs of the respective pair of subsets.

[0011] In some embodiments, modifying one of the subset of the at least one pair to reverse the sign of the input of the subsequence includes reversing the sign of a multiplication constant used in the subset.

[0012] In some embodiments, the generating includes removing a rounding operation (such as a nearest rounding operation, or a half-to-up rounding operation or an even-to-up rounding operation, etc.) from at least one of the pairs of subsets.

[0013] The routine can include an N-dimensional scalar product of two vectors and the instruction sequence includes a sum of N vector coefficient multiplications (such as a software routine implementing a matrix multiplication). Still further, each subsequence can include a respective vector coefficient multiplication, where the modified instruction sequence takes a difference of a sum of the subsequence with reversed sign input and a sum of the other subsequence.

[0014] The routine can implement a linear time-invariant (LTI) algorithm. Still further, identifying one or more pairs of subsets can include calculating a respective average error in an output of the routine due to truncation of each arithmetic operation of the set of arithmetic operations. Here, identifying one or more pairs of subsets can include minimizing a sum of the respective average errors, or implementing by minimizing the sum of the respective average errors.

[0015] The routine can implement a filter bank including two or more channels (such as an analysis-synthesis filter bank), where each instruction subset corresponds to a respective channel.

[0016] In a second aspect, a method of calculating an N-dimensional scalar product of two vectors in a hardware-based processing system having fixed-length two's complement binary representation is provided. The method includes calculating a sum of N / 2 vector coefficient vector multiplications in the scalar product, where the calculating includes truncating intermediate results that exceed a precision of the hardware-based processing system; calculating a sum of the other N / 2 vector coefficient vector multiplications in the scalar product, where the calculating includes reversing a sign of each vector coefficient of one of the two vectors and truncating intermediate results that exceed the precision of the hardware-based processing system; and calculating a difference of the sum of the N / 2 vector coefficient vector multiplications and the sum of the other N / 2 vector coefficient vector multiplications in the scalar product to thereby obtain the scalar product.

[0017] In a third aspect, a method of implementing a filter bank having a plurality of channels in a hardware-based processing system having fixed-length two's complement binary representation is provided. The method includes receiving an input signal; applying filters of a first subset of M channels of the plurality of channels to the input signal; applying filters of a second subset of M channels of the plurality of channels to a reversed sign input signal; and generating an output of the filter bank by taking a difference of an output of the first subset of M channels and an output of the second subset of M channels.

[0018] According to a fourth aspect of the application, there is provided a system adapted to implement the system of the first, second or third aspect referred to above, or any embodiment thereof.

[0019] To this end, there is provided a system for optimising a routine (or computation or algorithm) for a hardware-based processing system, the system comprising a memory and one or more processors configured to implement the steps of: receiving a sequence of instructions arranged to perform the routine, wherein the sequence of instructions comprises a set of arithmetic operations, wherein an output of an arithmetic operation exceeds a precision of the hardware-based processing system; identifying one or more pairs of subsets of instructions in the sequence of instructions, the subsets in each pair having a respective comparable truncation error; generating an optimised routine by modifying one of the subsets of each pair to invert a sign of one or more inputs of said subset and modifying the sequence of instructions to compensate for said inversion. The modification can be considered to cancel out the truncation error between each pair of subsequences.

[0020] According to a fifth aspect of the application, there is provided an application specific integrated circuit arranged to implement the method according to the second or third aspect, or any embodiment thereof.

[0021] According to a sixth aspect of the application, there is provided a computer program which, when executed by one or more processors, causes the one or more processors to implement the first, second or third aspect referred to above, or any embodiment thereof. The computer program can be stored on a computer readable medium. BRIEF DESCRIPTION OF DRAWINGS

[0022] Embodiments of the application will now be described, by way of example only, with reference to the accompanying drawings in which:

[0023] Figure 1a logically illustrating three different quantisation operations 110, 120, 130;

[0024] Figure 1b logically illustrating the application of a double sign inversion truncation operation to an example arithmetic operation;

[0025] Figure 1c logically illustrating the application of a double sign inversion truncation operation to an example sequence of arithmetic operations;

[0026] Figure 2 logically illustrating the application of a double sign inversion truncation operation to a further example sequence of arithmetic operations;

[0027] Figure 3 schematically illustrating an example of a computation (or routine) comprising a plurality of arithmetic operations;

[0028] Figure 4An example of a computer system is schematically illustrated;

[0029] Figure 5 A method 400 of optimizing a routine for a hardware-based processing system having fixed-length two's complement binary representation is schematically illustrated;

[0030] Figure 6a Such a 4th order FIR filter is schematically illustrated;

[0031] Figure 6b An optimized version of the FIR filter in Figure 6a with a truncation operation is schematically illustrated;

[0032] Figure 6c An optimized version of the FIR filter in Figure 6a is schematically illustrated;

[0033] Figure 7a An analysis-synthesis filter bank is schematically illustrated;

[0034] Figure 7b An analysis-synthesis filter bank optimized with a double sign inversion truncation operation is schematically illustrated. DETAILED DESCRIPTION

[0035] In the following description and in the various figures, certain embodiments of the application are described. However, it will be appreciated that the application is not limited to the embodiments described and some embodiments can not include all of the features described below. It will be apparent, however, that various modifications and changes can be made within the broader spirit and scope of the application as set forth in the appended claims.

[0036] Figure 1a Three different quantization operations 110, 120, 130 are logically illustrated. Each quantization operation 110, 120, 130 takes an input variable (or signal or number) denoted as x(n) and provides a quantized version of the variable (or signal or number) as output according to a predefined fixed binary precision. The output variable of the quantization is denoted as x Q (n).

[0037] Operation 110 is a truncation operation. The truncation operation is denoted by the symbol T in the figures, or as the mathematical function T(). The truncation operation takes as input a variable x(n) in two's complement binary representation and discards (or truncates) the least significant binary digits to produce a quantized binary output variable x Q (n) of a predefined fixed binary precision. For example, if the input variable x(n) is 6 bits long and is assigned the decimal value 13 10then the input variable x(n) will have a two's complement binary representation of 0011012. In the foregoing and hereafter, the subscript 10 indicates a decimal representation and the subscript 2 indicates a two's complement binary representation. In this example, the fixed binary width is 4 bits. The truncation operation discards (or removes) the two least significant bits to produce a 4-bit wide quantized output variable. In particular, the quantized binary output variable x Q (n) has a value of 0011 00 2, which is 12 in decimal representation. 10 Thus, the truncation introduces an error of -1 10 . Here, for ease of understanding, the discarded binary bits are kept as zero values and underlined, but it will be appreciated that these bits are not stored (and thus assumed to be zero) in the 4-bit wide output.

[0038] Similarly, in another example, the input variable x(n) can be assigned a decimal value of -13 10 then the input variable x(n) will have a two's complement binary representation of 1100112. In this example, the truncation operation outputs a quantized binary output variable x 00 (n) having a value of 1100 Q 2, which is -16 in decimal representation. 10 Thus, the truncation introduces an error of -3 10 . It will be appreciated that when truncating a two's complement binary representation, the introduced error will always be less than or equal to zero. Thus, when multiple such functions are implemented in a sequence of arithmetic operations, the average error can be non-zero. Thus, the truncation error in a sequence of arithmetic operations can have a large contribution to the overall mean squared error (MSE) over the overall sequence of arithmetic operations.

[0039] Still further, it will be appreciated that when such truncation is implemented in hardware (by a general purpose processor, or as an operation on a dedicated chip, an operation of a field programmable gate array, etc.), there are no additional hardware requirements. Rather, the discarded (or truncated) bits are simply not stored in the corresponding register in the processor, or simply not passed to a subsequent hardware block.

[0040] Operation 120 is a rounding (or rounding to nearest) operation. The rounding operation is represented in the figures by the symbol R, or as the mathematical function R(). The rounding operation takes as input a two's complement binary representation of an input variable x(n) and rounds the input variable to the nearest quantized binary digit of a pre-definable fixed binary precision representation. The nearest quantized binary digit of the pre-definable fixed binary precision representation is assigned to a quantized binary output variable x Q (n). For example, if the input variable x(n) is 6 bits long and is assigned a decimal value of 13 10then the input variable x(n) will have a signed binary representation of 0011012. In this example, the fixed binary width is 4 bits. The rounding operation produces a quantized output variable of 4 bits wide. In particular, the quantized binary output variable x Q (n) has a value of 0011 00 2, which in decimal representation is 12 10 . Thus, the rounding introduces an error of -1 10 . Here, the discarded binary bits are kept as zero values and underlined for ease of understanding, but it will be appreciated that these bits are not stored (and thus assumed to be zero) in the 4-bit wide output. It will be understood that there are several different such rounding schemes to handle the case where the number to be rounded is equidistant between two quantized binary numbers, such as round half to even, round to even, etc.

[0041] Similarly, in another example, the input variable x(n) can be assigned a decimal value of -13 10 then the input variable x(n) will have a signed binary representation of 1100112. In this example, the rounding operation outputs a quantized binary output variable x 00 (n) having a value of 1101 Q 2, which in decimal representation is -12 10 . Thus, the rounding introduces an error of +1 10 . It will be appreciated that when rounding a signed binary representation, the error introduced can be positive or negative or zero. Thus, when multiple such functions are implemented in a sequence of arithmetic operations, the average error tends to zero. Thus, the rounding error in a sequence of arithmetic operations can have a small (or zero) contribution to the overall mean squared error (MSE) over the overall sequence of arithmetic operations.

[0042] Still further, it will be appreciated that when implementing such rounding in hardware (by a general purpose processor, or as an operation on a dedicated chip, operation of a field programmable gate array, etc.), there are additional hardware requirements. In particular, additional arithmetic operations are needed to implement the rounding. Typically, at least an additional addition operation (or hardware adder) is needed.

[0043] In the present disclosure, a modified truncation operation is presented. This is referred to herein as a double sign inversion truncation (DIT) operation. Mathematically, this can be understood as a sign inversion truncation of a sign inversion variable. Given a variable x and a truncation operation T(), the DIT operation T'( ) can be expressed as: T'(x) = -T(-x).

[0044] It will be appreciated that since the truncation operation T() produces a negative mean value error as set forth above, the sign inversion of the truncated sign inversion variable produces a positive mean value error. For example, take the decimal number 2.5 10which has a two's complement fixed-point binary representation of 010.12, the truncation operation T() for a 3-bit wide output gives: T(2.5 10 ) = T(010.12) = 0102= 2 10 . This has an error of -0.5 10 . Conversely, the DIT operation gives: T'(2.5 10 ) = -T(101.12) = -1012= 0112= 3 10 . This has an error of +0.5 10 .

[0045] In other words, by inverting the sign of x prior to truncation, an error with a negative average value as expected from truncation is achieved, and by finally inverting back the sign, the average error becomes positive.

[0046] Figure 1a The operation 130 logically illustrated in FIG. 1 is an implementation of a double sign inversion truncation operation. The operation 130 includes a first (or initial) sign inversion operation 131, a truncation operation 110, and a second (or final) sign inversion operation 132.

[0047] Each sign inversion operation 131, 132 takes as input an input variable in two's complement binary representation and inverts the sign of the input variable to produce an output variable of opposite sign. It will be appreciated that a sign inversion operation is mathematically equivalent to multiplying by -1 10 .

[0048] The first sign inversion operation 131 takes as input the input variable x(n) of the operation 130. The first sign inversion operation 131 provides as output to the truncation operation 110 a sign-inverted version of the input variable x(n). The description of the truncation operation 110 above applies equally here.

[0049] The output of the truncation operation 110 is provided as input to the second sign inversion operation 132. The second sign inversion operation 132 provides as output a sign-inverted version of the output of the truncation operation 110. The sign-inverted version of the output of the truncation operation 110 forms (or is) the quantized binary output variable x Q (n) for (or corresponding to) the input variable x(n) of the operation 130.

[0050] For example, if the input variable x(n) is 6 bits long and is assigned the decimal value 13 10 , then the input variable x(n) will have a two's complement binary representation of 0011012. In this example, the fixed binary width is 4 bits. The truncation operation 110 produces a quantized output variable that is 4 bits wide. In particular, the first sign inversion operation produces a value of 1100112 or -13 10The truncation operation 110 produces an output 1100 00 2 or -16 10 Finally, the second sign inversion operation 131 produces a quantized binary output variable x Q (n) 0100 00 2 or 16 2. Error is +3 10 As can be seen, this is the opposite of the error sign that would be obtained by applying the truncation operation 110 without any sign inversion operations.

[0051] Similarly, in another example, the input variable x(n) can be assigned the decimal value -13 10 The input variable x(n) will then have a signed binary representation of 1100 12. In particular, the first sign inversion operation produces a value of 0011 012 or 13 10 The truncation operation 110 produces an output of 0011 00 2 or 12 10 Finally, the second sign inversion operation 131 produces a quantized binary output variable x Q (n) 1101 00 2 or -12 2. Error is +1 10 As can be seen, this is the opposite of the error sign that would be obtained by applying the truncation operation 110 without any sign inversion operations. It will be appreciated that when the DIT operation is applied to a signed binary representation, the introduced error will always be greater than or equal to zero. Thus, when multiple such functions are implemented in an arithmetic operation sequence, the average error is greater than or equal to zero, and likely greater than zero. Thus, the truncation error in the arithmetic operation sequence can have a large contribution to the overall mean squared error (MSE) over the overall arithmetic operation sequence.

[0052] Still further, it will be appreciated that when such a DIT is implemented in hardware (by a general purpose processor, or as an operation on a dedicated chip, an operation of a field programmable gate array, etc.), at most two additional addition operations (or hardware adders) are required. However, as described below, one or both of the sign inversion operations 131, 132 can be implemented as part of other existing arithmetic operations that are present in a given arithmetic operation sequence. In such a case, the required additional additional addition operations (or hardware adders) can be reduced to one or zero.

[0053] Figure 1bThe diagram logically illustrates the application of the DIT operation to an example arithmetic operation. Specifically, a constant multiplication operation 151 is shown. In the first sequence 150, a constant multiplication operation 151 applied to the input variable x(n) is shown. The input variable is then quantized to a fixed binary width using a truncation operation 110. As described above, the error introduced by the truncation of the output is always less than or equal to zero. Therefore, the first sequence 150 performs arithmetic on x(n)B with respect to a constant B, which is affected by the quantization error in the output.

[0054] The second sequence 160 is a modified version of the first sequence 150 using the double sign-inverting truncation operation 130. As can be seen, the constant multiplication operation 151 has been modified to perform the first sign-inverting operation 131 of the DIT operation without additional hardware overhead. In particular, the sign of the predefined constant B has been inverted, which results in the sign inversion of the required input without requiring additional operations. The second sign-inverting operation 132 is retained. The second sign-inverting operation 132 can be considered as compensating for the sign inversion of the predefined constant B, so that sequence 160 performs arithmetic operations on x(n)B for a certain constant B, which is affected by quantization error in the output. As described above, in this case, the error introduced by the quantization of the output is always greater than or equal to zero. However, in this case, the DIT operation requires only one additional operation (or hardware adder-subtractor) compared to the non-sign-inverting truncation sequence 150. For example, sign inversion can be performed using a subtractor to subtract the value to be inverted from zero.

[0055] Figure 1c The diagram logically illustrates the application of the DIT operation to example arithmetic operation sequences. Specifically, three arithmetic operation sequences 170, 180, and 190 are shown, each implementing (or performing) the calculation:

[0056] Ax(n) + By(n) = z(n)

[0057] For two input variables x(n) and y(n), and two predefined constants A and B, the output z(n) is affected by quantization error.

[0058] The first sequence 170 comprises two constant multiplication operations 151. One constant multiplication operation 151 multiplies the input x(n) by a predefined constant A, and the other constant multiplication operation 151 multiplies the input y(n) by a predefined constant B. The output of each constant multiplication operation 151 is truncated using a corresponding truncation operation 110, and then combined by an addition operation 171. As described above, each truncation operation 110 introduces a quantization error less than or equal to zero. Therefore, the overall error due to quantization on the output z(n) is less than or equal to zero. Furthermore, the quantization error introduced by the corresponding truncation operation 110 is always additive. Therefore, through multiple executions of the sequence 170, the two truncation operations 110 will increase the average error of the output z(n).

[0059] In contrast, the second sequence 180 includes a rounding operation 120 instead of a truncation operation 110. As described above, the quantization error introduced by the rounding operation 120 may be positive, negative, or zero. Therefore, through multiple executions of sequence 180, the average error of the output z(n) from the rounding operation 120 should tend to zero. However, due to the additional arithmetic operations required to implement the rounding operation 120, the hardware or operational overhead of the second sequence 180 is greater than that of the first sequence 170.

[0060] The third sequence includes truncation operation 110 and DIT operation 130. Specifically, the output of x(n) multiplied by constant A is truncated in the same manner as the first sequence 170. However, the input y(n) multiplied by a predefined constant B is truncated using DIT operation 130. In this example, the multiplication operation 151 associated with constant B has been modified to incorporate the first sign inversion operation 131 of DIT operation 130. This is as described above regarding... Figure 1b This is accomplished by inverting the sign of the constant B. Furthermore, the addition operation 171 has been modified to incorporate the second sign inversion operation 132 of the DIT operation 130. This has been done by changing the addition operation 171 to a subtraction operation 171. In this way, the computation performed by sequence 190 is preserved. However, it is now ensured that the quantization error introduced by the truncation of the output of y(n) multiplied by the constant B is greater than or equal to zero. The quantization errors in the third sequence 190 tend to cancel each other out. Therefore, through multiple executions of sequence 190, the average error from the quantized output z(n) should tend to zero.

[0061] Furthermore, since the first sign inversion 131 and the second sign inversion 132 are incorporated into the existing operations in sequence 190, there is no additional hardware or operational overhead compared to the first sequence. It will be understood that the computation Ax(n) + By(n) = z(n) described above forms part of many linear time-invariant routines (including but not limited to digital filters, fast Fourier transforms, discrete cosine transforms, neural network inference, etc.), and therefore the optimizations using DTI operations described above can be applied to hardware or software implementations of such routines, thereby improving accuracy and reducing hardware or processing overhead.

[0062] More generally, this disclosure has inventively achieved that, when implemented on a digital processing machine, arbitrary computation including sequences of arithmetic operations affected by quantization can be optimized by pairing subsets of arithmetic instructions with comparable truncation errors, and applying the DIT operation described above to one subset of each pair and applying standard truncation to another subset of each pair. This optimization provides error performance similar to or exceeding that of rounding operations, but with lower hardware overhead.

[0063] Figure 2 The diagram logically illustrates the application of the DIT operation to other example arithmetic operation sequences. Specifically, three arithmetic operation sequences 210, 220, and 230 are shown, each implementing (or performing) the calculation:

[0064] x(n)·a(n)+y(n)·b(n)=z(n)

[0065] For four input variables x(n), y(n), a(n), and b(n), the output z(n) is affected by quantization error.

[0066] The first sequence 210 comprises two multiplication operations 211. One multiplication operation 211 multiplies the input x(n) by the input a(n), and the other multiplication operation 211 multiplies the input y(n) by the input b(n). The output of each multiplication operation 211 is truncated using a corresponding truncation operation 110, and then combined by an addition operation 171. As described above, each truncation operation 110 introduces a quantization error less than or equal to zero. Therefore, the overall error due to quantization on the output z(n) is less than or equal to zero. Furthermore, the quantization error introduced by the corresponding truncation operation 110 is always cumulative. Therefore, through multiple executions of the sequence 210, the two truncation operations 110 will increase the average error of the output z(n).

[0067] In contrast, the second sequence 220 includes a rounding operation 120 instead of a truncation operation 110. As described above, the quantization error introduced by the rounding operation 120 can be positive, negative, or zero. Therefore, through multiple executions of sequence 220, the average error of the output z(n) from the rounding operation 120 should tend to zero. However, due to the additional arithmetic operations required to implement the rounding operation 120, the hardware or operational overhead of the second sequence 220 is greater than that of the first sequence 210.

[0068] The third sequence includes a truncation operation 110 and a DIT operation 130. Specifically, the output of x(n) multiplied by the input a(n) is truncated in the same manner as the first sequence 210. However, the input y(n) multiplied by b(n) is truncated using the DIT operation 130. Unlike sequence 190 above, the multiplication operation 211 is not a constant multiplication operation, and therefore it cannot be incorporated into the first sign inversion operation 131 without additional overhead. Therefore, sequence 230 is modified to incorporate a separate first sign inversion operation 131, which inverts the sign of the input b(n) before the multiplication operation 211. (As mentioned above...) Figure 1c As described, the addition operation 171 has been modified to incorporate the second sign inversion operation 132 of the DIT operation 130. This has been accomplished by changing the addition operation 171 to a subtraction operation 171. In this way, the computation performed by sequence 230 is preserved. As previously stated, the quantization errors in the third sequence 230 tend to cancel each other out. Therefore, through multiple executions of sequence 230, the average error from the quantized output z(n) should tend to zero.

[0069] Furthermore, since the second sign inversion 132 is incorporated into the existing operation in sequence 230, the third sequence 230 requires only one additional addition operation (or hardware adder) compared to the first sequence 210. In contrast, the second sequence 220, which uses rounding operations, requires at least two additional addition operations (or hardware adders) compared to the first sequence 210. It will be appreciated that the computation x(n)·a(n) + y(n)·b(n) = z(n) described above forms part of a matrix and vector multiplication routine, and therefore the optimizations using DTI operations described above can be applied to hardware or software implementations of such routines, thereby improving accuracy and reducing hardware or processing overhead.

[0070] In the example above, for ease of understanding, the DIT operation has been described with respect to a computation (in which the results of two arithmetic operations are combined to provide an output). However, it will be appreciated that the optimization using the DIT operation described above can be implemented on larger, more complex computations. In particular, the DIT operation can be used to optimize any computation (or routine) that can be divided into two subsets of instructions (or arithmetic operations), the outputs of which are combined to provide a result. Where the partition can be arranged such that the output of the first subset of instructions has a truncation error equivalent to that of the output of the second subset of instructions, optimization can be performed by applying a standard truncation operation to the first subset of instructions and applying the DIT operation to the second subset of instructions. This optimization typically involves modifying the second subset of instructions to invert the sign of the inputs of said subset, and modifying the sequence of computations (or routines) to compensate for said inversion. This compensation typically includes inverting the sign of the output of the second subset. As explained above, this can be implemented by modifying the operation that combines the outputs of the first and second subsets. In this way, the truncation error between the first and second subsets is canceled out. Here, the first and second subsets of instructions can be considered as forming subset pairs. More generally, the optimization may include dividing the computation (or routine) into more than one such subset pairs of instructions, each subset having a corresponding equivalent truncation error. Each pair can then be modified in the same manner as the pairs formed by the first and second subsets described above.

[0071] To understand, calculations (or routines) can be included in a sequence of instructions (or arithmetic operations) that can remain unchanged before and / or after one or more pairs.

[0072] Figure 3 An example of computation 300 (or routine) including multiple arithmetic operations is schematically illustrated. Specifically, the computation can be divided into two linear time-invariant computation systems 321 and 322. Each linear time-invariant computation system 321 and 322 includes multiple arithmetic operations affected by quantization errors. Implementation of computation 300:

[0073] F LTI (u(n))+G LTI (x(n))=z(n)

[0074] Where u(n) and x(n) are the inputs, F LTI () and G LTI () represent the first linear time-invariant computation system and the second linear time-invariant computation system, respectively. w(n) and y(n) represent the outputs of the first linear time-invariant computation system 321 and the second linear time-invariant computation system 322, respectively. In other words, F LTI (u(n))=w(n) and G LTI(x(n)) = y(n).

[0075] like Figure 3 As shown, calculation 300 combines the output w(n) of the first linear time-invariant calculation system 321 with the output y(n) of the second linear time-invariant calculation system 322.

[0076] Figure 3 As shown, DIT optimization has been applied. Therefore, computation 300 includes a first inversion operation 131 applied to the input x(n) of the second linear time-invariant computation system 322. Similarly, addition 330 has been modified to subtract the current sign-inverted output -y(n) of the second linear time-invariant computation system 322.

[0077] It will be understood that all arithmetic operations in the first linear time-invariant computation system 321 and the second linear time-invariant computation system 322 are affected by truncation operations. For the second linear time-invariant computation system 322, the first inversion operation 131 and the modification of the compensation modification addition operation 330 form a first inversion operation and a second inversion operation for each truncation, respectively. Therefore, truncation in the second linear time-invariant computation system 322 is a DTI operation. Therefore, the average errors of w(n) and y(n) will have the same absolute value but different signs. Therefore, the average error due to the truncation of the overall output z(n) will tend to zero. It will be appreciated that if only truncation is used (where the error will tend to increase in magnitude), this is an improvement on the average error on z(n) of the unmodified computation 300.

[0078] Therefore, it will be understood that a given algorithm (or routine or computation) – which can be divided into two parts (or subsets of instructions), each with an equal truncation error – can be optimized using DTI operations to ensure a zero-mean truncation error. This can be accomplished regardless of whether the two parts have different or similar operations, and regardless of whether the two parts have different or identical inputs. By extension, it will be understood that a given algorithm (or routine or computation) – which can be divided into N parts (or subsets of instructions), each with an equal truncation error – can be optimized using DTI operations to ensure a zero-mean truncation error.

[0079] Figure 4 An example of a computer system 1000 is schematically illustrated. System 1000 includes a computer 1020. Computer 1020 includes: storage medium 1040, memory 1060, processor 1080, interface 1100, user output interface 1120, user input interface 1140, and network interface 1160, all of which are linked together via one or more communication buses 1180.

[0080] Storage medium 1040 can be any form of non-volatile data storage device, such as one or more of hard disk drives, magnetic disks, optical disks, ROMs, etc. Storage medium 1040 can store an operating system for execution by processor 1080 to run computer 1020. Storage medium 1040 can also store one or more computer programs (or software, instructions, or code).

[0081] The memory 1060 may be any random access memory (memory cell or volatile storage medium) suitable for storing data and / or computer programs (or software or instructions or code).

[0082] Processor 1080 may be any data processing unit suitable for executing one or more computer programs (such as those stored on storage medium 1040 and / or memory 1060), some of which may be computer programs according to embodiments of the present invention, or computer programs that, when executed by processor 1080, cause processor 1080 to implement methods according to embodiments of the present invention and configure system 1000 as a system according to embodiments of the present invention. Processor 1080 may include a single data processing unit, or multiple data processing units operating in parallel or cooperatively. When performing data processing operations for embodiments of the present invention, processor 1080 may store data in storage medium 1040 and / or memory 1060, and / or read data from storage medium 1040 and / or memory 1060.

[0083] Interface 1100 can be any unit that provides an interface to a device 1220 external to or removable from computer 1020. Device 1220 can be one or more data storage devices, such as optical discs, hard disks, solid-state storage devices, etc. Device 1220 can have processing capabilities—for example, the device can be a smart card. Therefore, interface 1100 can access data from device 1220, provide data to device 1220, or interact with device 1220 in accordance with one or more commands received from processor 1080.

[0084] User input interface 1140 is configured to receive input from a user or operator of system 1000. The user may provide this input via one or more input devices of system 1000, such as a mouse (or other pointing device) 1260 and / or a keyboard 1240, which are connected to or communicate with user input interface 1140. However, it will be appreciated that the user may provide input to computer 1020 via one or more additional or alternative input devices, such as a touchscreen. Computer 1020 may store the input received from the input device via user input interface 1140 in memory 1060 for subsequent access and processing by processor 1080, or may pass it directly to processor 1080 so that processor 1080 can respond accordingly to user input.

[0085] User output interface 1120 is configured to provide graphical / visual and / or audio output to a user or operator of system 1000. Therefore, processor 1080 may be configured to instruct user output interface 1120 to generate an image / video signal representing desired graphical output and to provide such signal to a monitor (or screen or display unit) 1200 of system 1000 connected to user output interface 1120. Additionally or alternatively, processor 1080 may be configured to instruct user output interface 1120 to generate an audio signal representing desired audio output and to provide such signal to one or more speakers 1210 of system 1000 connected to user output interface 1120.

[0086] Ultimately, network interface 1160 provides computer 1020 with the ability to download data from one or more data communication networks and / or upload data to one or more data communication networks.

[0087] General Figure 4 The architecture of the system 1000 illustrated and described above is merely exemplary, and different architectures (e.g., with more) are possible. Figure 4 Other computer systems 1000 (with fewer components or having additional and / or alternative components than those shown in FIG. 1) can be used in embodiments of the present invention. As an example, computer system 100 may include one or more of the following: personal computer; server computer; mobile phone; tablet computer; laptop computer; television set; set-top box; game console; other mobile devices or consumer electronics; etc.

[0088] Figure 5A method 400 for optimizing routines for a hardware-based processing system with a fixed-length binary complement representation is schematically illustrated. As will be understood from the preceding discussion, existing routines can be automatically optimized by including DIT operations (suitable for the fixed-length requirements of the target hardware processing system). The target hardware processing system can be a general-purpose processing system, such as... Figure 4 The system 1000 described herein. In this case, the fixed-length requirement is typically determined by the architecture of the processor 1080. The fixed length may depend on the type of variable in the arithmetic operation. Typically, the fixed length is a power of 2 multiple of the word length in the architecture of the processor 1080. Similarly, it will be understood that the target hardware processing system can be an embedded system (or system-on-a-chip) or a component thereof. For example, the target hardware processing system can be (or include) an application-specific integrated circuit (ASIC). In another example, the target hardware processing system can be (or include) a field-programmable gate array (FPGA). In this case, the bit length can be enforced according to the operator.

[0089] Therefore, it will be understood that a routine can be a software routine executed by a processor. Similarly, a routine can be a description of a hardware routine used to produce ASICs, FPGAs, or other embedded systems.

[0090] A routine specifies (or describes or otherwise embodies) an algorithm to be implemented by a computing system, such that implementing (or executing) the routine results in the implementation (or execution) of the algorithm.

[0091] To understand, Method 400 is typically composed of, for example Figure 4 The computing system described in System 1000 is executed. However, the computing system implementing Method 400 is not required to be the same type (or category) of computing system as the target hardware processing system.

[0092] At step 410, a sequence of instructions is received, which is arranged to execute a routine. As explained above, the target hardware processing system for the routine may be a general-purpose computer in some cases and an embedded system in others. Therefore, the sequence of instructions may be represented (or received) as any of the following: a high-level software language (such as C, C++, C#, etc.), a low-level programming language (such as assembly language, machine code), or a hardware description language (such as VHDL, Verilog, etc.). It will also be understood that method 400 may be implemented as part of the compilation of software code in a high-level language. Therefore, the sequence of instructions may be represented (or received) as a compiler intermediate representation or intermediate language.

[0093] Typically, the instruction sequence includes (or specifies or otherwise represents) a sequence of arithmetic operations. At least some of the arithmetic operations will produce outputs exceeding the precision of the target hardware-based processing system. The instruction sequence may have specified (or included) quantization operations (such as truncation or rounding) to be performed on the output of the arithmetic operations. Alternatively, in some cases, the instruction sequence may not specify how the output of the arithmetic operations should be quantized.

[0094] In step 420, one or more pairs of instruction subsets in the instruction sequence are identified. This identification is performed such that each subset has a corresponding equivalent truncation error. It will be understood that each instruction subset may include more than one arithmetic operation. In fact, the subset itself may be or include complex routines. A subset may have more than one input variable and may have more than one output. Similarly, a subset may include more than one instruction sequence and therefore may include one or more instruction branches. Two subsets of a given pair are identified if the outputs of each subset are later combined in the instruction sequence. Step 420 can be implemented by static analysis of the instruction sequence. For example, as described above, several predefined computations (or primitive computations) with predefined partitions (or subset pairs) can be identified. Examples described above include computations of the form: Ax(n) + By(n) = z(n), x(n)·a(n) + y(n)·b(n) = z(n), F LTI (u(n))+G LTI (x(n)) = z(n), etc. Similarly, as briefly described below for some known computational structures, analytical methods can be used to determine pairs (or partitions) of instruction subsets. It will also be understood that dynamic analysis can be used to identify instruction subsets that produce considerable truncation errors. This can be implemented by running a simulation of candidate instruction subsets on an appropriate range of inputs. Therefore, identification step 420 may include calculating the corresponding average error in the output of the software routine due to the truncation of each arithmetic operation in the set of arithmetic operations, and identifying subset pairs to minimize the sum of the corresponding average errors.

[0095] In step 430, an optimized routine (or a version of the routine) is generated. The optimized routine is generated by arranging the routine to apply DIT operations to a subset of instructions for each pair and to apply truncation (or standard truncation) to another subset of instructions for each pair. In this way, the optimized routine is arranged to cancel out truncation errors between each pair of subsets. Typically, for each pair, step 430 includes modifying 432 a subset of the subset of each pair to invert the sign of one or more inputs of said subset. As described above, modification step 432 may include including (or introducing) one or more sign inversion operations into the instruction subset. Additionally or alternatively, modification step 432 may include inverting the sign of one or more multiplication constants specified (or present) in the instruction subset.

[0096] Step 430 includes modifying the instruction sequence 434 to compensate for the inversion. Modifying step 434 typically includes including a compensation operation in the instruction sequence. The compensation operation is arranged to compensate (or adjust or otherwise modify) the instruction sequence based on the inversion, such that the operation of the routine is preserved. In other words, the compensation operation compensates for the inversion, thereby preserving the routine functionality when the algorithm is implemented. As described above, the compensation operation may be or include a sign inversion operation applied to one or more outputs of a subset of instructions. Additionally or alternatively, modifying step 434 may include changing the operations in the instruction sequence that combine the outputs of subset pairs to cause a change in sign. For example, an addition operation may be changed to a subtraction operation, or vice versa.

[0097] As discussed above, in some cases, the instruction sequence may have already specified (or included) a quantization operation. Therefore, step 430 may include replacing one or more rounding operations in the subset pair with a truncation operation. Alternatively, the instruction sequence may not specify how to quantize the output of the arithmetic operation. Therefore, step 430 may include embedding a truncation operation into the subset pair.

[0098] Step 430 generates an optimized routine represented by a modified sequence of instructions.

[0099] As indicated by optional step 440, the optimized routine can be further used. Step 440 may include outputting a modified sequence of instructions for further use (further processing). For example, where the instruction sequence specifies a hardware routine, step 440 may include providing a modified sequence of instructions for manufacturing one or more embedded systems (such as an ASIC or FPGA). Step 440 may include compiling the modified sequence of instructions into a netlist.

[0100] Similarly, when the instruction sequence specifies a software routine, step 440 may include compiling the modified instruction sequence to generate executable code for the routine.

[0101] While optimizations using DIT operations can be automatically implemented for any routine (or computation) as described above, there are certain types of widely used computations that can be beneficially implemented in hardware (or software) using DIT operations, optimized for specific bit length requirements of a particular digital processing system. Some examples of such routines are provided below. It will be appreciated that these described routines can also be identified and optimized using the method 400 described above.

[0102] General matrix multiplication and dot product

[0103] Matrix multiplication is a fundamental operation in many fields, including but not limited to channel equalization, neural networks, and LTI algorithms. The output of a multiplication typically requires quantization because the number of bits in the result is always greater than the number of bits in the operands. An 8-bit multiplication produces a 16-bit result. Multiplication is one of the main operations in matrix multiplication and dot products. Furthermore, multiplication in matrix multiplication and dot products is combined with addition. Each element of a matrix or vector can be considered as the sum of the multiplication results.

[0104] Two N-dimensional column vectors and The dot product can be expressed as:

[0105]

[0106] in yes The transpose of .

[0107] One approach to quantification would be to use the following rounding:

[0108]

[0109] This requires N multiplications, N rounding operations (with the same computational cost as additions), and N-1 two-input additions.

[0110] Conversely, the DIT operation can be used to truncate half of the multiplication. And apply the DIT operation to the remaining multiplications:

[0111]

[0112] This requires N multiplications, N / 2 sign inversions (where the cost of a single computation is similar to rounding), N-2 two-input additions, and one two-input subtraction.

[0113] The only additional cost is N / 2 sign inversions, which is less computationally expensive than N rounding operations. Note that N-2 additions plus a single subtraction are computationally cost-effective as N-1 additions.

[0114]

[0115] Table 1. - Operations required for non-constant dot products with rounding and DIT.

[0116] When implemented in hardware (such as FPGAs or ASICs), the overall hardware cost of using DIT is reduced compared to applying rounding. In software implementations, using DIT reduces the overall computational cost of executing routines compared to applying rounding. Similar reasoning can be applied to matrix multiplication.

[0117] Referring to method 400 described above, a routine may include an N-dimensional scalar product of two vectors, and the instruction sequence includes summing the multiplications of the N vector coefficients. In this example, identification step 420 may identify a pair of instruction subsets such that the first subset of instructions includes summation. The first subset consists of half of the N multiplications, and the second subset consists of the other half of the N multiplications. Therefore, modification step 432 may include N / 2 sign reversal operations to reverse the elements in the summation of the first subset. Modification step 434 may include including a compensation operation in the sequence, which is arranged to take the difference between the sums of the first and second subsets.

[0118] Constant matrix multiplication and dot product

[0119] Similarly, in many fields, when performing matrix or vector multiplication, one of the operands in the matrix or vector operation has a constant value over a long period. There are three possible scenarios.

[0120] a) The elements of the constant operands are read from memory once each time the overall program is run (or executed) and are never changed during runtime. Here, the required sign inversion can be pre-computed, and no additional computational or hardware overhead is incurred by using DIT.

[0121] b) Elements of constant operators are pre-computed, stored in memory, used for a long time during the operation, and then recomputed. Instead of inverting values ​​during matrix / vector multiplication, values ​​can be inverted before being stored in memory, thus incurring no additional computational or hardware overhead during the execution of the multiplication.

[0122] c) The elements of constant operands are never modified, and each operation using them has dedicated resources. This is typically the case in massively parallel systems, where each operand element has a dedicated multiplier. In this case, the multiplier is optimized to always perform multiplication with the constant, and the sign of the constant can be reversed (as previously discussed). Figure 1cAs described above, therefore, using DIT does not incur additional computational or hardware overhead.

[0123] Linear time-invariant algorithm

[0124] In LTI algorithms, analytical expressions can be found for the propagation of quantization errors caused at arbitrary points to the output. See, for example, D. Menard and O. Sentieys, "Automatic evaluation of the accuracy of fixed-point algorithms," Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, Paris, France, 2002, pp. 529-535, doi:10.1109 / DATE.2002.998351. Since these analytical expressions are well-known, they will not be described further in this paper. However, these analytical expressions can be used to partition LTI systems (where error propagation is asymmetric). In this case, assuming no rounding is applied, optimization methods can be applied to determine which quantizations must be truncated via DIT to minimize the average error of the output.

[0125] Example method is:

[0126] 1. Calculate the average error μ at each truncation point i. i .

[0127] 2. Calculate the mean factor m i The simulation error *i* propagates to the output. The average error at the output due to the truncation of *i* is *μ*. i,out =μ i ·m i .

[0128] Signal processing theory states that m i =∑ n g i (n), where g i (n) is the impulse response from the cutoff point to the output.

[0129] 3. Given a column vector Calculate N-dimensional column vectors Its minimization

[0130] For routines that include the LTI algorithm, this method can be used as part of the identification step 420 described above.

[0131] Step 3 can be performed using a brute-force search, specifically by generating... All combinations are considered, and the one that produces the minimum error is selected. Additional penalty functions (or costs) can also be used. For example, a vector that produces the minimum error can be selected while minimizing either code length (for software routines) or the number of gates (for routines to be implemented in hardware).

[0132] Alternatively, step 3 can be performed by solving the well-known partitioning problem, given a set of numbers (i.e., μ). i,out ·w i The partitioning problem seeks two partitions such that the sum of the elements in each partition is as close as possible. A partition can be assigned to a traditional truncation (i.e., w). i =1), and another partition can be assigned to DIT (i.e., w i =-1).

[0133] It will be understood that several well-known heuristics exist for solving the partitioning problem. These methods include greedy number partitioning, maximum difference algorithms, etc. Greedy number partitioning is described in "From approximate to optimal solutions: A case study of number partitioning" by Korf, Richard E. (August 1995), and included in "IJCAI'95: Proceedings of the 14th international joint conference on Artificial Intelligence" by Mellish, Chris S. (ed.), pp. 266–272, ISBN 978-1-55860-363-9. Maximum difference algorithms are described in "The differencing method of set partitioning" by N. Karmarkar, R.M. Karp, Technical Report UCB / CSD 82 / 113, Department of Computer Science, University of California, Berkeley, California, 1982. Therefore, these methods will not be discussed further in this paper.

[0134] An example of an LTI algorithm or computation is a 4th-order linear-phase FIR filter, defined as:

[0135] y[n]=x[n]·b0+x[n-1]·b1+x[n-2]·b2+x[n-3]·b3+x[n-4].b4

[0136] =x[n]·α+x[n-1]·β+x[n-2]·γ+x[n-3]·β+x[n-4]·α

[0137] =(x[n]+x[n-4])·α+(x[n-1]+x[n-3])·β+x[n-2]·γ

[0138] Figure 6a This fourth-order FIR filter is schematically illustrated. Boxes with addition symbols indicate addition operations, triangles indicate multiplication by the constant indicated in the triangle, circles indicate summation operations, and boxes labeled D indicate decrementing of the input index.

[0139] For this example:

[0140] · (6-digit complement: 0.100012)

[0141] · (6-digit complement: 0.111112)

[0142] · (6-digit complement: 0.101112)

[0143] The input (x[n]) is an 8-bit two-complement variable less than 1.

[0144] • The outputs of all multipliers are truncated to 8 bits.

[0145] The input multiplied by α is truncated to 4 bits.

[0146] The inputs multiplied by β and γ remain 8 bits.

[0147] The output of addition is not truncated.

[0148] Figure 6b An FIR filter with the required truncation operation is schematically illustrated, and the number of bits for all variables is shown. It will be understood that the number of bits chosen in this case is merely for ease of understanding, and this filter implementation can use different bit widths without loss of generality. Nevertheless, the bit width is consistent with ASIC design, and an LTI system with non-uniform averaging error at the output is demonstrated. Figure 6b In this context, the quantization error generated by each quantization has been labeled ∈0……∈4.

[0149] The average error value at the output is:

[0150]

[0151] μ 2,out =μ2=(2-7 -2 -11 ) = 0.00683593755 10

[0152] μ 3,out =(2 -7 -2 -13 ) = 0.007690429687500 10 =μ 4,out

[0153] Figure 6b The average error for the truncation case shown is 0.02734375. 10 As discussed above, for appropriate A brute-force search is feasible. In this case, there are 32 possible vectors. The vector that minimizes the average error at the output is shown below:

[0154] Optimal solution: a weight of 1 means truncation; -1 means DIT.

[0155]

[0156] In this case, four vectors They have the same minimum absolute value. However, the third and fourth solutions require less hardware. Figure 6c The fourth solution is illustrated schematically.

[0157] Analysis-synthesis filter bank (AS FB)

[0158] Analysis-synthesis filter banks are commonly used systems for speech enhancement in communication applications. Figure 7a A basic structural implementation with truncation is shown, and Figure 7b This illustrates how a DIT operation can be applied to cancel the average error at the output v(n) (assuming the quantization applied to each channel is the same). For both systems shown, a truncation is used to implement the filter and the spectral weighting block. Note that the filter is an LTI system, but the spectral weighting block is not. However, it can be shown that the spectral weighting block does not modify the sign of the error.

[0159] As can be seen, the analysis-synthesis filter bank comprises several channels 710 with a common input y(n). The outputs of the channels 710 are summed using a combination operation 171 to provide the output v(n). Therefore, the DIT operation can be applied to a subset of the M channels. Standard truncation can be applied to another non-overlapping subset of the M channels. In this way, the error cancellation between the first M channels and the second M channels described above can be achieved without using rounding operations.

[0160] This segmentation can be implemented automatically in the identification step 420 described above.

[0161] exist Figure 7a and Figure 7b In the specific example shown, it can be seen that a single sign inversion operation is introduced into the input of the first two channels. Combination operation 171 is then modified to subtract the outputs of the first two channels from the sum of the outputs of the remaining channels. Therefore, the output v(n) is preserved.

[0162] It will be appreciated that the described method has been shown as individual steps performed in a specific order. However, those skilled in the art will appreciate that these steps can be combined or performed in a different order while still achieving the desired result.

[0163] It will be understood that embodiments of the present invention can be implemented using a wide variety of different information processing systems. In particular, while the figures and their discussion provide exemplary computing systems and methods, these are merely presented to provide useful reference in discussing various aspects of the invention. Embodiments of the invention can be implemented on any suitable data processing device, such as a personal computer, laptop computer, personal digital assistant, mobile phone, set-top box, television, server computer, etc. Of course, for the purposes of discussion, the description of the systems and methods has been simplified, and they are merely one of many different types of systems and methods that can be used in embodiments of the invention. It will be understood that the boundaries between logical blocks are merely illustrative, and alternative embodiments may combine logical blocks or elements, or may enforce alternative decompositions of functionality for various logical blocks or elements.

[0164] As will be appreciated, the above-described functions can be implemented as one or more corresponding modules in hardware and / or software. For example, the above-described functions can be implemented as one or more software components for execution by the system's processor. Alternatively, the above-described functions can be implemented as hardware, such as on one or more field-programmable gate arrays (FPGAs) and / or one or more application-specific integrated circuits (ASICs) and / or one or more digital signal processors (DSPs) and / or other hardware arrangements. The method steps implemented in the flowcharts included herein or as described above can each be implemented by their respective corresponding modules; the multiple method steps implemented in the flowcharts included herein or as described above can be implemented together by a single module.

[0165] As will be understood, with respect to embodiments of the present invention implemented by a computer program, the storage medium and transmission medium carrying the computer program form aspects of the present invention. A computer program may have one or more program instructions or program code that, when executed by a computer, implement embodiments of the present invention. As used herein, the term "program" can be a sequence of instructions designed to execute on a computer system and may include subroutines, functions, procedures, modules, object methods, object implementations, executable applications, client applets, server applets, source code, object code, shared libraries, dynamic link libraries, and / or other sequences of instructions designed to execute on a computer system. The storage medium may be a disk (such as a hard disk drive or floppy disk), an optical disk (such as a CD-ROM, DVD-ROM, or Blu-ray disc), or a memory (such as ROM, RAM, EEPROM, EPROM, flash memory, or portable / removable memory devices), etc. The transmission medium may be a communication signal, data broadcast, a communication link between two or more computers, etc.

[0166] Appendix A

[0167] It can be proven that the statistical properties of the error with mean μ = 0 (which is the sum of the errors with each mean μ) i =0 and variance N independent errors n i The error between the sum of the two values ​​(μ) and the mean μ = 0 (which is the error of the sum of the two values ​​μ) is the error of the sum of the two values ​​(μ) and the mean μ = 0. i Any value and the same variance as in the first case N independent errors n i The result of addition is the same. Therefore, statistically, the use of the DIT operation described above will always produce the same result as rounding.

[0168] Given a rounding variable s i A set of errors n i They have a zero-mean probability density function (pdf). If s i Instead of being rounded, truncation was applied, resulting in noise. The resulting PDF is similar, but the left shift is equal to the non-zero mean. If DTI operations are applied instead, then the pdf is

[0169] First, let's look at the effect of moving pdf along a random variable, given a characteristic function (cf)Φ. X (ω) of pdff X (x), characteristic function f X (x+Δ) is e jΔω φX (ω). It can be said that cf is the frequency transformation of pdf, making it suitable for studying random variables in the same terminology. Therefore, and

[0170] This demonstrates the effect of adding many independent random variables. Many independent variables X i The characteristic function of the sum is equal to

[0171] Finally, considering the preceding points, the following can be proven: If the algorithm utilizes rounding, the error at its output will be determined by the rounding signal / variable s. i All generated errors n i The sum of . Therefore, the characteristic function will equal .

[0172] If the algorithm combines K truncations and M DIT operations, the output will be determined by the mean. The truncation error and mean are The DIT error is composed of... The cf of the output error is...

[0173]

[0174] If DIT technology is applied in the best way, then Make

[0175]

[0176] This proves that if DIT is applied to ensure that the population mean is zero, the resulting error pdf is exactly the same as rounding noise with an ideal zero mean.

Claims

1. A method for optimizing routines for a hardware-based processing system having a fixed-length binary complement representation, the method comprising: Receive a sequence of instructions, the sequence of instructions being configured to execute the routine, wherein the sequence of instructions includes a set of arithmetic operations, wherein the output of the arithmetic operations exceeds the precision of the hardware-based processing system; Identify one or more pairs of instruction subsets in the instruction sequence, each pair of subsets having a corresponding equivalent truncation error; An optimized routine is generated by modifying one of the subsets of each pair to invert the symbols of one or more inputs of the subset and modifying the instruction sequence to compensate for the inversion.

2. The method of claim 1, wherein modifying the instruction sequence comprises: The instruction sequence is modified to reverse the sign of the output of each subsequence with the reversed sign input.

3. The method of claim 1, wherein the instruction sequence includes at least one instruction for summing the outputs of corresponding subset pairs, and the modification of the instruction sequence includes: Each instruction used to sum the outputs is replaced with an instruction used to calculate the difference between the outputs of the corresponding subset pairs.

4. The method according to any one of the preceding claims, wherein modifying one of at least one subset of a pair to invert the sign of the input to the subsequence comprises: Reverse the sign of the multiplication constants used in the subset.

5. The method according to any one of the preceding claims, wherein the generation includes removing rounding operations from at least one pair of subsets.

6. The method according to any one of the preceding claims, wherein the routine comprises an N-dimensional scalar product of two vectors and the instruction sequence comprises summing the multiplications of the coefficients of the N vectors, optionally wherein the software routine implements matrix multiplication.

7. The method of claim 6, wherein each subsequence includes a corresponding vector coefficient multiplication, wherein the modified instruction sequence is the difference between the sum of a subset with inverted sign inputs and the sum of the other subsets.

8. The method according to any one of claims 1-5, wherein the routine implements a linear time-invariant (LTI) algorithm.

9. The method of claim 8, wherein identifying one or more subsets comprises: Calculate the corresponding average error in the output of the routine due to the truncation of each arithmetic operation in the set of arithmetic operations, optionally wherein identifying a pair or more subsets includes minimizing the sum of the corresponding average errors.

10. The method according to any one of claims 1-5, wherein the routine implementation comprises a filter bank of two or more channels, wherein each subset of instructions corresponds to a corresponding channel, and optionally, wherein the filter bank is an analysis-synthesis filter bank.

11. The method according to any one of the preceding claims, wherein the routine is a software routine or a hardware description language routine.

12. A method for computing the N-dimensional scalar product of two vectors in a hardware-based processing system having a fixed-length binary complement representation, the method comprising: Calculate the sum of the vector multiplications of the N / 2 vector coefficients in the scalar product, wherein the calculation includes truncating intermediate results that exceed the precision of the hardware-based processing system; Calculate the sum of the vector multiplications of the other N / 2 vector coefficients in the scalar product, wherein the calculation includes reversing the sign of each vector coefficient of one of the two vectors and truncating intermediate results that exceed the precision of the hardware-based processing system; The scalar product is obtained by calculating the difference between the sum of the multiplications of the N / 2 vector coefficients in the scalar product and the sum of the multiplications of the other N / 2 vector coefficients in the scalar product.

13. A method for implementing a filter bank with multiple channels in a hardware-based processing system having a fixed-length two's complement binary representation, the method comprising: Receive input signals; The filters of the first subset of M channels from the plurality of channels are applied to the input signal; The filters of the second subset of M channels from the plurality of channels are applied to the inverted symbol input signal; The output of the filter bank is generated by taking the difference between the output of the first subset of M channels and the output of the second subset of M channels.

14. A system configured to implement the method according to any one of claims 1 to 13.

15. An application-specific integrated circuit (ASIC) arranged to implement the method according to claim 12 or 13.

16. A computer-readable medium storing a computer program, which, when executed by a processor, causes the processor to perform the method according to any one of claims 1 to 13.

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