Active-disturbance-rejection control method for dual-active-bridge converter based on virtual impedance compensation

Abstract

The invention discloses a virtual impedance compensation-based active-disturbance-rejection control method for a dual-active-bridge converter, and the method comprises the following steps: firstly designing a virtual impedance compensation strategy, connecting an equivalent virtual conductor in parallel with an output capacitor, converting the equivalent virtual conductor into a duty ratio injection amount, and achieving the active counteracting of the negative impedance of a constant-power load and the reconstruction of the damping of a port; an unstable pole of the right half plane is made to move back to the left half plane, and extra power loss is not introduced; an active disturbance rejection control strategy based on virtual impedance compensation is designed, residual uncertainty after virtual impedance compensation is uniformly regarded as total disturbance online observation and feedforward offset, and therefore rapid and smooth voltage tracking is kept under parameter perturbation and external disturbance. Under the working conditions of voltage reference step and load abrupt change, the improved active disturbance rejection control strategy realizes the effects of no overshoot, shortest setting time and minimum oscillation by enhancing disturbance observation and virtual impedance compensation, and has better damping and disturbance rejection performance.

Description

Technical Field

[0001] This invention belongs to the field of dual active bridge converter control technology, specifically relating to an active disturbance rejection control method for dual active bridge converters based on virtual impedance compensation. Background Technology

[0002] Dual active bridge converters, as high-frequency isolated bidirectional DC / DC converters, are widely used in the power interfaces of various DC sources. In recent years, due to the increasing penetration of renewable energy, DC microgrid technology is emerging. Photovoltaic and energy storage batteries connected to a DC grid require only one DC / DC converter, while wind turbines connected to a DC microgrid require only one AC / DC converter. Compared to traditional AC grids, this reduces the number of power electronic converters needed, improving power transmission efficiency within the grid. Simultaneously, DC microgrids offer advantages such as simplified wiring, better adaptation to DC loads, and improved power quality and stability. In DC microgrids, dual active bridge converters serve as crucial bidirectional isolation interfaces between the DC source and the DC bus, isolating the impact of DC source faults on the DC bus while maintaining power balance within the DC microgrid. Dual active bridge converters also have important applications in aerospace power systems, electric vehicle power supply networks, and charging infrastructure.

[0003] Dual active bridge converters commonly employ constant voltage control strategies to maintain a stable DC bus voltage, thereby ensuring stable power supply to subsequent converters or loads. Traditional proportional-integral (PI) control strategies rely heavily on precise circuit parameters, such as auxiliary inductance and load size. When these parameters deviate, the system's dynamic performance deteriorates significantly. While model predictive control offers advantages over traditional PI control, such as reduced overshoot, improved dynamic response speed, and the ability to directly incorporate constraints into the optimization problem for multi-objective collaborative optimization, it still heavily relies on precise modeling and circuit parameters, resulting in poor robustness. Sliding mode control is a robust nonlinear control method that designs a reaching law to make the system state approach the sliding surface, achieving the set control objective. This control method has a simple control structure and is insensitive to system parameters and disturbances. However, due to the limitations of the controller itself, the control signal is discontinuous, and sliding mode control can produce chattering problems, causing the output voltage to oscillate at high frequencies near the given value, thus affecting system performance. In comparison, active disturbance rejection control (ADRC) is a control method with strong robustness and good dynamic steady-state performance against the system model. For example, a LADRC control method based on a DAB converter (CN114499209A) offers advantages in robustness and performance. However, this patent does not consider scenarios such as DC microgrids, aerospace power supplies, electric vehicle power supply networks, and charging infrastructure. In such systems, to meet performance targets, the downstream converter typically employs strict closed-loop control, resulting in a constant power load characteristic at the output of the upstream DC / DC converter. Since the VI characteristic curve of a constant power load has a negative slope, exhibiting negative impedance characteristics, it affects the stability of the DC / DC converter. Control strategies designed for positive impedance loads encounter insufficient stability margins, requiring improved control strategies to effectively suppress the negative impedance instability introduced by constant power loads.

[0004] Therefore, there is an urgent need for an improved control method for dual active bridge power electronic converters that is robust to circuit parameters and models, has good steady-state and dynamic performance, and can effectively suppress negative impedance instability introduced by constant power loads. Summary of the Invention

[0005] The purpose of this invention is to propose an active disturbance rejection control (ADRC) method for dual active bridge converters based on virtual impedance compensation. First, a virtual impedance compensation strategy is designed, which uses an equivalent virtual conductance in parallel with the output capacitor, converted into a duty cycle injection quantity. This achieves active cancellation of the negative impedance of a constant power load and port damping reshaping, causing unstable poles in the right half-plane to migrate back to the left half-plane without introducing additional power loss. Based on this, an ADRC strategy based on virtual impedance compensation is designed, treating the remaining uncertainty after virtual impedance compensation as a unified total disturbance observed online and fed forward to cancel it, thereby maintaining fast and smooth voltage tracking under parameter perturbations and external disturbances.

[0006] The present invention is achieved by at least one of the following technical solutions.

[0007] A method for active disturbance rejection control of a dual active bridge converter based on virtual impedance compensation includes the following steps:

[0008] S1. Establish a virtual impedance compensation strategy, which includes connecting virtual admittance in parallel across the output capacitor.

[0009] S2. By converting the virtual current corresponding to the virtual admittance into the duty cycle injection amount and superimposing it with the nominal control amount, the voltage regulation control and the suppression of the instability of the constant power load CPL are achieved.

[0010] S3. Introduce virtual admittance into the first-order total disturbance model;

[0011] S4. The first-order total disturbance model is estimated online and fed forward compensation is performed by an improved second-order extended state observer, so that the closed loop is equivalent to a single integral element and the control law is tuned according to the bandwidth method.

[0012] Furthermore, in step S1, the virtual admittance in the virtual impedance compensation strategy should be greater than the ratio of the constant power load value to the output voltage. At this time, the negative admittance introduced by the constant power load is canceled by virtual parallel admittance, and the pole of the transfer function from duty cycle to output voltage can be shifted back to the left half-plane.

[0013] Furthermore, in step S2, the virtual admittance adopts an implementation scheme based solely on output voltage measurement, that is, the voltage sampling value at the converter output terminal is used as the only input, and the voltage is multiplied by the set virtual admittance to directly obtain the corresponding virtual current.

[0014] Further, step S2 includes: proportionally converting the virtual current according to the nominal channel relationship between phase shift and secondary bridge current to obtain the converted duty cycle injection amount.

[0015] Furthermore, in step S3, the first-order total perturbation model incorporating virtual admittance becomes:

[0016]

[0017] in, Let y be the derivative of the output voltage y, w(t) represent the modeling error and interference from circuit parameters, and Y v For virtual admittance, C2 is the output capacitor, and P... CPL For a constant power load, b0 is the nominal gain, u is the duty cycle, and V... o The output voltage is indicated.

[0018] The total disturbance at this point is expressed as:

[0019]

[0020] Non-convergent terms introduced by constant power load during disturbance The virtual impedance compensation term cancels out the system's stability, and the first-order total disturbance model is rewritten as follows:

[0021]

[0022] Furthermore, the nominal gain adopts the equivalent parameter obtained from the dual active bridge average small-signal model, and is fed forward normalized with this nominal gain, so that the closed loop after disturbance observation and feedforward compensation is equivalent to a single integral element, thereby facilitating the direct tuning of the proportional element according to the bandwidth method to obtain the desired overshoot-free response.

[0023] Furthermore, the extended state observer is used to estimate online the model uncertainty, parameter drift, unmodeled dynamics, external disturbance unification, and virtual admittance compensation as a total disturbance. In this case, the state-space equation of the improved second-order extended state observer should be:

[0024]

[0025] Where z1 and z2 represent the observed values ​​of output voltage and total disturbance, respectively. Let K represent the derivatives of z1 and z2. p β1 and β2 represent the first and second order gains of the observer, respectively, and a0 represents the effect of the virtual impedance on the observer structure.

[0026] Furthermore, the control law is formed by subtracting the reference value signal from the real-time observation of the output voltage by the extended state observer as a feedback quantity to generate a control error signal.

[0027] Furthermore, the improved second-order extended state observer estimate is fed forward in the control law to offset the influence of the virtual admittance compensation, so that the compensated controlled object is approximately equivalent to a single integral element within the operating bandwidth, thereby reducing the dependence on the accurate model and simplifying bandwidth tuning.

[0028] The present invention provides a computer-readable storage medium storing a computer program, characterized in that: when the computer program is executed by a processor, the processor implements the method as described in any one of claims 1 to 9.

[0029] Compared with existing technologies, the beneficial effects of the present invention are as follows:

[0030] (1) Port damping reshaping and suppression of instability caused by constant power load. By actively compensating for the negative impedance caused by constant power load through parallel virtual admittance at the output, the equivalent damping is improved and the unstable poles are moved back to the stable region, thereby improving the stability of DC port with constant power load from the mechanism and improving dynamic performance.

[0031] (2) It can be implemented based solely on voltage measurement, with low hardware and cost overhead. The virtual admittance is calculated in real time from the output voltage to obtain the corresponding virtual current and control quantity injection, and its implementation does not depend on the output current sensor; at the same time, no parallel physical resistor is required, making it easy to deploy on existing controllers.

[0032] (3) Stronger noise immunity with observation feedback. The real-time observation of the output voltage by the extended state observer is used as feedback and the difference is calculated with the reference value. This can suppress measurement noise from entering the error loop while ensuring dynamic response. Combined with the bandwidth separation of "fast observation and slow control" (the observer bandwidth is usually about 3-10 times the controller bandwidth), the disturbance convergence speed can be further improved and the impact of sampling / computation delay can be reduced.

[0033] (4) Compatible with bidirectional power and common modulation methods, with a wide range of applications. The control method proposed in this invention can work under both forward and reverse power transmission and can be combined with common dual active bridge converter modulation strategies such as single phase shift and its extended phase shift. It can improve dynamic performance while also improving converter efficiency, and is suitable for application scenarios such as electric vehicles, energy storage and DC microgrids.

[0034] (5) It is highly practical for engineering implementation and easy to implement digitally. The proportional element and the observer can be directly tuned using the bandwidth method, and both the virtual admittance and the extended state observer can be easily implemented on the digital controller. Attached Figure Description

[0035] Figure 1 The diagram shows the topology of the dual active bridge converter in this embodiment.

[0036] Figure 2 This is a schematic diagram of a parallel virtual resistor in an embodiment.

[0037] Figure 3 This is a schematic diagram of the design method for virtual impedance compensation in an embodiment.

[0038] Figure 4 The diagram below shows the control block diagram of the improved active disturbance rejection control strategy based on virtual impedance compensation, as an example.

[0039] Figure 5 The figure shows the simulation verification results of the example. Detailed Implementation

[0040] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0041] To enable those skilled in the art to implement the present invention, a preferred embodiment of the improved active disturbance rejection control method for dual active bridge converters based on virtual impedance compensation considering constant power loads is described in detail below with reference to the accompanying drawings.

[0042] This embodiment addresses the problems of insufficient stability margin and strong controller dependence on models and parameters in dual active bridge (DAB) converters under constant power load (CPL) conditions due to negative port impedance. It proposes an active disturbance rejection control method for DAB converters based on virtual impedance compensation. This method involves voltage regulation control of DAB DC / DC converters operating under constant power load (CPL) conditions, such as in DC microgrids, to achieve high output voltage stability and fast dynamic performance in the presence of model uncertainty and external disturbances. The method includes the following steps:

[0043] Step 1: Establish a reduced-order average model of the dual active bridge converter;

[0044] Figure 1 This is a dual active bridge converter topology, with one full-bridge converter on each side of the transformer. S1-S4 form the primary bridge, and S5-S8 form the secondary bridge. DC bus capacitors C1 and C2 are connected in parallel across the primary and secondary bridges, respectively. The two full bridges are coupled through a 1:n high-frequency isolation transformer to achieve electrical isolation and step-up / step-down conversion. Power is driven by the phase difference between the square waves generated by the primary and secondary bridge arms, and then flows through the auxiliary inductor L. s transfer.

[0045] In this embodiment, the average transmission power P of the DAB converter using single-phase-shift modulation within one switching cycle is:

[0046]

[0047] Among them, V i It is the input voltage, V o For the output voltage, T hs This is half a switching cycle. Because the inductor current and bridge arm output voltage of the dual active bridge converter have half-cycle symmetry, only half a cycle needs to be analyzed to obtain the average transmission power within one switching cycle; v p (t) is the output voltage of the secondary bridge; i L (t) is the auxiliary inductor current at time t; d is the duty cycle of the dual active bridge converter; f is the switching frequency of the dual active bridge converter. f is the switching frequency, n is the transformer turns ratio, d is the relative shift ratio of the primary and secondary full bridges, when d>0, the DAB converter transmits power in the forward direction, and when d<0, the DAB converter transmits power in the reverse direction.

[0048] The converter output current is averaged over one cycle to obtain:

[0049]

[0050] Applying small-signal linearization to the above equation yields the transfer function from duty cycle to output voltage:

[0051]

[0052] Where s is the Laplace operator and D0 is the duty cycle at the steady-state operating point.

[0053] When a constant power load P is connected to the output terminal CPL At that time, the port current and voltage satisfy:

[0054]

[0055] Among them I CPL (t) represents the current at the constant power load at time t.

[0056] At the steady-state operating point (V o I o At this point, make it a smaller signal, so that get:

[0057]

[0058] Among them, v o i CPL V represents the instantaneous values ​​of the output voltage and current. o I o This indicates the steady-state operating values ​​of the output voltage and current. These represent the small disturbance components of the output voltage and current, respectively.

[0059] Therefore, as Figure 2 As shown, at the steady-state operating point (V o I o At point (), the current i of a constant power load can be approximated by a straight line tangent to the curve, including the equivalent resistance Z. CPL and equivalent controlled current source i CPL Two parts, as follows:

[0060]

[0061] Simultaneously considering the output capacitor C2 and the constant power load P CPL The output port dynamically satisfies the following differential equation:

[0062]

[0063] in, b2 > represents the average value of the converter output current over one cycle. ​

[0064] At the steady-state operating point (V o D o P CPL ) is transformed into a small signal:

[0065]

[0066] in It represents the derivative of the small disturbance component of the output voltage.

[0067] Transforming the above time-domain small-signal model to the frequency domain yields:

[0068]

[0069] Where V o D(s) and D(s) represent the frequency domain quantities of the output voltage and duty cycle.

[0070] Therefore, the transfer function from duty cycle to output voltage is:

[0071]

[0072] Wherein, the nominal gain b0 is defined as:

[0073]

[0074] Where n is the transformer turns ratio.

[0075] The transfer function has poles in the right half-plane:

[0076]

[0077] When the poles of the transfer function appear in the right half-plane, the system will become unstable.

[0078] Step 2: Design a virtual impedance compensation strategy to improve port damping and move unstable poles to the left half-plane;

[0079] To increase port damping and move the right-half-plane pole back to the left-half-plane, such as Figure 2 As shown, a virtual admittance Y is connected in parallel across the output capacitor C2. v The transfer function from duty cycle to output voltage after parallel virtual admittance is:

[0080]

[0081] Where Y v This is a virtual admittance.

[0082] At this point, the pole becomes:

[0083]

[0084] In order to move the poles back to the left half-plane, the designed parallel virtual impedance should satisfy the following condition:

[0085]

[0086] This effectively cancels out the negative admittance using a virtual parallel admittance, restoring the equivalent impedance of the port to a positive real number and satisfying the stability requirements. This method improves system stability without affecting the converter's power transfer efficiency.

[0087] Step 3: Implement the parallel virtual impedance strategy: By converting the virtual current corresponding to the virtual admittance into the duty cycle (or phase shift) injection amount and superimposing it with the nominal control amount, the voltage regulation control and the suppression of CPL instability are achieved.

[0088] Figure 3 (a) uses a block diagram to illustrate the control principle of the duty cycle as the control variable on the output voltage under the small signal average model.

[0089] To achieve parallel virtual impedance while reducing the number of sensors, this invention uses output voltage feedback to inject virtual impedance, such as... Figure 3 As shown in (b).

[0090] Flow through virtual admittance Y v Virtual current I v (s) is:

[0091] I v (s)=Y v (s)V o (s)

[0092] Since the virtual current is determined entirely by the output voltage and virtual admittance, the calculation process does not depend on any output current measurement or related data input. Therefore, there is no need to acquire output current data, and thus no need to configure an additional output current sensor or add new hardware related to output current measurement.

[0093] Convert the current into duty cycle injection amount d v (s), such as Figure 3 As shown in (c):

[0094]

[0095] Among them G φo (s) represents the nominal path relationship between the phase shift and the secondary bridge current, G φi (s)=b0C2.

[0096] The duty cycle d(s) after implementing the injected virtual impedance should be reduced by d0(s) from the original duty cycle d0(s).v (s):

[0097] d(s)=d0(s)-d v (s).

[0098] Step 4: Design an active disturbance rejection control strategy based on virtual impedance compensation.

[0099] Active disturbance rejection control (ADRC) unifies the unknown intrinsic dynamics and external disturbances of the controlled object into a total disturbance f(t). It estimates this disturbance online using an extended state observer and provides feedforward compensation, making the object approximate as a component containing only the nominal gain b0 from a closed-loop perspective. This allows it to maintain the desired tracking and robust performance even with model uncertainties and disturbances. In this embodiment, the output voltage is denoted as y, the control quantity (duty cycle) as u, and the first-order total disturbance model is as follows:

[0100]

[0101] in, Let f(t) be the derivative of y. The total disturbance f(t) includes the disturbance introduced by the constant power load. And interference w(t) such as modeling errors and changes in circuit parameters:

[0102]

[0103] This disturbance includes non-convergent terms introduced by a constant power load. It affects system stability.

[0104] Where b0 is obtained from the average model in step 1 and is used as the nominal parameter for normalization and feedforward compensation.

[0105] The traditional second-order linear extended state observer is designed as follows when observing disturbances:

[0106]

[0107] At this time, the control quantity u0 is represented as:

[0108]

[0109] Among them, z1, z2、 Let K represent the observed quantities of the output voltage and the total disturbance f(t) and their derivatives, respectively. p is the proportionality coefficient of the error signal, and r is the reference signal of the output voltage.

[0110] To facilitate engineering tuning, the first-order and second-order gains β1 and β2 of the observer are selected using the bandwidth method when the observer bandwidth is ω0:

[0111] β1=2ω0

[0112]

[0113] The first-order total perturbation model after injecting virtual impedance becomes:

[0114]

[0115] When the virtual admittance is applied in parallel, the dynamic equation of the output port should remain unaffected, therefore:

[0116]

[0117] The total disturbance at this point is expressed as:

[0118]

[0119] Non-convergent terms introduced by constant power load during disturbance The virtual impedance compensation term cancels out the error, thus improving system stability. The rewritten first-order total disturbance model is as follows:

[0120]

[0121] After ESO estimates the total disturbance and feedforwards to cancel it, the closed-loop dominant pole is placed at -ω. c At this point, the expected error dynamic is

[0122]

[0123] Where e = ry is the tracking error of the output voltage. ω represents the first derivative of the error with respect to time. c This refers to the controller bandwidth.

[0124] To ensure that the disturbance is well estimated and compensated, the system is simplified to the following single integrator:

[0125]

[0126] Connecting the above equation with the dynamic equation of the expected error, we can obtain:

[0127] K p =ω c

[0128] Therefore, the structure of the control variables and state observers needs to be modified.

[0129]

[0130] When the observer converges after good tuning, z1 approaches y and z2 approaches the total disturbance f′, and the system can satisfy the form of a single integrator.

[0131] Combining the first-order total disturbance model and the expected error dynamics, the state-space equation of the improved structure's second-order extended state observer should be:

[0132]

[0133] Where a0 represents the effect of the virtual impedance on the observer structure:

[0134]

[0135] The state matrix A corresponding to the above state-space equation is:

[0136]

[0137] As one example, if the observer's pole is set at ω0, then the characteristic equation |sI-A| should satisfy:

[0138] |sI-A|=(s+ω0) 2

[0139]

[0140] Where I represents the entity providing the evidence.

[0141] Solving for the given information, we get:

[0142] β1=2ω0+a0

[0143]

[0144] Controller bandwidth K p for:

[0145] K p =ω c

[0146] To ensure good dynamic performance, maintain the separation principle of fast observation and slow control, and improve disturbance convergence speed and noise immunity, the observer convergence speed should be faster than the controller. As an example, the observer bandwidth ω0 is taken as the controller bandwidth ω. c 3 to 10 times.

[0147] ω0=(3~10)ω c

[0148] Design controller bandwidth f c If the frequency is 1kHz, then the scaling factor K p for:

[0149] K p =ω c =2πf c =6.28e3

[0150] If the controller bandwidth is set to three times the observer bandwidth, then the observer bandwidth ω0 is:

[0151] ω0=3ω c =3 × 6.28e3 = 18.84e3

[0152] In this embodiment, the control law uses the real-time output voltage observation z1 of the extended state observer as feedback and subtracts it from the reference signal to form the control error signal. Since z1 is obtained by filtering and estimating the output and total disturbance under a set bandwidth by the extended state observer, compared to directly using the original measured voltage as feedback, it can suppress measurement noise from entering the error loop and improve the noise immunity and robustness of the closed loop. The improved second-order extended state observer estimate is fed forward in the control law to compensate for the virtual admittance compensation, making the compensated controlled object approximately equivalent to a single integral element within the operating bandwidth, thereby reducing the dependence on the accurate model and simplifying bandwidth tuning.

[0153] To verify the stability and dynamic performance of the present invention under constant power load conditions, a digital simulation platform was built to compare two representative control strategies: (1) Virtual Direct Power Control (VDPC); (2) Active Disturbance Rejection Control (ADRC) and the improved ADRC strategy described in this invention in conjunction with virtual impedance compensation. The simulation object is an isolated dual active bridge DC / DC converter, and the constant power load is realized through a controlled current source with constant power. Its negative incremental impedance characteristics are used to examine the DC port stability and damping margin.

[0154] The circuit parameters for the dual active bridge DC / DC converter are set as follows:

[0155]

[0156] The following scenario will be designed to compare the improved active disturbance rejection strategy with the unimproved active disturbance rejection strategy and PI control. The control parameters of all three control methods will be tuned under the premise that the controller bandwidth is 1kHz to ensure the scientific nature of the comparison.

[0157] (1) Load step: The constant power load suddenly changes from 1200W to 2400W.

[0158] (2) Output voltage reference value fluctuation: The voltage reference value suddenly changed from 320V to 360V.

[0159] Figure 5 (a) gives the dynamic waveforms of the three control strategies in the first scenario.

[0160] Compared with VDPC, conventional ADRC reduces overshoot from about 1.2% to about 0.03% (a decrease of about 97%), shortens dynamic recovery time from about 15ms to about 2ms (a reduction of about 86%), and significantly reduces oscillations.

[0161] Compared with conventional ADRC, the proposed improved ADRC reduces the overshoot from about 0.5% to 0%, shortens the dynamic recovery time from about 2ms to about 1.7ms (a reduction of about 15%), further suppresses oscillations, and essentially eliminates oscillations.

[0162] Figure 5 (b) shows the dynamic waveforms of the three control strategies in the second scenario.

[0163] Compared with VDPC, conventional ADRC reduces overshoot from about 2% to about 0.56% (a decrease of about 72%), shortens settling time from about 16ms to about 3ms (a reduction of about 81.25%), and significantly reduces oscillation.

[0164] Compared with conventional ADRC, the improved ADRC reduces the overshoot from about 0.56% to 0%, shortens the settling time from about 3ms to about 2.7ms (a reduction of about 10%), further suppresses oscillations, and essentially eliminates oscillations.

[0165] Therefore, the improved ADRC, by enhancing disturbance observation and virtual impedance compensation, can achieve the effects of no overshoot, shortest settling time, and minimal oscillation, and has better damping and disturbance rejection performance.

[0166] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, enabling those skilled in the art to better understand and utilize the invention.

Claims

1. A method for active disturbance rejection control of a dual active bridge converter based on virtual impedance compensation, characterized in that, Includes the following steps: S1. Establish a virtual impedance compensation strategy, which includes connecting virtual admittance in parallel across the output capacitor. S2. By converting the virtual current corresponding to the virtual admittance into the duty cycle injection amount and superimposing it with the nominal control amount, the voltage regulation control and the suppression of the instability of the constant power load CPL are achieved. S3. Introduce virtual admittance into the first-order total disturbance model; S4. The first-order total disturbance model is estimated online and fed forward compensation is performed by an improved second-order extended state observer, so that the closed loop is equivalent to a single integral element and the control law is tuned according to the bandwidth method.

2. The active disturbance rejection control method for a dual active bridge converter based on virtual impedance compensation as described in claim 1, characterized in that: In step S1, the virtual admittance in the virtual impedance compensation strategy should be greater than the ratio of the constant power load value to the output voltage. At this time, the negative admittance introduced by the constant power load is canceled by virtual parallel admittance, and the poles of the transfer function from duty cycle to output voltage can be moved back to the left half plane.

3. The active disturbance rejection control method for a dual active bridge converter based on virtual impedance compensation as described in claim 2, characterized in that: In step S2, the virtual admittance adopts an implementation scheme based solely on output voltage measurement. That is, the voltage sample value at the converter output terminal is used as the only input, and the voltage is multiplied by the set virtual admittance to directly obtain the corresponding virtual current.

4. The active disturbance rejection control method for a dual active bridge converter based on virtual impedance compensation as described in claim 3, characterized in that: Step S2 includes: proportionally converting the virtual current according to the nominal channel relationship between phase shift and secondary bridge current to obtain the converted duty cycle injection amount.

5. The active disturbance rejection control method for a dual active bridge converter based on virtual impedance compensation as described in claim 4, characterized in that: In step S3, the first-order total disturbance model with virtual admittance becomes: in, Let y be the derivative of the output voltage y, w(t) represent the modeling error and interference from circuit parameters, and Y v For virtual admittance, C2 is the output capacitor, and P... CPL For a constant power load, b0 is the nominal gain, u is the duty cycle, and V... o The output voltage is indicated. The total disturbance at this point is expressed as: Non-convergent terms introduced by constant power load during disturbance The virtual impedance compensation term cancels out the system's stability, and the first-order total disturbance model is rewritten as follows:

6. The active disturbance rejection control method for a dual active bridge converter based on virtual impedance compensation as described in claim 5, characterized in that: The nominal gain is obtained by using the equivalent parameter obtained from the dual active bridge average small-signal model, and the nominal gain is used for feedforward normalization. This makes the closed loop after disturbance observation and feedforward compensation equivalent to a single integral element, which makes it easy to directly tune the proportional element according to the bandwidth method to obtain the desired overshoot-free response.

7. The active disturbance rejection control method for a dual active bridge converter based on virtual impedance compensation as described in claim 6, characterized in that: The extended state observer is used to estimate online the model uncertainty, parameter drift, unmodeled dynamics, external disturbance unification, and virtual admittance compensation as a total disturbance. The state-space equation of the improved second-order extended state observer should then be: Where z1 and z2 represent the observed values ​​of output voltage and total disturbance, respectively. Let K represent the derivatives of z1 and z2. p β1 and β2 represent the first and second order gains of the observer, respectively, and a0 represents the effect of the virtual impedance on the observer structure.

8. The active disturbance rejection control method for a dual active bridge converter based on virtual impedance compensation as described in claim 7, characterized in that: The control law is formed by subtracting the reference value signal from the real-time observation of the output voltage by the extended state observer as a feedback quantity to generate a control error signal.

9. The active disturbance rejection control method for a dual active bridge converter based on virtual impedance compensation as described in claim 8, characterized in that: The improved second-order extended state observer estimate is fed forward in the control law to offset the effect of virtual admittance compensation, so that the compensated controlled object is approximately equivalent to a single integral element within the operating bandwidth, thereby reducing the dependence on the accurate model and simplifying bandwidth tuning.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the processor implements the method as described in any one of claims 1 to 9.

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