Chip packaging method
By employing a second solder pad made of tin and a reflow soldering chip packaging method, combined with surface mount equipment and solder mask, the problem of high cost in existing chip packaging has been solved, achieving cost reduction and improved soldering accuracy.
Patent Information
- Application Number
- CN202511658770.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-01-09
AI Technical Summary
Existing chip packaging processes are costly, mainly due to expensive equipment and complex operations, which keeps processing costs high and weakens the market competitiveness of products.
The second solder pad made of tin is used in a chip packaging method that combines reflow soldering with surface mount equipment and solder mask, which avoids the limitations of ultrasonic hot pressing and reduces equipment and labor costs.
It effectively reduces processing costs, avoids pad cracking and incomplete soldering, and improves welding accuracy and product lifespan.
Smart Images
Figure CN121311073A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to a chip packaging method. Background Technology
[0002] As a critical frequency control component in electronic devices, the assembly quality of the chip and crystal substrate in a temperature-compensated oscillator directly affects the frequency stability, reliability, and lifespan of the product. Currently, the industry commonly uses flip-chip bonding combined with ultrasonic welding to achieve electrical connection and mechanical fixation between the chip and the crystal substrate. The specific implementation process of this process is as follows: First, gold balls are welded onto the surface of the chip's pads using ultrasonic thermopressing technology through a ball-mounting machine; this process is called ball mounting. After ball mounting is completed, the flip-chip bonding machine is used to weld the ball-mounted chip to the corresponding pads of the crystal substrate using ultrasonic thermopressing, ultimately achieving the assembly and fixation of the chip and the substrate.
[0003] However, the existing assembly process described above has significant technical defects and limitations in practical applications, specifically in the following aspects: High processing costs. The core equipment required for this process is a ball-planting machine and a flipping machine, which are expensive to purchase, and subsequent maintenance, parts replacement, and other costs are also high. Furthermore, the equipment has a high operational threshold, requiring specialized technicians for debugging and maintenance, further increasing labor costs. Ultimately, this leads to a significant increase in the overall processing cost of the temperature-compensated oscillator product, weakening its market competitiveness.
[0004] Therefore, there is an urgent need for a chip packaging method to solve the above-mentioned technical problems. Summary of the Invention
[0005] The purpose of this invention is to provide a chip packaging method that aims to solve the problem of high processing costs in chip packaging in the prior art. This chip packaging method can effectively reduce processing costs.
[0006] To achieve this objective, the present invention adopts the following technical solution:
[0007] Chip packaging methods include:
[0008] A substrate structure and a second chip are provided. The substrate structure includes a base and a first chip disposed on the base. A first pad is disposed on the first chip.
[0009] A second pad is fabricated on the second chip, and the material of the second pad is tin;
[0010] A solder resist layer is provided on the first chip, and the solder resist layer is provided with a window structure, the window structure being provided corresponding to the first pad;
[0011] The second chip is mounted on the first chip using a surface mount device, and the second pad is set to correspond to the first pad.
[0012] In some possible implementations, the second pad has a first shape and a second shape, wherein the first shape is a columnar structure and the second shape is a spherical structure. Fabrication of the second pad on the second chip includes:
[0013] The second pad, which has the columnar structure, is fabricated on the second chip;
[0014] The second pad is fused from the columnar structure into the spherical structure using a reflow soldering process.
[0015] In some possible implementations, the second pad, which has the columnar structure, is prepared on the second chip by an electroplating process.
[0016] In some possible implementations, the diameter of the columnar structure is d2, and the diameter of the spherical structure is d4, where d4 = (0.7-0.9)d2.
[0017] In some possible implementations, the electroplating temperature is 18°C-32°C, and the current density is 1.5 A / dm³. 2 -3A / dm 2 .
[0018] In some possible implementations, during the electroplating process, a filter element is used to filter the electroplating solution. The filter element is made of polypropylene and has a mesh diameter of d1, where d1 ≤ 7 μm.
[0019] In some possible implementations, when the second chip is mounted onto the first chip using a surface mount device, the mounting pressure is F, which ranges from 0.5N to 2.5N, and the mounting speed is v, which ranges from 20,000 CPH to 60,000 CPH.
[0020] In some possible implementations, after the second chip is mounted onto the first chip using a surface mount device, and the second pad is correspondingly set with the first pad, the method further includes:
[0021] The second pad is soldered to the first pad using a reflow soldering process.
[0022] In some possible implementations, when the second pad is soldered to the first pad using a reflow soldering process, the reflow soldering temperature is T, and the range of T is 235℃-260℃.
[0023] In some possible implementations, the surface of the first chip needs to be cleaned before the solder mask layer is applied to the first chip.
[0024] The beneficial effects of this invention are:
[0025] The chip packaging method provided by this invention uses tin as the material for the second pad. Tin is inexpensive, and the tin-based second pad is typically soldered to the second chip using reflow soldering. Compared with the existing method of using ultrasonic thermocompression to solder gold balls, this method avoids the second pad cracking caused by ultrasonic thermocompression and eliminates the need for a ball-mounting machine, effectively reducing the processing cost of the second pad. The second chip is mounted to the first chip using a surface mount device, with the second pad corresponding to the first pad. Compared with the existing method of using a flip chip to connect the second chip and the first chip, this method effectively reduces processing costs. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the structure of the second chip provided in an embodiment of the present invention;
[0027] Figure 2 This is a schematic diagram of the assembly structure of the base and the first chip provided in an embodiment of the present invention;
[0028] Figure 3 This is a top view of the chip packaging structure provided in an embodiment of the present invention;
[0029] Figure 4 This is an assembly perspective view of the base and solder mask layer provided in an embodiment of the present invention;
[0030] Figure 5 This is a schematic flowchart of the chip packaging method provided in an embodiment of the present invention.
[0031] In the picture:
[0032] 100, Base; 110, Third pad; 200, First chip; 210, First pad; 300, Solder mask; 400, Second chip; 410, Second pad. Detailed Implementation
[0033] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.
[0034] In the description of this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection or a detachable connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0035] In the description of this invention, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0036] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0037] like Figures 1 to 5 As shown, the present invention provides a chip packaging method, comprising the following steps:
[0038] S1. A substrate structure and a second chip 400 are provided. The substrate structure includes a base 100 and a first chip 200 disposed on the base 100. A first pad 210 is disposed on the first chip 200.
[0039] It is easy to imagine that the second chip 400 could also be other base or substrate structures.
[0040] S2. Prepare a second pad 410 on the second chip 400. The material of the second pad 410 is tin.
[0041] S3. A solder resist layer 300 is provided on the first chip 200. The solder resist layer 300 is provided with a window structure, and the window structure is provided in correspondence with the first pad 210.
[0042] S4. Use a surface mount device to mount the second chip 400 onto the first chip 200, and set the second pad 410 to correspond to the first pad 210.
[0043] The chip packaging method provided in this embodiment uses tin as the material for the second pad 410. Tin is inexpensive, and the tin-based second pad 410 is typically reflow soldered to the second chip 400. Compared to the existing method of using ultrasonic thermocompression to solder gold balls, this avoids the second pad 410 from cracking due to ultrasonic thermocompression and eliminates the need for a ball-mounting machine, effectively reducing the processing cost of the second pad 410. The second chip 400 is mounted to the first chip 200 using a surface mount device, with the second pad 410 corresponding to the first pad 210. Compared to the existing method of using a flip chip to connect the second chip 400 and the first chip 200, this method effectively reduces processing costs. It is conceivable that steps S2 and S3 can be adjusted as needed. For example, step S2 can be completed first, followed by step S3, or vice versa. It is understandable that when the second chip 400 is a different base or substrate structure, multiple second pads 410 are disposed on the other base or substrate structure. The other base or substrate structure is mounted to the first pad 210 on the first chip 200 through the second pads 410, thereby realizing the encapsulation of the other base or substrate structure and the chip.
[0044] Optionally, the second pad 410 has a first shape and a second shape, the first shape being a columnar structure and the second shape being a spherical structure. Step S2 includes:
[0045] S21. A second pad 410 with a columnar structure is prepared on the second chip 400;
[0046] S22. Through the reflow soldering process, the second pad 410 is melted from a columnar structure into a spherical structure.
[0047] The second pad 410 is mounted to the first pad 210 in a spherical structure. After the spherical second pad 410 is heated and melted, the surface tension of the second pad 410 allows the solder to naturally form a rounded solder joint, which is evenly filled in the window structure, avoiding local accumulation or gaps. The spherical second pad 410 has no sharp edges, which can automatically correct minor offsets and quickly achieve precise alignment with the window structure. The spherical structure can evenly distribute welding stress and thermal stress to the contact interface with the first pad 210, avoiding local stress concentration that could lead to cracking of the welding surface.
[0048] In addition, the second pad 410 is first connected to the second chip 400 in a columnar structure, which can increase the connection area with the second chip 400; the transition from columnar structure to spherical structure makes it easier to control the volume of the spherical structure.
[0049] In this embodiment, a second pad 410 with a columnar structure is prepared on the second chip 400 by an electroplating process. Using an electroplating process to prepare the second pad 410 with a columnar structure allows for more precise control of the columnar structure diameter; the electroplated layer has good thickness uniformity; the second pad 410 has fewer defects, a dense surface, strong oxidation and corrosion resistance, and high forming quality.
[0050] Optionally, during electroplating, the electroplating temperature is 18℃-32℃, and the current density is 1.5A / dm³. 2 -3A / dm 2 Excessively high electroplating temperature leads to a rapid deposition rate, resulting in coarse crystals in the plating layer and affecting the surface smoothness of the second pad 410. Conversely, excessively low electroplating temperature causes slow tin ion diffusion, resulting in uneven plating thickness and edge burrs. At lower current densities, tin ions have sufficient time for orderly deposition, resulting in a fine, smooth plating layer. At higher current densities, the ion deposition rate exceeds the diffusion rate, leading to defects such as roughness, porosity, and scorching in the plating layer. Internal stress is also more likely to remain, making it prone to bubble formation when melting into a spherical structure. Setting the electroplating temperature to 18℃-32℃ and the current density to 1.5A / dm³ is recommended. 2 -3A / dm 2 This ensures the stability of the plating solution. When multiple second pads 410 are set, the diameter and height of the multiple columnar structures are made uniform.
[0051] Preferably, during the electroplating process, a filter element is used to filter the electroplating solution. The filter element is made of polypropylene, and the mesh diameter of the filter element is d1, where d1 ≤ 7 μm. By setting d1 ≤ 7 μm, tiny impurities such as metal oxide particles, dust, and additive decomposition residues in the electroplating solution can be precisely filtered, preventing impurities from embedding into the electroplating layer and forming pinholes or pits. This ensures the smoothness of the second solder pad 410 surface and improves solder wettability. Polypropylene has strong chemical stability, resists the corrosion of the electroplating solution, and does not react with the electroplating solution, avoiding contamination of the electroplating solution or degradation that generates new impurities, ensuring long-term stable filtration performance. In other embodiments, when using the filter element to filter the electroplating solution, the electroplating solution can be stirred simultaneously to increase the liquid turnover rate on the filter element surface and prevent impurities from accumulating and clogging the filter element pores.
[0052] Optionally, the diameter of the columnar structure is d2, and the diameter of the spherical structure is d4, where d4 = (0.7-0.9)d2. If the diameter of d4 is too large relative to d2, the fit between the second pad 410 of the spherical structure and the window structure will be poor, reducing the soldering accuracy. In addition, when the second pad 410 melts from the first state to the second state, it consumes more energy, increasing the processing cost. If the diameter of d4 is too small relative to d2, it may result in a large gap between the second pad 410 of the spherical structure and the window structure. During the soldering process, the diffusion of solder will cause the height of the second pad 410 to be too low, resulting in poor soldering or cold solder joints between the second pad 410 and the first pad 210, reducing the production yield.
[0053] Optionally, when mounting the second chip 400 onto the first chip 200 using a surface mount device, the mounting pressure is F, ranging from 0.5N to 2.5N, and the mounting speed is v, ranging from 20,000 CPH to 60,000 CPH. Insufficient mounting pressure will result in poor contact between the first pad 210 and the second pad 410, making them prone to displacement during transport or heating; excessive mounting pressure may damage the first pad 210; excessive mounting speed will cause impact, resulting in uneven force on the first pad 210 and the second pad 410 upon contact, easily leading to tilting or bouncing; excessive mounting speed may cause the first pad 210 and the second pad 410 to be exposed to air for a long time, accelerating surface oxidation and affecting subsequent soldering wettability. By setting F to a range of 0.5N-2.5N and v to a range of 20000CPH-60000CPH, the first pad 210 and the second pad 410 can be precisely aligned, avoiding misalignment, while also achieving a certain level of mounting efficiency.
[0054] Optionally, after mounting the second chip 400 onto the first chip 200 using a surface mount device, and setting the second pad 410 to correspond with the first pad 210, the method further includes:
[0055] S5. The second pad 410 is soldered to the first pad 210 by reflow soldering.
[0056] The reflow soldering process melts the first pad 210 and the second pad 410, connecting the two pads and improving the bonding strength. This process can withstand environmental influences such as temperature cycling and vibration, reducing the risk of cracking and detachment, and significantly extending the product's service life.
[0057] Optionally, when welding the second pad 410 to the first pad 210 using a reflow soldering process, the reflow soldering temperature is T, which ranges from 235℃ to 260℃. If the reflow soldering temperature is too low, the second pad 410 and the first pad 210 cannot completely melt, only softening on the surface or partially melting, failing to form a continuous alloy layer, resulting in a cold solder joint. Furthermore, the molten solder has poor fluidity, easily leaving air behind and forming voids, resulting in extremely low mechanical strength of the solder joint, making it prone to cracking and detachment under vibration and temperature cycling. If the reflow soldering temperature is too high, the solder melts excessively, becoming too fluid and easily overflowing the window structure, forming bridges with adjacent pads, causing short circuits, and directly leading to product malfunction. By setting T within the range of 235℃-260℃, the solder completely melts with moderate fluidity, forming rounded and dense solder joints. Simultaneously, the weld layer has high mechanical strength, improving the product's impact resistance and aging resistance.
[0058] In this embodiment, before the solder resist layer 300 is applied to the first chip 200, the surface of the first chip 200 needs to be cleaned to remove contaminants such as oil, fingerprints, and dust from the surface of the first chip 200. These impurities will form an isolation layer, causing the solder resist layer 300 to not adhere tightly to the first chip 200. After cleaning, the solder resist layer 300 and the first chip 200 can form a firm connection, avoiding cracking or falling off caused by subsequent high temperature or environmental changes.
[0059] In this embodiment, a plurality of third pads 110 are provided on the base 100, and the plurality of third pads 110 surround the periphery of the first chip 200. The third pads 110 can be used to connect to external components, or can also be used to connect to the first chip 200 or the second chip 400; the plurality of third pads 110 surrounding the periphery of the first chip 200 form multi-point welding with the corresponding pads of the first chip 200 or the second chip 400, increasing the connection contact area, reducing the risk of single solder joint failure, and ensuring continuous and stable electrical connection; the periphery distribution can match the circumferential signal pin layout of the first chip 200 or the second chip 400, shortening the signal transmission path, reducing delay and interference, and ensuring the frequency accuracy and signal integrity of the temperature compensation oscillator.
[0060] like Figure 4 As shown, in this embodiment, a groove for accommodating the first chip 200 is provided on the base 100, and a plurality of third pads 110 are provided on the surface of the groove and surround the periphery of the groove. The groove can improve the mounting stability of the first chip 200.
[0061] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. A chip packaging method, characterized in that, include: A substrate structure and a second chip (400) are provided. The substrate structure includes a base (100) and a first chip (200) disposed on the base (100). A first pad (210) is disposed on the first chip (200). A second pad (410) is prepared on the second chip (400), and the material of the second pad (410) is tin; A solder resist layer (300) is provided on the first chip (200), and the solder resist layer (300) is provided with a window structure, and the window structure is provided corresponding to the first pad (210); The second chip (400) is mounted on the first chip (200) using a surface mount device, and the second pad (410) is set to correspond to the first pad (210).
2. The chip packaging method according to claim 1, characterized in that, The second pad (410) has a first shape and a second shape, wherein the first shape is a columnar structure and the second shape is a spherical structure. Fabrication of the second pad (410) on the second chip (400) includes: The second pad (410) is fabricated in the columnar structure on the second chip (400); The second pad (410) is fused from the columnar structure into the spherical structure by a reflow soldering process.
3. The chip packaging method according to claim 2, characterized in that, The second pad (410) having the columnar structure is prepared on the second chip (400) by an electroplating process.
4. The chip packaging method according to claim 2, characterized in that, The diameter of the columnar structure is d2, and the diameter of the spherical structure is d4, where d4 = (0.7 - 0.9)d2.
5. The chip packaging method according to claim 3, characterized in that, During electroplating, the plating temperature is 18℃-32℃, and the current density is 1.5A / dm³. 2 -3A / dm 2 .
6. The chip packaging method according to claim 3, characterized in that, During the electroplating process, a filter element is used to filter the electroplating solution. The filter element is made of polypropylene and has a mesh diameter of d1, where d1 ≤ 7 μm.
7. The chip packaging method according to claim 1, characterized in that, When the second chip (400) is mounted on the first chip (200) using a chip mounting device, the mounting pressure is F, which ranges from 0.5N to 2.5N, and the mounting speed is v, which ranges from 20000CPH to 60000CPH.
8. The chip packaging method according to claim 1, characterized in that, After the second chip (400) is mounted on the first chip (200) using a surface mount device, and the second pad (410) is correspondingly set with the first pad (210), the process further includes: The second pad (410) is soldered to the first pad (210) by a reflow soldering process.
9. The chip packaging method according to claim 8, characterized in that, When the second pad (410) is soldered to the first pad (210) by reflow soldering, the reflow soldering temperature is T, and the range of T is 235℃-260℃.
10. The chip packaging method according to claim 1, characterized in that, Before the solder resist layer (300) is applied to the first chip (200), the surface of the first chip (200) needs to be cleaned.