Power supply integrity repairing method and device and storage medium

Abstract

The invention discloses a power supply integrity repairing method and device and a storage medium, and belongs to the technical field of semiconductors, and the power supply integrity repairing method comprises the steps: obtaining layout power supply distribution network data, executing voltage drop analysis and electromigration analysis, and generating voltage drop distribution data and electromigration hotspot data; identifying an intersection region which conforms to the minimum punching rule and is associated with the voltage drop difference value and the electromigration value in the adjacent metal layers as a candidate punching region; for each candidate region, calculating the maximum number of through holes based on a voltage drop difference value when the region has no through hole, and calculating the maximum number of through holes based on an electromigration value when the region has the through hole; and executing a through hole adding operation according to a calculation result, and generating optimized layout data. The number of the through holes is dynamically determined through collaborative analysis of voltage drop and electromigration, the influence of parasitic parameters can be reduced while the integrity of the power supply is improved, the process reliability is ensured, the antenna effect is prevented, and comprehensive optimization of the power supply network is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a power integrity repair method and device and storage medium. BACKGROUND

[0002] At present, most integrated circuit designs adopt automatic punching optimization technology, which automatically adds vias in the metal layer intersection area of the power network through computer-aided design software, but there are three defects: first, a large number of redundant vias will be blindly generated, introducing unnecessary parasitic capacitance; second, high via density will cause etching process defects (such as bridging or incomplete etching); third, the accumulation of via charges will aggravate the antenna effect, which will cause the increase of chip power consumption, the decrease of yield and the risk of reliability, and the existing solutions (such as manual inspection or fixed rule constraints) cannot effectively avoid the problem of redundant holes while ensuring the integrity of the power supply. SUMMARY

[0003] The present application provides a power integrity repair method, device and storage medium, aiming to solve the problems of increased parasitic capacitance, process defects and antenna effect caused by redundant holes in the punching technology.

[0004] In a first aspect, a power integrity repair method is provided, comprising:

[0005] Obtaining power distribution network data in a layout;

[0006] Performing voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data containing voltage drop difference values of each region and electromigration hotspot data labeled with electromigration values;

[0007] Identifying, from the power distribution network data, intersection regions in adjacent metal layers that meet a preset minimum punching rule and have associated voltage drop difference values and electromigration values as candidate punching regions;

[0008] For each candidate punching region, determining a punching rule according to the voltage drop difference value and the electromigration value, the punching rule being that when the candidate punching region has no via, calculating the maximum number of vias according to the voltage drop difference value; when the candidate punching region already has a via, calculating the maximum number of vias according to the electromigration value;

[0009] Performing a via adding operation according to the maximum number of vias to generate optimized layout data

[0010] In a second aspect, a power integrity repair device is also provided, comprising:

[0011] A data acquisition module configured to obtain power distribution network data in a layout;

[0012] The analysis module is configured to perform voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data containing voltage drop difference values of each region and electromigration hotspot data labeled with electromigration values.

[0013] The candidate region identification module is configured to identify, from the power distribution network data, an intersection region in adjacent metal layers as a candidate punching region, which meets a preset minimum punching rule and has associated voltage drop difference values and electromigration values.

[0014] The punching rule determination module is configured to determine, for each candidate punching region, a punching rule according to the voltage drop difference values and the electromigration values, wherein when the candidate punching region has no via hole, the maximum number of via holes is calculated according to the voltage drop difference values; and when the candidate punching region already has a via hole, the maximum number of via holes is calculated according to the electromigration values.

[0015] The via hole optimization module is configured to perform a via hole adding operation according to the maximum number of via holes to generate optimized layout data.

[0016] In a third aspect, a computer readable storage medium is provided, which stores a computer program. The computer program is loaded by a processor to perform the steps of the power integrity repair method of any one of the first aspect.

[0017] Advantages:

[0018] The present application effectively solves the technical problems caused by blind via hole addition in traditional power network repair through intelligent dynamic punching rules. First, the maximum number of via holes for each candidate region is dynamically determined according to the voltage drop difference values and the electromigration values, avoiding blind via hole addition based on experience and fundamentally eliminating the problem of increased parasitic capacitance caused by redundant via holes. Second, by identifying candidate regions that meet the preset minimum punching rule and have associated electrical parameters, the newly added via holes are located in sensitive electrical performance areas, avoiding process risks caused by punching in unnecessary locations. Finally, for regions without via holes, the number of via holes is calculated based on the voltage drop difference values to ensure the necessity of via hole addition. For regions with existing via holes, the number of newly added via holes is calculated according to the electromigration values to prevent local current density from exceeding the standard. The dual constraint mechanism effectively controls the via hole density and reduces the occurrence rate of antenna effect. Moreover, the preset minimum punching rule already includes process design rules (such as minimum spacing, size, etc.), so that the generated via hole layout meets the manufacturing process requirements and avoids process defects caused by improper design.

[0019] Therefore, the present application dynamically determines the number of via holes through the cooperative analysis of voltage drop and electromigration, which not only improves the power integrity but also reduces the influence of parasitic parameters, ensures process reliability, and prevents antenna effect, achieving comprehensive optimization of the power network. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0021] Figure 1 is a flow diagram of the power integrity repair method provided by some embodiments of the present application;

[0022] Figure 2 is a schematic diagram of determining the punching rule provided by some embodiments of the present application;

[0023] Figure 3 is a schematic diagram of the punching scheme provided by the prior art;

[0024] Figure 4 is one of the schematic diagrams of the punching scheme provided by the present application;

[0025] Figure 5 is the second schematic diagram of the punching scheme provided by the present application;

[0026] Figure 6 is a structural block diagram of the power integrity repair device provided by some embodiments of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely in the following description with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the scope of protection of the present application.

[0028] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are intended to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description of the present application and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise expressly specified.

[0029] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0030] The use of "adapted to" or "configured to" in the present application means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps. In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0031] In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation described as "exemplary" in the present application is not necessarily to be construed as preferred or advantageous over other implementations. The following description is presented to enable any person skilled in the art to make and use the present application. In the following description, for the purposes of explanation, details are set forth in order to provide a thorough understanding of the application. It should be apparent to those skilled in the art that the application can be practiced without the specific details presented below. In other instances, well-known structures and processes are not described in detail in order to avoid obscuring the application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features presented herein.

[0032] In the integrated circuit power integrity design, via is a key technology to connect different metal layer power network, which importance mainly reflects in three aspects: first, via can effectively reduce the parasitic resistance of power distribution network, through multi-level parallel conduction to reduce IR Drop (ΔV = I x R), so that the transistor obtains stable power supply voltage; second, reasonable via layout can balance the current distribution, avoid the electromigration (EM) effect caused by local current density too high, and improve the chip reliability; finally, via realizes the three-dimensional interconnection optimization of power network, and constructs low impedance power supply path under limited wiring resources. However, the traditional indiscriminate via will cause the problem of redundant holes, which will increase the parasitic capacitance, worsen the antenna effect and cause process defects (such as incomplete etching).

[0033] Based on this, the optimal via number is dynamically determined through voltage drop and electromigration analysis, that is, the via rule driven by electrical characteristics is used to replace the traditional empirical via, which can reduce the influence of parasitic parameters, ensure process reliability and prevent antenna effect, and realize the comprehensive optimization of power network while improving power integrity.

[0034] In one aspect, the embodiment provides a power integrity repair method, as shown in Figure 1 , comprising:

[0035] S101: Obtain power distribution network data in the layout.

[0036] It can be understood that the power distribution network data refers to the geometric and electrical parameters of the power network (PDN) extracted from the integrated circuit layout design system, specifically including: 1) physical structure data: layout geometric information such as metal layer interconnection topology, power / ground line width and spacing, existing via position and size. 2) Electrical characteristic data: parasitic resistance (R) parameters and parasitic capacitance (C) parameters extracted based on process files (such as interconnection process technology format file ITF / library exchange format file LEF); 3) Design constraint data: process minimum via rule (such as minimum via size, spacing), metal layer stacking relationship and other manufacturing constraint conditions.

[0037] S102: Perform voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data containing voltage drop difference values of each region and electromigration hotspot data labeled with electromigration values.

[0038] Exemplarily, step S102 comprises: extracting parasitic resistance parameters and parasitic capacitance parameters of metal interconnections in the layout; performing power distribution network simulation based on the parasitic resistance parameters and the parasitic capacitance parameters, to obtain voltage values and current density values of all electrical nodes; defining a difference between the voltage values and a preset nominal power voltage value as a voltage drop difference value, and generating the voltage drop distribution data by spatial interpolation; converting the current density values into electromigration values, and marking electrical nodes that exceed a maximum process allowed electromigration value as electromigration hotspots, to form the electromigration hotspot data. The voltage drop distribution data and the electromigration hotspot data are used for subsequent identification of candidate punch regions.

[0039] It can be understood that the voltage drop (IR Drop) and electromigration (EM) analysis of step S102 refers to quantitative evaluation of the power network by the following process: first, the parasitic resistance (R) and parasitic capacitance (C) parameters of metal interconnections are extracted from the layout (based on the ITF / LEF process file) and input into simulation tools such as Ansys Totem or Cadence Voltus_FI; second, power distribution network (PDN) simulation is performed under the condition of applying working current and nominal voltage (such as VDD=1.2V), to generate voltage values (V_actual) and current density (J) of all electrical nodes in the whole chip; third, the difference δV=V_nominal-V_actual between the voltage of each electrical node and the nominal value is calculated, and the voltage drop distribution heat map of the whole domain is formed by spatial interpolation technology (such as Kriging algorithm), to generate the voltage drop distribution data.

[0040] At the same time, the current density value J of each node is obtained by power distribution network simulation; when the node current density exceeds the maximum value allowed by the process (J>J_max, such as J_max=1mA / μm 2 ), the node is marked as an electromigration hotspot; the current density exceeding rate of the electromigration hotspot (EM=(J-J_max) / J_max×100%) is taken as the electromigration value, and the hotspot coordinates and EM value are recorded, to form the structured electromigration hotspot data. The structured data (δV distribution and EM hotspot coordinates) output in this step provides a decision basis for subsequent punching, so as to realize accurate positioning of the power network problem, avoid the risk of missed detection in traditional manual inspection, and replace empirical rules with quantitative simulation.

[0041] S103: identifying, from the power distribution network data, an intersection region in adjacent metal layers that meets a preset minimum punch rule and has associated voltage drop difference value and electromigration value as a candidate punch region.

[0042] Exemplarily, the step S103 comprises: judging whether the intersection region between the metal layers belongs to the overlapping region of the same electrical node; judging whether the area of the overlapping region meets the process minimum via size requirement; judging whether the distance between the overlapping region and the existing via meets the design rule requirement; when all the judgments are positive results, the intersection region is determined as the candidate via region.

[0043] It should be noted that the intersection region meeting all conditions as the candidate via region means that the following three conditions are met simultaneously: 1) electrical node consistency condition. Detect the overlapping region (such as Metal 1 and Metal 2 are connected to the same power network VDD at the layout coordinates (x, y)) belonging to the same electrical node in the adjacent metal layers. Exclude the overlapping region of different electrical nodes (such as the intersection region of VDD and GND). 2) Process manufacturability condition. Exclude the region with an overlapping area less than the preset minimum via size (for example, the process rule requires that the via size is greater than or equal to 0.1 μm x 0.1 μm, and the overlapping area needs to be greater than or equal to 0.01 μm 2 ). Avoid the via that cannot be manufactured according to the design rule due to insufficient area. 3) Design rule compliance condition. Verify whether the distance between the remaining region and the existing via meets the preset design rule (such as the via distance needs to be greater than or equal to 0.05 μm, and the distance between the via and the metal edge needs to be greater than or equal to 0.03 μm). Prevent short circuit or reliability problems caused by distance violation.

[0044] It can be understood that the candidate via region identification of step S103 is a key step for accurate positioning through multi-dimensional condition screening: first, based on a physical verification tool such as Calibre, the geometric overlapping region (i.e. the electrical connection region) belonging to the same power node (such as net 1, and net 2 is other metal structure) in the adjacent metal layers (such as Figure 2 The adjacent metal layers are yellow metal layers and blue metal layers, and the geometric overlapping region (i.e. the electrical connection region) belonging to the same power node (such as net 1, and net 2 is other metal structure) in the adjacent metal layers (such as Figure 2The red diagonal region is shown. For example, a certain candidate region needs to satisfy δV>0.3%VDD and EM>80%J_max. This step replaces the traditional indiscriminate punching through a triple screening mechanism (electrical connectivity→process size→spacing rule) to avoid the problem of redundant holes from the source and make the newly added through holes act on the IR Drop / EM problem area accurately.

[0045] S104: For each candidate punching region, determine a punching rule according to the voltage drop difference value and the electromigration value, the punching rule being that when the candidate punching region has no through hole, the maximum number of through holes is calculated according to the voltage drop difference value; when the candidate punching region already has a through hole, the maximum number of through holes is calculated according to the electromigration value.

[0046] Exemplarily, step S104 includes: for a through hole-free region, multiplying the ratio of the voltage drop difference value to a preset voltage drop safety threshold value by a preset process correction coefficient to obtain the maximum number of through holes; for a through hole region, multiplying the ratio of the measured electromigration value to a preset electromigration threshold value by a preset electromigration correction coefficient to obtain the maximum number of through holes; wherein the maximum number of through holes is not less than the minimum number of through holes required by the process. The punching rule is used to guide the subsequent through hole adding operation.

[0047] It can be understood that the dynamic punching rule proposed in step S104 is to distinguish the initial state of the candidate region (with or without through hole) and adopt a differentiated calculation strategy:

[0048] 1) IR Drop strategy for through hole-free regions. By quantifying the voltage drop difference δV of adjacent metal layers (such as Layer M2=1.18V vs Layer M3=1.15V→δV=|1.18V-1.15V|=30mV) and the process set voltage drop safety threshold Threshold_V (if the design VDD=1.2V, Threshold_V is set to 0.5% VDD, then Threshold_V=1.2V×0.5%=6mV), the through hole demand basis is calculated according to the proportional relationship, and then multiplied by the process correction coefficient k_v (such as k_v is set to 1.2-1.5, which is used to compensate for the yield influence of photolithography on multiple hole arrays). For example, when δV / Threshold_V=30mV / 6mV=5 and k_v=1.3, 6.5 (rounded up to 7) through holes are generated, and the final determined maximum number of through holes needs to meet the minimum number of through holes required in the design rule manual (DRM). For example, TSMC 7nm process, its metal interconnection layer design rule clearly requires that any effective connection must contain at least 2 through holes (i.e. N_min≥2).

[0049] 2) EM strategy for existing via region. First, extract the electromigration value (EM) of the current via in this candidate region. The electromigration value (EM) is the current density overage rate obtained by power network simulation (formula: EM = (J_measured - J_max) / J_max x 100%), where J_max is the maximum allowed current density defined in the process file (such as 1 mA / μm 2 ). Second, perform a ratio operation (i.e. EM / Threshold_EM) on the electromigration value (EM) and the preset electromigration threshold value (Threshold_EM, such as 100%) to quantify the severity of the current electromigration risk. For example, if EM = 150%, the ratio is 150% / 100% = 1.5; if EM = 80%, the ratio is 80% / 100% = 0.8. Finally, multiply the above ratio by the electromigration correction coefficient k_em (which is determined by process reliability requirements, such as k_em ≥ 1) to obtain the theoretical maximum number of vias. At the same time, it also needs to meet the process minimum via number constraint (such as the design rule manual requires at least 2 vias per μm 2 ), to avoid violating the hole spacing.

[0050] For example, assuming a candidate region: measured EM = 120%, Threshold_EM = 100%, k_em = 1.2, and the process requires a minimum number of vias N_min = 3; then:

[0051] Theoretical value: 1.2 x (120% / 100%) = 1.44, rounded up to 2;

[0052] Final value: max(2, 3) = 3 (satisfies the minimum process requirement).

[0053] Therefore, the function of step S104 is to intelligently calculate the number of holes for the no-via region according to the IR Drop (voltage drop difference), and dynamically adjust the number of holes for the via region according to the electromigration (EM) risk to avoid redundant holes; by controlling the upper limit of the number of holes through the ratio of the voltage drop threshold and the EM threshold, while forcibly meeting the process minimum via number requirement, both performance and reliability are considered; and by automatically calculating through the formula rule (such as no-hole formula: k_v*deltaV / Threshold_V, and hole formula: k_em*EM / Threshold_EM), replacing manual experience judgment, the number of design iterations is reduced.

[0054] S105: Perform a via addition operation according to the maximum number of vias to generate optimized layout data.

[0055] Exemplarily, the step S105 comprises: when the calculated maximum via number is lower than the minimum via number required by the process, adding after scaling the via size proportionally; when the calculated maximum via number is not lower than the minimum via number required by the process, adding by using the standard via size and pitch; and generating the optimized layout data after performing the via adding operation. The optimized layout data is used for subsequent design rule checking and electrical rule checking.

[0056] It can be understood that the step S105 is to perform intelligent via adding based on the dynamically calculated maximum via number. If the calculated value is lower than the minimum number of the process (for example, the design rule requires at least 2 holes per region), the number is made to meet the requirement by proportionally reducing the via size (for example, reducing the diameter by 20%), so as to avoid violating the design rule. When the calculated value meets or exceeds the minimum number, the standard via size and pitch defined by the process library (for example, 0.1 μm diameter and 0.2 μm pitch) are directly used for adding, so that the connection reliability is ensured. Through the size elastic adjustment, the IR Drop / EM repair requirements are accurately matched while meeting the process constraints, and the redundancy or insufficient problem caused by the “fixed size punching” in the prior art is avoided.

[0057] That is, the via adding is performed according to the dynamically calculated maximum via number (N_max), which is divided into two scenarios: when N_max

[0058] For example, it is assumed that N_max=1 is calculated (because EM=80%, Threshold_EM=100%, k_em=1.2→0.96 is rounded), and N_min=2 is required by the process (at least 2 vias per μm 2 For example, it is assumed that N_max=1 is calculated (because EM=80%, Threshold_EM=100%, k_em=1.2→0.96 is rounded), and N_min=2 is required by the process (at least 2 vias per μm

[0059] For example, it is assumed that N_max=4 is calculated (because δV=2%, Threshold_V=0.5%, k_v=1.0→4.0 is rounded), and N_min=2 is required by the process; and the standard via parameters are: D=0.1 μm and P=0.2 μm. Then, 4 vias are added according to the standard rule (with a pitch of 0.2 μm) in the intersection region. The maximum current path is realized, the voltage drop problem is alleviated, and no redundant hole is introduced.

[0060] In some embodiments, the power integrity restoration method further includes: after performing a via addition operation, performing a design rule check to verify whether the via spacing and the distance between the via and the metal edge meet process requirements; and performing an electrical rule check to verify whether the via current density and the metal line current density exceed the process upper limit; when violations are found, for violations of the design rule check, maintaining the original number of vias and adjusting the position of the violating vias to meet the minimum spacing requirements; for violations of the electrical rule check, increasing the number of vias or increasing the width of the connecting metal lines to reduce the current density below the safety threshold; the results of the design rule check and the electrical rule check are used to update the optimized layout data to make it meet process requirements and electrical safety standards. The check results are used to update the optimized layout data so that the power integrity restoration meets design requirements.

[0061] Understandably, after adding dynamic vias, a dual verification process is performed: 1) Design Rule Check (DRC). Verify that the via spacing (Via-to-Via) and via-to-metal distance (Via-to-Metal) comply with the process documentation (e.g., TSMCN28 DRC Rule). If violations are found, adjust the non-compliant vias by position shifting (keeping the total number unchanged) to avoid etching defects; 2) Electrical Rule Check (ERC). Detect whether the via / metal line current density exceeds the limit (e.g., >1mA / μm). 2 If the current density is exceeded, the number of through holes or the metal wires can be increased to reduce the current density.

[0062] In other embodiments, the power integrity repair method further includes: establishing a layout change record table to record via coordinates, dimensions, change types, and their corresponding voltage drop improvement rates and electromigration risk levels; the layout change record table is used as reference data for subsequent iterative optimization.

[0063] Understandably, by establishing a structured layout change log table, the technical parameters and optimization effects of each via operation can be fully tracked. For example, the log content includes: 1) Geometric attributes: via coordinates (e.g., (X,Y)=(10.2μm,5.7μm)), dimensions (e.g., diameter 0.1μm→0.07μm); 2) Change type: distinguishing between addition, scaling, or shift operations; 3) Performance indicators: quantifying voltage drop improvement rate (e.g., IR Drop reduced by 35%) and electromigration risk level (e.g., EM from high→medium). This enables traceable optimization, guiding subsequent via drilling strategies through historical data; and it also verifies the effectiveness of the k_v / k_em correction coefficient (e.g., if the log table shows that the EM risk still exceeds the limit when k_em=1.2 in a certain area, then it will be adjusted to 1.5 in the next iteration).

[0064] In some other specific examples, the power integrity repair method further includes: after performing the via addition operation, re-performing voltage drop analysis and electromigration analysis on the power distribution network data; when the analysis results do not meet the preset power integrity design requirements, iteratively executing the power integrity repair method until the optimized layout data meets the requirements.

[0065] Understandably, after adding vias, the following process is used to ensure the effectiveness of power integrity restoration: 1) Secondary verification. Using simulation tools (such as Cadence Voltus), the optimized power network is re-analyzed for IR Drop and EM to verify whether it meets design requirements (e.g., voltage drop ≤ 2%, EM ≤ 100%); 2) Iterative optimization. If the analysis results are unsatisfactory (e.g., EM in a certain area is still 120%), the dynamic via-punching process is executed again based on the new layout data (e.g., determining via-punching rules) until all constraints are met. For example, if a power network still has a local IR Drop of 3% (threshold 2%) after the first restoration, the system automatically triggers secondary via-punching, increasing the number of vias from 3 to 5 by increasing the k_v coefficient, ultimately reducing the IR Drop to 1.8%.

[0066] Please refer to Figures 3-5 . Figure 3 This indicates that in existing technology, under low current conditions, there are two through holes before optimization, but redundant holes appear after automatic drilling (marked in red). This demonstrates the defect of "redundancy generated by automatic drilling" in existing technology, which may lead to problems such as etching defects and antenna effects. Figure 4 This application's technical solution, also targeting scenarios with low current, is consistent with existing technologies before optimization. However, after automatic drilling, the number of through-holes is not increased, maintaining the original two through-holes. This indicates that this application, based on dynamic calculations (such as voltage drop differences or electromigration values), avoids the addition of redundant holes, thus solving the redundant hole problem in existing technologies. Figure 5 The technical solution of this application indicates that, under high current scenarios, there were two vias before optimization, and the number of vias increased after automatic drilling. This demonstrates that this application can reasonably increase the number of vias according to actual conditions (such as high electromigration risk or large voltage drop under high current) and rules (such as calculating the maximum number of vias based on electromigration values ​​and not less than the minimum number of vias required by the process) to meet power integrity requirements, reflecting the advantage of this application in "dynamic optimization, balancing performance and reliability".

[0067] Through the above Figures 3-5 The scenario comparison intuitively demonstrates the technical characteristics of this application compared to the prior art, which can avoid redundant vias and reasonably optimize the number of vias as needed under different current conditions, thereby achieving power integrity repair.

[0068] In summary, this application proposes a dynamically constrained power integrity repair method. Through joint analysis of voltage drop (IRDrop) and electromigration (EM), it intelligently determines via rules in intersecting power network regions: for regions without vias, it dynamically calculates the maximum number of vias based on the voltage drop difference; for regions with existing vias, it adjusts the number of vias based on electromigration values ​​and enforces minimum via constraints (such as TSMC DRC rules). Its advantages include: avoiding redundant vias and reducing parasitic capacitance in existing technologies through dynamic constraints of both voltage drop and EM (such as k_v*δV / Threshold_V and k_em*EM / Threshold_EM formulas); automated via rules replacing manual inspection, reducing the number of iterations; and adapting to different process nodes (such as 7nm and 28nm) with k_v / k_em correction coefficients, addressing the lack of customized rules in existing technologies.

[0069] On the other hand, such as Figure 6 As shown, this embodiment provides a power integrity repair device, including a data acquisition module 601, an analysis module 602, a candidate region identification module 603, a hole drilling rule determination module 604, and a through-hole optimization module 605.

[0070] For example, the data acquisition module 601 is configured to acquire power distribution network data in the layout.

[0071] For example, the analysis module 602 is configured to perform voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data including voltage drop differences in each region and electromigration hotspot data with labeled electromigration values.

[0072] For example, the candidate region identification module 603 is configured to identify intersecting regions in adjacent metal layers that meet the preset minimum drilling rules and have associated voltage drop difference and electromigration value as candidate drilling regions from the power distribution network data.

[0073] For example, the drilling rule determination module 604 is configured to determine the drilling rule for each candidate drilling area based on the voltage drop difference and the electromigration value. The drilling rule is that when there are no through holes in the candidate drilling area, the maximum number of through holes is calculated based on the voltage drop difference; when there are already through holes in the candidate drilling area, the maximum number of through holes is calculated based on the electromigration value.

[0074] For example, the via optimization module 605 is configured to perform a via addition operation based on the maximum number of vias to generate optimized layout data.

[0075] This embodiment also provides a computer-readable storage medium storing a computer program thereon, which is loaded by a processor to perform the steps in the power integrity repair method described in any of the above embodiments.

[0076] In the embodiments of this application, the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0078] The above provides a detailed description of a power integrity repair method, apparatus, and storage medium provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power integrity repair method, characterized by, The method comprises the following steps: Obtaining power distribution network data in a layout; Performing voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data containing voltage drop difference values of each region and electromigration hotspot data marked with electromigration values; Identifying, from the power distribution network data, intersecting regions in adjacent metal layers that meet a preset minimum via rule and have associated voltage drop difference values and electromigration values as candidate via regions; For each candidate via region, determining a via rule according to the voltage drop difference value and the electromigration value, wherein the via rule is that, when the candidate via region has no via, the maximum number of vias is calculated according to the voltage drop difference value; and when the candidate via region already has a via, the maximum number of vias is calculated according to the electromigration value; Performing a via adding operation according to the maximum number of vias to generate optimized layout data.

2. The power integrity repair method of claim 1, wherein, The voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data containing voltage drop difference values of each region and electromigration hotspot data marked with electromigration values comprise the following steps: Extracting parasitic resistance parameters and parasitic capacitance parameters of metal wires in the layout; Performing power distribution network simulation based on the parasitic resistance parameters and the parasitic capacitance parameters to obtain voltage values and current density values of all electrical nodes; Defining the difference between the voltage value and a preset power voltage nominal value as a voltage drop difference value, and generating the voltage drop distribution data through spatial interpolation; Converting the current density value into an electromigration value, and marking electrical nodes that exceed a process allowed maximum electromigration value as electromigration hotspots to form the electromigration hotspot data.

3. The power integrity repair method of claim 1, wherein, The determination of the via rule according to the voltage drop difference value and the electromigration value for each candidate via region comprises the following steps: For a via-free region, the maximum number of vias is obtained by multiplying the ratio of the voltage drop difference value to a preset voltage drop safety threshold value by a preset process correction coefficient; For a via region, the maximum number of vias is obtained by multiplying the ratio of the measured electromigration value to a preset electromigration threshold value by a preset electromigration correction coefficient; The maximum number of vias is not less than a process required minimum via number.

4. The power integrity repair method of claim 1, wherein, The identification of the intersecting regions in the adjacent metal layers that meet the preset minimum via rule and have associated voltage drop difference values and electromigration values as candidate via regions from the power distribution network data comprises the following steps: Judging whether the intersecting region between the metal layers belongs to an overlapping region of the same electrical node; Judging whether the area of the overlapping region meets the process minimum via size requirement; Judging whether the distance between the overlapping region and the existing via meets the design rule requirement; When all the judgments are positive results, the intersecting region is determined as a candidate via region.

5. The power integrity repair method of claim 1, wherein, The via adding operation according to the maximum number of vias to generate the optimized layout data comprises the following steps: When the calculated maximum number of vias is lower than the process required minimum via number, the via size is reduced in proportion before adding; When the calculated maximum number of vias is not less than the process required minimum via number, a standard via size and distance are used for adding; After performing the via adding operation, the optimized layout data is generated.

6. The power integrity repair method of claim 1, wherein, The method further comprises the following steps: After the via adding operation is performed, a design rule check is performed to verify whether the via spacing and the via-to-metal edge spacing meet the process requirements; and an electrical rule check is performed to verify whether the via current density and the metal line current density exceed the process upper limit; When a violation is found in the check, for the design rule check violation, the original number of vias is maintained, and the position of the violating via is adjusted to meet the minimum spacing requirement; for the electrical rule check violation, the number of vias is increased or the connection metal line width is expanded to reduce the current density below the safety threshold; The results of the design rule check and the electrical rule check are used to update the optimized layout data.

7. The power integrity repair method of claim 1, wherein, Further comprising: A layout change record table is established to record the via coordinates, sizes, change types, and their corresponding voltage drop improvement rates and electromigration risk levels; wherein the layout change record table is used as reference data for subsequent iterative optimization.

8. The power integrity repair method of claim 1, wherein, Further comprising: After the via adding operation is performed, the power distribution network data is re-analyzed for voltage drop and electromigration; When the analysis results do not meet the pre-set power integrity design requirements, the power integrity repair method of any one of claims 1-7 is iteratively performed until the optimized layout data meets the requirements.

9. A power integrity repair apparatus, characterized by, Comprising: A data acquisition module configured to acquire power distribution network data in a layout; An analysis module configured to analyze the power distribution network data for voltage drop and electromigration, obtaining voltage drop distribution data containing voltage drop difference values for each region and electromigration hotspot data labeled with electromigration values; A candidate region identification module configured to identify from the power distribution network data an intersection region in adjacent metal layers that meets a pre-set minimum via rule and has associated voltage drop difference values and electromigration values as a candidate via region; A via rule determination module configured to determine a via rule for each candidate via region based on the voltage drop difference values and the electromigration values, the via rule being to calculate the maximum number of vias based on the voltage drop difference values when the candidate via region has no via, and to calculate the maximum number of vias based on the electromigration values when the candidate via region already has a via; A via optimization module configured to perform a via adding operation based on the maximum number of vias to generate optimized layout data.

10. A computer-readable storage medium, characterized in that, A computer program is stored thereon, which is loaded by a processor to perform the steps in the method of any one of claims 1-8. A computer program is stored thereon, which is loaded by a processor to perform the steps in the method of any one of claims 1-8.

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