Aperture error and non-linear collaborative calibration circuit and method of assembly line ADC
By using aperture error and nonlinear calibration circuitry, the sampling clock skew and bandwidth mismatch issues of pipelined ADCs in SHA-less architecture are resolved, achieving high linearity and low cost ADC performance, suitable for integrated RF transceiver systems.
Patent Information
- Application Number
- CN202511391509.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-26
- Publication Date
- 2026-01-13
AI Technical Summary
In the SHA-less architecture, pipelined ADCs suffer from sampling clock skew and signal path bandwidth mismatch, which leads to dynamic comparator offset under non-DC input and deterioration of harmonic performance under high-frequency input, affecting linearity.
An aperture error calibration module is used in conjunction with code value histogram statistics and SAR logic feedback mechanism to detect and compensate for the sampling clock phase deviation between Sub-ADC and MDAC; a nonlinear error calibration module estimates and compensates for the nonlinear harmonic distortion of pipeline ADC through pseudo-random jitter injection and double threshold window cross-cutting statistics.
It achieves high linearity under large input bandwidth, reduces comparator offset sensitivity and process dependence, is suitable for integrated RF transceiver systems, and features low cost and high sensitivity.
Smart Images
Figure CN121333309A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of mixed signal integrated circuits, and particularly relates to a pipeline ADC (Analog-to-Digital Converter) aperture error and nonlinearity collaborative calibration circuit and method. BACKGROUND
[0002] With the development of 5G / 6G communication, satellite remote sensing and radar systems, unprecedentedly stringent requirements are put forward for the sampling rate, bandwidth and dynamic range of ADCs. Pipeline ADCs are widely used in high-speed scenarios above GS / s due to their high sampling rate and large input bandwidth, and have important significance and research value for realizing ultra-high-speed communication systems.
[0003] In order to realize a large input bandwidth, most pipeline ADCs usually adopt a SHA-less architecture, which significantly reduces system power consumption and expands input bandwidth by eliminating traditional SHA modules, but at the same time introduces new technical challenges such as sampling clock deviation (aperture error) and signal path bandwidth mismatch. Aperture error will cause the sampling time deviation of the two paths of sub-ADC and CDAC (capacitive digital analog converter), and will cause dynamic comparator offset under non-DC input, while bandwidth mismatch will significantly worsen harmonic performance as the input frequency increases, seriously affecting the linearity index of the ADC under high-frequency input. SUMMARY
[0004] In order to solve the above problems existing in the prior art, the application provides a pipeline ADC aperture error and nonlinearity collaborative calibration circuit and method. The technical problem to be solved by the application is realized by the following technical scheme: The application provides a pipeline ADC aperture error and nonlinearity collaborative calibration circuit, comprising: a pipeline ADC circuit and a calibration circuit connected with the first stage of the pipeline ADC circuit, the calibration circuit comprising an aperture error calibration module and a nonlinearity error calibration module, wherein, The pipeline ADC circuit is used for sampling and step-by-step quantizing an input analog signal and outputting a digital code; The aperture error calibration module is used for combining code value histogram statistics and SAR logic feedback mechanism, detecting and compensating for the sampling clock phase deviation between the first stage Sub-ADC and MDAC according to the output of the pipeline ADC circuit; The nonlinearity error calibration module is used for combining pseudo-random jitter injection and error estimation of double-threshold window crossing statistics, detecting and compensating for the nonlinearity harmonic distortion of the pipeline ADC circuit according to the output of the pipeline ADC circuit.
[0005] The application also provides a method for calibrating aperture error and nonlinearity of a pipeline ADC, and a pipeline ADC aperture error and nonlinearity calibration circuit according to any one of the embodiments. Step 1: Perform aperture error calibration process, combine code value histogram statistics and SAR logic feedback mechanism, adjust the sampling clock phase of the first stage Sub-ADC of the pipeline ADC circuit according to the output of the pipeline ADC circuit, so that it is aligned with the sampling time of the MDAC; Step 2: Perform nonlinearity error calibration process, combine pseudo-random jitter injection and error estimation of double-threshold window crossing statistics, dynamically estimate and compensate the nonlinearity harmonic distortion of the pipeline ADC circuit according to the output of the pipeline ADC circuit.
[0006] Compared with the prior art, the application has the following beneficial effects: The pipeline ADC aperture error and nonlinearity calibration circuit of the application not only retains the large input bandwidth characteristics of the SHA-less architecture, but also realizes high linearity index under large input bandwidth by introducing digital background calibration methods of aperture error calibration and nonlinearity calibration, has the characteristics of low cost and high sensitivity, avoids the problems of comparator offset sensitivity, strong process dependence and large area overhead, and is suitable for application scenarios such as integrated radio frequency transceiver systems.
[0007] The above description is only a summary of the technical solutions of the application, in order to more clearly understand the technical means of the application, the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are as follows. BRIEF DESCRIPTION OF DRAWINGS
[0008] Figure 1 is a principle block diagram of a pipeline ADC aperture error and nonlinearity calibration provided by an embodiment of the application; Figure 2 is a schematic diagram of sampling clock tilt and its influence on the residual curve of the pipeline ADC provided by an embodiment of the application; Figure 3 is a principle block diagram of aperture error calibration provided by an embodiment of the application; Figure 4 is a schematic diagram of clock phase convergence process during aperture error calibration provided by an embodiment of the application; Figure 5 is a flowchart of nonlinearity harmonic calibration provided by an embodiment of the application; Figure 6 is a pipeline ADC quantization spectrum diagram under low frequency and Nyquist frequency provided by an embodiment of the application; Figure 7 SNDR and SFDR of the pipeline ADC provided by the embodiment of the present application at each input frequency. DETAILED DESCRIPTION
[0009] In order to further illustrate the technical means and effects taken by the present application to achieve the predetermined purposes, the aperture error and nonlinearity co-calibration circuit and method of a pipeline ADC according to the present application are described in detail below in combination with the drawings and specific embodiments.
[0010] The foregoing and other technical contents, features and effects of the present application can be clearly presented in the specific embodiment description below in combination with the drawings. Through the description of the specific embodiments, the technical means and effects taken by the present application to achieve the predetermined purposes can be understood more deeply and specifically. However, the attached drawings are provided for reference and illustration only, and are not used to limit the technical solutions of the present application.
[0011] In a first aspect, the embodiment of the present application provides an aperture error and nonlinearity co-calibration circuit of a pipeline ADC, please refer to Figure 1 , Figure 1 The principle block diagram of the aperture error and nonlinearity co-calibration of the pipeline ADC provided by the embodiment of the present application is shown in Figure 1 The aperture error and nonlinearity co-calibration circuit of the pipeline ADC of the present embodiment includes a pipeline ADC circuit and a calibration circuit connected with the first stage of the pipeline ADC circuit, and the calibration circuit includes an aperture error calibration module and a nonlinearity error calibration module.
[0012] The pipeline ADC circuit is used to sample and quantize the input analog signal step by step and output digital codes; the aperture error calibration module is used to detect and compensate the sampling clock phase deviation between the first stage Sub-ADC and MDAC according to the output of the pipeline ADC circuit by combining code value histogram statistics and SAR logic feedback mechanism; the nonlinearity error calibration module is used to detect and compensate the nonlinearity harmonic distortion of the pipeline ADC circuit according to the output of the pipeline ADC circuit by combining pseudo-random dithering injection and double-threshold window crossing statistics error estimation.
[0013] In an optional embodiment, the aperture error calibration module includes an adjustable delay chain and a digital control unit. The adjustable delay chain is connected with the sampling switch of the Sub-ADC and the comparator switch of the MDAC respectively, and is used to provide controllable binary delay for the Sub-ADC and the MDAC according to the received control code. The digital control unit is used to execute the aperture error calibration algorithm and generate the control code according to the output of the pipeline ADC circuit.
[0014] In an optional embodiment, the digital control unit executes a aperture error calibration algorithm to generate the control code according to the output of the pipeline ADC circuit, which can include the following steps: S1: alternately output the first control code and the second control code to the adjustable delay chain to generate the first sampling clock phase and the second sampling clock phase.
[0015] In this embodiment, the first sampling clock phase represents that the sampling time of the Sub-ADC is earlier than the sampling time of the MDAC, and the second sampling clock phase represents that the sampling time of the Sub-ADC is later than the sampling time of the MDAC.
[0016] S2: respectively count the histogram distribution of the digital code output by the pipeline ADC circuit corresponding to the first sampling clock phase and the second sampling clock phase under a preset number of sampling points.
[0017] In this embodiment, the number of occurrences and the frequency of the code value after splicing of the pipeline ADC circuit are counted under a certain number of sampling points when sampling under the two sampling clock phases.
[0018] S3: compare the size and the frequency of the corresponding code values in the two histogram distributions bit by bit from the highest bit.
[0019] In this embodiment, according to the obtained statistical results, the size and the distribution frequency of the code values under the two sampling clock phases are compared from high to low.
[0020] S4: determine the sampling clock phase that causes greater deviation according to the comparison result, and adjust the corresponding control code in the direction of reducing the deviation according to the determined sampling clock phase.
[0021] In this embodiment, if the high bit code value of one of the sampling clock phases is larger or the frequency is higher, it is determined that the high frequency deviation caused by this sampling clock phase is larger, and the control code corresponding to this sampling clock phase is adjusted in the direction of the MDAC sampling time, otherwise the next high bit code value is compared, and so on until the comparison is completed.
[0022] S5: iteratively execute steps S1-S4 until the difference between the first control code and the second control code is less than a preset threshold.
[0023] In this embodiment, the digital control unit is further configured to calculate the mean value of the first control code and the second control code as the optimal control code when the difference between the first control code and the second control code is less than the preset threshold, so as to lock the adjustable delay chain at the optimal sampling clock phase.
[0024] The aperture error calibration module of the embodiment includes an analog part and a digital part, wherein the analog part can be executed by analog circuits (such as switches, capacitors, amplifiers, comparators); and the digital part can be executed by digital circuits or logic (such as state machines, processors, counters, comparators, SAR logic).
[0025] In the embodiment, the analog part, that is, the adjustable delay chain, can be a controllable binary switch capacitor array, which provides controllable binary delays for the sampling circuit nodes of the Sub-ADC of the first stage of the pipeline ADC circuit and the comparator comparison switch of the MDAC. The digital part, that is, the digital control unit, is responsible for implementing the generation algorithm of the control code of the binary switch capacitor array. By monitoring the number of occurrences and the frequency of the output digital code value after splicing of the later stage of the pipeline ADC circuit, the control code is updated after SAR feedback logic processing to control the binary capacitor array switch, so as to adjust the sampling clock phase deviation of the Sub-ADC and the MDAC to an acceptable range, and realize adaptive calibration convergence.
[0026] In the high-speed application of the pipeline ADC, the sampling clock skew Δt will significantly change the residual curve characteristics of the ADC, as shown in the sampling clock skew and its influence on the residual curve of the pipeline ADC. Figure 2 When the clock deviation exists, the MDAC and the Sub-ADC path sample different signal instantaneous values, which causes the ideal linear transfer curve to appear nonlinear distortion, and introduces harmonic distortion in the frequency domain.
[0027] Specifically, the specific process of executing the aperture error calibration algorithm by the digital control unit of the embodiment is described in detail.
[0028] First, the adjustable delay chain control logic circuit gives the alternating control codes A and B in the first round of calibration, and controls the sampling time of the Sub-ADC to be before or after the sampling time of the MDAC in the first stage of the pipeline ADC circuit, which corresponds to the sampling clock phases φ1 and φ2, respectively. Then the number of occurrences and the frequency of the code value after splicing of the later stage of the pipeline ADC circuit are counted under the two sampling clock phases. According to the statistical results, the size and the distribution frequency of the code value under the two sampling clock phases are compared from high bits to low bits. If the high bit code value of one of the sampling clock phases is larger or has a higher frequency, it is determined that the high frequency deviation caused by the sampling clock phase is larger, and the control code corresponding to the sampling clock phase is adjusted in the direction of the MDAC sampling time, otherwise the next high bit code value is compared, and so on until the comparison is completed. Calibration is performed once every sampling point, and the loop is iterated until the algorithm converges. When the difference between the two control codes is less than a preset threshold, it is considered to be converged, and the average of the final control codes A and B is taken as the optimal control code to stabilize the sampling clock phase at the optimal position.
[0029] Exemplarily, when comparing the size and distribution frequency of the code values of the two sampling clock phases from high bit to low bit, firstly, whether 1 exists in the two highest bits is compared, if 1 exists in both, the frequency of the appearance of 1 is compared, the sampling clock phase with higher frequency of the appearance of 1 causes greater high frequency deviation; otherwise, if 1 exists in the highest bit only in one sampling clock phase and 0 exists in the highest bit only in the other sampling clock phase, the sampling clock phase with the code value of 1 causes greater high frequency deviation can be directly determined, that is, the sampling clock phase causing greater high frequency deviation is determined by comparing the size of the code values.
[0030] It should be noted that if the code value distribution of the two histograms is completely consistent, it may be that the number of iteration points is too small to expose the super redundancy problem. In this case, the control code is not adjusted, but the code value statistical distribution operation is performed again until the code value distribution is different or the algorithm converges.
[0031] Please refer to Figure 3 , Figure 3 is the principle block diagram of the aperture error calibration provided by the embodiment of the present application, as shown in Figure 3 , the code values of the back stage of the pipeline ADC circuit are sent to the histogram counter after splicing and optimization processing to count the number of occurrences and frequency, the comparison results are sent to the digital switch control code generation circuit based on the SAR logic feedback after comparison by each bit comparator, the control codes A and B are updated, the opening and closing of the binary switch capacitor array at the sampling node of the first stage of the pipeline ADC circuit and the comparator switch are controlled, thereby controlling the delay on these nodes. The range of the code values output by the back stage of the pipeline ADC circuit is updated after the update of the control codes, the new output code values are sent to the histogram counter for a new round of calibration, until the code values of the control codes A and B are close and the difference is less than the preset threshold φth, the algorithm converges. As shown in Figure 4 , the clock phase convergence process schematic diagram during the aperture error calibration provided by the embodiment of the present application, in the initial phase, the sampling phase deviation of the two kinds of clocks controlled by the control codes A and B is close to the maximum, the phase with greater deviation is determined according to the statistical algorithm, and the phase iteration is repeatedly performed, finally in the phase convergence stage, the sampling clock phase is stabilized at the optimal position.
[0032] It can be understood that during the working process of the pipeline ADC, the aperture error calibration module can be periodically or aperiodically reactivated (for example, when the chip temperature or power voltage changes significantly), and the aperture error calibration algorithm is repeatedly executed, so as to realize adaptive compensation for the fluctuation under the change of PVT (process, voltage, temperature).
[0033] In an optional embodiment, the nonlinear error calibration module comprises a dither generation and injection module and a nonlinear harmonic calibration digital unit. The dither generation and injection module is configured to generate a pseudo-random dither sequence and superimpose the pseudo-random dither sequence in the form of a voltage on the analog signal by using a switched capacitor provided in the MDAC.
[0034] In the embodiment, the amplitude of the pseudo-random dither sequence is controllable, for example, the pseudo-random dither sequence can have an amplitude of ±Dither.
[0035] The nonlinear harmonic calibration digital unit is configured to linearize and compensate the digital code corresponding to the analog signal superimposed with the dither, calibrate the compensated digital code according to the pseudo-random dither sequence, construct an original error function according to the number of crossing behaviors of the calibrated digital code based on a double-threshold window crossing detection method, smooth the original error function, and update the compensation coefficient of the linearization compensation according to the smoothed error function by using a least mean square algorithm.
[0036] Optionally, the smoothing of the error function comprises using an exponential weighted moving average filter to smooth the original error function. In the embodiment, by smoothing the original error function, the quantization noise and the high-frequency components introduced by the calibration itself are effectively suppressed, and the long-term trend characteristics of the error signal can be retained.
[0037] The nonlinear error calibration module of the embodiment can adopt a four-stage feedback processing architecture, and also comprises an analog part and a digital part. The analog part can be executed by an analog circuit (such as a switched capacitor of the MDAC and a voltage injection circuit), and the digital part can be executed by a digital logic circuit (such as a DSP, a state machine, a filter, and an LMS engine).
[0038] Further, the nonlinear harmonic calibration process provided by the embodiment of the application is illustrated in the flowchart shown in Figure 5 The compensation and calibration process of the nonlinear harmonic calibration digital unit of the embodiment is described in detail.
[0039] As shown in Figure 5 The pseudo-random dither with an amplitude of ±Dither is injected into the analog signal by the switched capacitor at the MDAC. After data splicing, the digital code Dout output by the pipeline ADC circuit is processed by the linearization compensation device, and then the ±Dither previously injected in the MDAC is subtracted to obtain the calibrated digital code Dout_cal. The digital code Dout_cal is input into the nonlinear harmonic calibration digital unit provided with ± D thThe double-threshold window signal crossing behavior detection device counts the number of crossing behaviors at the detection point and constructs an original error function err. Considering the random fluctuation of the error signal in a high-frequency sampling environment, an exponential weighted moving average (EWMA) filter is introduced to extract the error signal and perform EWMA algorithm to smooth the original error function, obtaining a smoothed error function err_avg. This method can effectively suppress the quantization noise and the high-frequency components introduced by the calibration itself, and can retain the long-term trend characteristics of the error signal, avoiding the mis-calibration caused by instantaneous fluctuations. The smoothed error function err_avg is sent to the LMS iterative algorithm device, which is used to update the compensation coefficients arf 2~5 , the iterative formula is represented as: .
[0040] In the formula, is the updated order compensation coefficient of the th time, is the updated order compensation coefficient of the th time, is the calibration step size, is the smoothed error.
[0041] The error estimation and linearization compensation device updates the compensation coefficients arf 2~5 , and then processes the digital code Dout output by the pipeline ADC circuit and performs the next round of loop self-calibration until the algorithm converges, finally realizing the digital background calibration of the non-linear harmonics.
[0042] Exemplarily, the construction process of the original error function err is described. First, Dout_cal is sent into the double-threshold window signal crossing behavior detection device, and the number of signal crossing behaviors at the detection point is counted and represented as: D th The double-threshold window signal crossing behavior detection device counts the number of signal crossing behaviors at the detection point and is represented as: ; ; In the formula, represents a pseudo-random dithering sequence, is a sign judgment function, which takes 1 when the content in the parentheses is true, and 0 otherwise, The original error function err is constructed and represented as: .
[0043] It should be noted that in the first round of calibration, the compensation coefficients arf 2~5are initial values, thus, Dout_cal processed by the error estimation and linearization compensation device is actually the same as Dout. After the value of the compensation coefficient arf 2~5 is updated for the first time, the error estimation and linearization compensation device can actually process Dout.
[0044] The aperture error and nonlinearity cooperative calibration circuit of the pipeline ADC of the embodiment adds relevant calibration circuits to the pipeline ADC circuit structure. An adjustable bandwidth load is added to the sampling path of the Sub-ADC of the first stage of the pipeline analog-to-digital converter, so as to match the sampling time and bandwidth of the MDAC path. The second stage and subsequent stages of the pipeline are similar to the first stage, and all contain Sub-ADCs and MDACs but do not contain calibration-related circuits. The aperture error calibration module controls the digital adjustable delay chain to adjust the sampling clock phase of the Sub-ADC to eliminate the clock deviation between the sampling time of the MDAC by extracting the spliced code value distribution information of the subsequent stage in real time. At the same time, a pseudo-random dither sequence ±Dither is injected from the switch capacitor of the MDAC and quantized by the subsequent ADC, and the output code value enters the nonlinearity harmonic calibration digital unit: the output code value first enters the linearization compensation device for linearization compensation of the last compensation coefficient, and then enters the signal crossing behavior detection device provided with a double-threshold window. The number of crossing behaviors at the detection point is counted and used to construct an original error function. After moving average filtering (EWMA), the compensation coefficient arf 2~5 is dynamically adjusted through the LMS error feedback mechanism, the linearization compensation effect of the linearization compensation device on the output code value is adjusted, and background nonlinearity calibration is realized.
[0045] The aperture error and nonlinearity cooperative calibration circuit of the pipeline ADC of the embodiment not only retains the large input bandwidth characteristic of the SHA-less architecture, but also realizes high linearity under large input bandwidth through the introduction of the digital background calibration method of aperture error calibration and nonlinearity calibration, has the characteristics of low cost and high sensitivity, avoids problems such as comparator offset sensitivity, strong process dependence and large area overhead, and is suitable for application scenarios such as integrated radio frequency transceiver systems. Based on the pipeline architecture under the CMOS process, the sampling bandwidth is effectively improved under ultrahigh-speed sampling through bandwidth matching and aperture error cooperative calibration, and the large-bandwidth robustness of the ADC under PVT fluctuation is realized. The architecture is suitable for ultrahigh-speed high-bandwidth signal acquisition scenarios such as electronic countermeasures, and has breakthroughly realized the indexes of 0-10GHz sampling rate and maximum 5GHz input bandwidth under the CMOS process. Compared with traditional schemes, the architecture has the advantages of low hardware cost, multi-module reusability and high integration, and has important significance and research value.
[0046] In a second aspect, the embodiments of the present application provide a method for aperture error and nonlinearity co-calibration of a pipeline ADC, which is suitable for the pipeline ADC aperture error and nonlinearity co-calibration circuit provided in the first aspect, and the method comprises: Step 1: performing an aperture error calibration process, combining code histogram statistics and SAR logic feedback mechanism, adjusting the sampling clock phase of the Sub-ADC of the first stage of the pipeline ADC circuit according to the output of the pipeline ADC circuit, so that it is aligned with the sampling time of the MDAC.
[0047] In an optional embodiment, step 1 comprises: Step 1.1: alternately outputting the first control code and the second control code to the first stage of the pipeline ADC circuit to generate corresponding first sampling clock phase and second sampling clock phase; Step 1.2: respectively counting the histogram distribution of the digital code output by the pipeline ADC circuit corresponding to the first sampling clock phase and the second sampling clock phase under a preset number of sampling points; Step 1.3: comparing the size and frequency of the corresponding code values in the two histogram distributions bit by bit from the highest bit; Step 1.4: determining the sampling clock phase that causes greater deviation according to the comparison result, and adjusting the corresponding control code in the direction of reducing the deviation according to the determined sampling clock phase; Step 1.5: repeating steps 1.1-1.4 until the difference between the first control code and the second control code is less than a preset threshold, and calculating the mean value of the first control code and the second control code as the optimal control code output.
[0048] Step 2: performing a nonlinearity error calibration process, combining pseudo-random dithering injection and error estimation of double-threshold window crossing statistics, dynamically estimating and compensating the nonlinearity harmonic distortion of the pipeline ADC circuit according to the output of the pipeline ADC circuit.
[0049] In an optional embodiment, step 2 comprises: Step 2.1: generating a pseudo-random dithering sequence, and superimposing the pseudo-random dithering sequence in the form of voltage on the analog signal input to the pipeline ADC circuit; Step 2.2: performing linearization compensation on the digital code output by the pipeline ADC circuit, calibrating the compensated digital code according to the pseudo-random dithering sequence to obtain calibrated digital code; Step 2.3: detecting the crossing behavior of the calibrated digital code according to the preset double-threshold window, and constructing an original error function according to the statistical result of the number of crossing behaviors, Step 2.4: smoothing the original error function, and iteratively updating the compensation coefficient of the linearization compensation according to the smoothed error function using the least mean square algorithm; Step 2.5: Perform the compensation operation of step 2.2 using the updated compensation coefficient, form a closed-loop feedback until the error converges.
[0050] The aperture error and nonlinearity collaborative calibration method of the pipeline ADC of the embodiment is based on bandwidth matching and aperture error calibration of a post-stage quantization code value statistical distribution. By detecting a quantization code value of a post-stage Sub-ADC, a distribution characteristic is obtained, and compared with an ideal distribution characteristic, a clock phase error is extracted and compensated. For adaptive calibration of harmonic distortion of a high-speed ADC, an LMS algorithm and an EWMA smoothing filter are used to iteratively optimize a harmonic compensation coefficient, and the output nonlinearity of the pipeline ADC is obviously improved.
[0051] For specific contents of the aperture error and nonlinearity collaborative calibration method of the pipeline ADC and corresponding beneficial effects, please refer to the related contents of the aperture error and nonlinearity collaborative calibration circuit of the pipeline ADC provided in the first aspect, which will not be repeated here.
[0052] Further, the effect of the aperture error and nonlinearity collaborative calibration circuit and method of the pipeline ADC of the embodiment is illustrated by experiments. Different frequency sinusoidal signals are input to the aperture error and nonlinearity collaborative calibration circuit of the pipeline ADC of the embodiment, output data of the pipeline ADC circuit is read, and a MATLAB program is used for discrete Fourier transform (DFT), so as to test the spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) under different input frequencies. Taking a sampling rate of 10 GS / s and an input analog signal frequency of 4.9 GHz as an example, the pipeline ADC quantization spectrum under low frequency and Nyquist frequency is as shown in FIG. 6, wherein the SFDR of the output data under low frequency input is 63.1 dB, and the SNDR is 48.9 dB; the SFDR of the output data under Nyquist frequency input is 64 dB, and the SNDR is 48 dB. Through frequency sweeping, the SFDR and SNDR of the output under each input frequency are as shown in FIG. 7. Figure 6 Figure 7 The pipeline ADC provided in the embodiment of the present application has the SNDR and SFDR under each input frequency as shown in FIG. 7.
[0053] It is to be understood that the terminology "first", "second", and the like used herein is merely intended to differentiate one element from another element, and does not imply or suggest any actual relationship or sequence between the elements. Also, the terms "comprise", "comprising", or any other variant thereof are intended to cover non-exclusive inclusions, such that an item or apparatus that comprises a list of elements does not exclude other elements not expressly listed. An element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the item or apparatus comprising the element. The terms "connected" or "coupled" or similar terms are not limited to a direct physical or mechanical connection, but can also include an electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are merely intended to facilitate the description of the present application and simplify the description, and thus cannot be construed as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as limiting the present application.
[0054] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. The illustrative expressions of the above terms in the present specification do not necessarily refer to the same embodiment or example. Also, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, a person skilled in the art can combine and integrate different embodiments or examples described in the present specification.
[0055] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those of ordinary skill in the art to which the present application belongs, a number of simple deductions or substitutions can be made without departing from the concept of the present application, and all should be considered as falling within the scope of protection of the present application.
Claims
1. A collaborative calibration circuit for aperture error and nonlinearity of a pipelined ADC, characterized in that, include: A pipelined ADC circuit and a calibration circuit connected to the first stage of the pipelined ADC circuit, wherein the calibration circuit includes an aperture error calibration module and a nonlinear error calibration module, wherein... The pipelined ADC circuit is used to sample and quantize the input analog signal step by step and output digital code. The aperture error calibration module is used to combine code value histogram statistics and SAR logic feedback mechanism to detect and compensate for the sampling clock phase deviation between the first-stage Sub-ADC and MDAC based on the output of the pipeline ADC circuit. The nonlinear error calibration module is used to combine pseudo-random jitter injection and double threshold window cross-cutting statistics for error estimation, and to detect and compensate for the nonlinear harmonic distortion of the pipelined ADC circuit based on the output of the pipelined ADC circuit.
2. The aperture error and nonlinearity co-calibration circuit for pipelined ADC according to claim 1, characterized in that, The aperture error calibration module includes: An adjustable delay chain, connected to the sampling switch of the Sub-ADC and the comparator switch of the MDAC respectively, is used to provide controllable binary delay for the Sub-ADC and the MDAC according to the received control code; A digital control unit is used to execute the aperture error calibration algorithm and generate the control code based on the output of the pipeline ADC circuit.
3. The aperture error and nonlinearity co-calibration circuit for pipelined ADC according to claim 2, characterized in that, The digital control unit executes the aperture error calibration algorithm and generates the control code based on the output of the pipeline ADC circuit, including: S1: Alternately output the first control code and the second control code to the adjustable delay chain to generate the first sampling clock phase and the second sampling clock phase; S2: Calculate the histogram distribution of the digital codes output by the pipeline ADC circuit corresponding to the first sampling clock phase and the second sampling clock phase, respectively, under a preset number of sampling points; S3: Starting from the most significant bit, compare the magnitude and frequency of corresponding code values in the two histogram distributions bit by bit; S4: Based on the comparison results, determine the sampling clock phase that causes the larger deviation, and adjust the corresponding control code in the direction of reducing the deviation according to the determined sampling clock phase; S5: Iteratively execute steps S1-S4 until the difference between the first control code and the second control code is less than a preset threshold.
4. The aperture error and nonlinearity co-calibration circuit for pipelined ADC according to claim 3, characterized in that, The first sampling clock phase indicates that the sampling time of the Sub-ADC is earlier than the sampling time of the MDAC, and the second sampling clock phase indicates that the sampling time of the Sub-ADC is later than the sampling time of the MDAC.
5. The aperture error and nonlinearity co-calibration circuit for pipelined ADC according to claim 3, characterized in that, The digital control unit is further configured to calculate the average of the first control code and the second control code as the optimal control code when the difference between the first control code and the second control code is less than a preset threshold, so as to lock the adjustable delay chain at the optimal sampling clock phase.
6. The aperture error and nonlinearity co-calibration circuit for pipelined ADC according to claim 1, characterized in that, The nonlinear error calibration module includes: Dither generation injection module is used to generate pseudo-random jitter sequence and superimpose the pseudo-random jitter sequence on the analog signal in the form of voltage using the switched capacitor set in the MDAC; A nonlinear harmonic calibration digital unit is used to linearize the digital code corresponding to the superimposed jitter analog signal. The compensated digital code is calibrated according to the pseudo-random jitter sequence. Based on the dual threshold window crossing detection method, an original error function is constructed according to the number of crossing behaviors of the calibrated digital code. The original error function is smoothed, and the least mean square algorithm is used to update the compensation coefficient of linearization compensation according to the smoothed error function.
7. The aperture error and nonlinearity co-calibration circuit for pipelined ADC according to claim 6, characterized in that, Smoothing the error function includes: using an exponentially weighted moving average filter to smooth the original error function.
8. A method for coordinated calibration of aperture error and nonlinearity in a pipelined ADC, characterized in that, The method, adapted to the aperture error and nonlinearity co-calibration circuit of the pipeline ADC according to any one of claims 1-7, comprises: Step 1: Perform the aperture error calibration process. Combining code value histogram statistics and SAR logic feedback mechanism, adjust the sampling clock phase of the first stage Sub-ADC of the pipelined ADC circuit according to the output of the pipelined ADC circuit so that it is aligned with the sampling time of the MDAC. Step 2: Perform a nonlinear error calibration process, combining pseudo-random jitter injection and error estimation with double threshold window cross-cutting statistics, and dynamically estimate and compensate for the nonlinear harmonic distortion of the pipelined ADC circuit based on the output of the pipelined ADC circuit.
9. The method for coordinated calibration of aperture error and nonlinearity of pipelined ADC according to claim 8, characterized in that, Step 1 includes: Step 1.1: Alternately output the first control code and the second control code to the first stage of the pipelined ADC circuit to generate the corresponding first sampling clock phase and second sampling clock phase; Step 1.2: Calculate the histogram distribution of the digital codes output by the pipeline ADC circuit corresponding to the first sampling clock phase and the second sampling clock phase, respectively, under the preset number of sampling points; Step 1.3: Starting from the most significant bit, compare the magnitude and frequency of corresponding code values in the two histogram distributions bit by bit; Step 1.4: Based on the comparison results, determine the sampling clock phase that causes the larger deviation, and adjust the corresponding control code in the direction of reducing the deviation according to the determined sampling clock phase; Step 1.5: Repeat steps 1.1-1.4 until the difference between the first control code and the second control code is less than a preset threshold. Then, calculate the average of the first control code and the second control code as the optimal control code output.
10. The method for coordinated calibration of aperture error and nonlinearity of a pipelined ADC according to claim 8, characterized in that, Step 2 includes: Step 2.1: Generate a pseudo-random jitter sequence and superimpose the pseudo-random jitter sequence onto the analog signal input to the pipeline ADC circuit in the form of a voltage. Step 2.2: Perform linearization compensation on the digital code output by the pipeline ADC circuit, and calibrate the compensated digital code according to the pseudo-random jitter sequence to obtain the calibrated digital code; Step 2.3: Based on a preset dual-threshold window, detect the crossing behavior of the calibrated digital code, and construct the original error function based on the statistical results of the number of crossing behaviors. Step 2.4: Smooth the original error function and use the least mean square algorithm to iteratively update the linearization compensation coefficients based on the smoothed error function; Step 2.5: Execute the compensation operation in step 2.2 using the updated compensation coefficients to form a closed-loop feedback until the error converges.