Automatic compiling vectorization method, terminal and medium

Abstract

The invention provides a compiling automatic vectorization method, a terminal and a medium, and the method comprises the steps: extracting each seed instruction group in a program block, and constructing an instruction group queue based on each extracted seed instruction group; sequentially executing SIMD (Single Instruction Multiple Data) judgment on each instruction group in the instruction group queue, and executing a corresponding vectorization design according to an SIMD judgment result to obtain an initial vectorization scheme; performing redundant structure rewriting on the initial vectorization scheme to obtain a simplified vectorization scheme; respectively calculating a scalar total execution cost and a vector total execution cost corresponding to the simplified vectorization scheme by using a preset cost model; when it is detected that the scalar total execution cost is larger than the vector total execution cost, setting the simplified vectorization scheme as a final vectorization scheme, and conducting vectorization compiling on the program block based on the final vectorization scheme; according to the method, the compiling efficiency of program vectorization compiling can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of computer application technology, and to an automatic vectorization method for compilation, a terminal, and a medium. Background Technology

[0002] Vectorized computation refers to executing the same instruction on multiple different data simultaneously, that is, applying instructions to an array / vector at the same time to achieve the effect of parallel computing. To achieve vectorized computation, it is usually necessary to use automatic vectorization methods to optimize the program during compilation. That is, by analyzing loops or other potential parallel patterns in the program source code, scalar instructions are automatically converted into vectorized instructions. After compilation, the processor's SIMD (Single Instruction, Multiple Data) instruction set is used to perform vectorized execution.

[0003] To achieve vectorized computation, existing processors often integrate SIMD extension units as acceleration components to perform data-level parallel computation. Although existing SIMD extension units can support various vector registers of different sizes, the SIMD operation instructions generated based on existing automatic vectorization methods can often only operate on fixed-size SIMD registers. That is, in a single round of vectorization compilation, SIMD instructions can only be generated for a fixed-size vectorization factor. When executing SIMD instructions generated based on a fixed-size vectorization factor, the performance advantage of the SIMD unit supporting multiple vectorization factors is often not utilized, resulting in low hardware performance utilization efficiency of the SIMD unit. Furthermore, for complex program structures, the sizes of the various vectorization factors usually differ, which often requires repeated compilation of the same program, resulting in inefficient vectorized programs. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide an automatic vectorization compilation method, terminal, and computer storage medium to solve the problems that existing automatic vectorization compilation methods cannot flexibly adapt to different sizes of SIMD registers and corresponding arithmetic instructions when performing vectorization compilation of varying complexity, i.e., they cannot flexibly utilize different sizes of SIMD registers and arithmetic instructions to handle the vectorization compilation process of complex programs, resulting in low utilization efficiency of SIMD hardware performance.

[0005] To achieve the above and other related objectives, the present invention provides a method for automatic vectorization of compilation in a first aspect, comprising: extracting various sub-instruction groups from a program block, and constructing an instruction group queue based on the extracted sub-instruction groups; performing vector design based on SIMD decision results on each sub-instruction group in the instruction group queue to obtain a total initial vector scheme; performing redundant structure rewriting on the total initial vectorization scheme to obtain a simplified vectorization scheme; calculating the scalar total execution cost and vector total execution cost corresponding to the simplified vectorization scheme using a preset cost model; detecting whether the scalar total execution cost is greater than the vector total execution cost, and if so, setting the simplified vectorization scheme as the final vectorization scheme, and performing vectorized compilation of the program block based on the final vectorization scheme.

[0006] In one embodiment of this application, the method for extracting various sub-instruction groups from a program block includes: obtaining each original instruction in the program block corresponding to an instruction type as a related instruction corresponding to the instruction type; dividing each related instruction into several initial instruction groups according to the dependency relationship between the related instructions; obtaining each Store instruction in the program block and dividing each Store instruction into several initial instruction groups according to the dependency relationship between the instructions; splitting each initial instruction group according to the continuity of the access address and the data type of the access data to obtain various sub-instruction groups; wherein, the instructions in a single seed instruction group are arranged in the order of the access address.

[0007] In one embodiment of this application, for a single seed instruction group, the implementation of the vector design based on the SIMD determination result includes: extracting a new associated instruction group from the associated instruction group queue corresponding to the current seed instruction group, and using it as the current instruction group; wherein, the associated instruction group queue is a queue pre-constructed based on the current seed instruction group, used to store instruction groups associated with the current seed instruction group; performing SIMD determination on the current instruction group, and updating the current vectorization scheme corresponding to the current instruction group according to the determination result; and, when the determination result is to maintain VF or reduce VF, expanding the associated instruction group queue; iteratively updating the current instruction group until the iteration process is completed for all associated instruction groups in the associated instruction group queue; and using the latest obtained vectorization scheme as the initial vectorization scheme corresponding to the current seed instruction group.

[0008] In one embodiment of this application, the step of performing SIMD determination on the current instruction group and updating the current vectorization scheme corresponding to the current instruction group according to the determination result includes: determining whether the current instruction group can be directly replaced by a single SIMD instruction based on the hardware characteristics of the target hardware, and determining whether there is a dependency relationship between the parameter instructions in the current instruction group; if both are satisfied, the current vectorization method is determined to be maintaining VF, and a current node corresponding to the current instruction group is added to the current vectorization scheme, and the current node is marked as maintaining VF; if not satisfied simultaneously, the length of the current instruction group is further compared with the length threshold; when it is greater than the length threshold, the current vectorization method is determined to be reducing VF, and a current node corresponding to the current instruction group is added to the current vectorization scheme, and the current node is marked as reducing VF; when it is less than or equal to the length threshold, the current vectorization method is determined to be abandoning vectorization; a current node corresponding to the current instruction group is added to the current vectorization scheme, and the current node is marked as abandoning vectorization.

[0009] In one embodiment of this application, the expansion process of the associated instruction group queue includes: when the current vectorization method is to maintain VF, extracting each instruction parameter in the current instruction group and constructing each instruction parameter into a parameter matrix corresponding to the current instruction group; in the parameter matrix, setting each instruction parameter with the same parameter position as the same instruction parameter class; according to the instruction type of the current instruction group, performing a vectorizability determination on each instruction parameter class in the current instruction group one by one, extracting the vectorizable instruction parameter class, and further extracting the set of parameter instructions corresponding to the vectorizable instruction parameter class, adding it as a new instruction group to the current associated instruction group queue; and when the current vectorization method is to reduce VF, performing optimal segmentation on the current instruction group to obtain a first sub-instruction group and a second sub-instruction group; adding the segmented first sub-instruction group and second sub-instruction group to the current associated instruction group queue respectively.

[0010] In one embodiment of this application, the implementation of redundant structure rewriting of the initial vectorization scheme includes: Perform topological sorting on each node in the initial vectorization scheme so that each node is located after its corresponding parameter node after sorting; determine whether each node is a redundant node by detecting the node identifier of the parameter node corresponding to each node; set the node identifier of each redundant node to be unvectorizable, and set the node identifier of the parameter node corresponding to the redundant node to be a deletion identifier.

[0011] In one embodiment of this application, performing optimal segmentation on the current instruction group based on the evaluation score matrix of the current instruction group includes: Each instruction in the current instruction group is paired up to form paired instruction groups; based on each paired instruction group, a pairing set is generated; based on each paired instruction group, instruction segmentation is performed iteratively to obtain a first segmentation set, a second segmentation set, and a total segmentation evaluation score corresponding to each paired instruction group; the maximum value among the total segmentation evaluation scores corresponding to each paired instruction group is selected, and the paired instruction group corresponding to the maximum value is taken as the optimal pairing group of the current instruction group, and the first segmentation set and the second segmentation set corresponding to the optimal pairing group are taken as the first sub-instruction group and the second sub-instruction group of the current instruction group; wherein, the evaluation score matrix is ​​an evaluation matrix constructed based on the affinity between instructions, used to guide the grouping of instruction groups.

[0012] In one embodiment of this application, the step of extracting redundant nodes from each node by detecting the node identifier of the parameter node corresponding to each node includes: Based on the topologically sorted nodes, traverse each node in the vectorization scheme in the order of arrangement, and determine whether the node identifier of the node itself is a reduced VF identifier; if so, further determine whether the node identifier of the corresponding parameter node is an unvectorizable identifier; if so, set the node as a redundant node.

[0013] In one embodiment of this application, the vectorization compilation of the program block based on the final vectorization scheme includes: Perform topological sorting on each node in the final vectorization scheme, so that each node is placed after all its corresponding parameter nodes; rearrange the execution order of each instruction in the program block so that the instructions contained in the instruction group corresponding to the node are brought together; and perform corresponding vectorization transformation on the instruction sequence after the execution order is rearranged according to the node identifier of each node after topological sorting in the final vectorization scheme.

[0014] In one embodiment of this application, the rearrangement of the execution order of each instruction in the program block includes: Initialize an empty instruction sequence; filter out irrelevant instructions from the program block, and add the irrelevant instructions to the instruction sequence while maintaining their original order; wherein, the irrelevant instructions are those not included in the instruction group corresponding to any node; perform positional rearrangement based on the instruction sequence for the instructions corresponding to each node in the final vectorization scheme, including: accessing each node in the final vectorization scheme sequentially according to the topological sorting order; taking the node accessed in a single instance as the current node, and taking the instruction group corresponding to the current node as the current instruction group; for the current node, using a forward search order, searching for a target position instruction that meets preset conditions in the current instruction sequence, and inserting each instruction in the current instruction group corresponding to the current node before the target position instruction; wherein, the preset conditions include: the target position instruction depends on an instruction in the current instruction group, and the target position instruction is the earliest searched instruction.

[0015] Furthermore, the present invention also provides a terminal, comprising: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal performs the automatic vectorization compilation method as described in any one of claims 1 to 9.

[0016] As described above, the automatic vectorization compilation method, terminal, and computer storage medium provided by this invention can dynamically adjust the VF according to the structure of the optimized program. Compared with the prior art, it can adapt to more complex program structures, make full use of SIMD registers of different capacities and corresponding arithmetic instructions, and improve program throughput, thereby effectively improving the vectorization compilation efficiency of the program. In addition, it avoids the problem space of combinatorial scale, and corrects malformed program structures through redundant structure rewriting, further improving the vectorization compilation efficiency of the program. Attached Figure Description

[0017] Figure 1 The diagram shows a directed acyclic graph corresponding to the vectorization scheme in this invention. Figure 2 The diagram shown is a flowchart of the automatic vectorization method for compilation provided by the present invention in one embodiment; Figure 3 This is a flowchart illustrating the execution of step S100 in this invention. Figure 4 This is a schematic diagram illustrating the execution flow of the vector design based on the SIMD determination result for a single seed instruction group in this invention. Figure 5 This is a flowchart illustrating the execution of step S300 in this invention. Figure 6The diagram shows a flowchart illustrating the implementation of vectorized compilation of program blocks based on the final vectorization scheme described in this invention. Figure 7 This is a flowchart illustrating the execution of step S402 in this invention. Figure 8 This is a schematic diagram illustrating the process of performing optimal segmentation on the current instruction group based on the evaluation score matrix of the current instruction group, as described in this invention. Figure 9 The diagram shows a flowchart of the instruction segmentation process described in this invention during a single execution process. Figure 10 The diagram shown is a structural schematic of a terminal provided by the present invention in one embodiment. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] To address the technical problems existing in the prior art, the automatic vectorization method provided in this application constructs a vectorization scheme for the program to be compiled using an evaluation score matrix, and evaluates the program performance corresponding to the vectorization scheme using a cost model to obtain a final vectorization scheme with improved program performance; based on the final vectorization scheme, the scalar instruction set in each instruction group of the final vectorization scheme is replaced with the corresponding SIMD instructions to realize the automatic vectorization compilation process of the program to be compiled.

[0021] The vectorization scheme is a replacement scheme that replaces each scalar instruction in the program with SIMD operation instructions.

[0022] In this embodiment, the vectorization scheme is as follows: Figure 1 As shown, this is a directed acyclic graph; nodes represent a set, and edges represent dependencies. like Figure 1As shown, the nodes (rectangles) in the figure represent scalar instruction groups that can be merged into a single SIMD instruction, that is, a group of original scalar instructions that can be replaced by a single SIMD operation instruction; for example, the scalar instructions include scalar memory access, scalar unary operation, or scalar binary operation; the edges between two adjacent nodes in the figure are used to represent the dependencies between the scalar instructions corresponding to the adjacent nodes.

[0023] Each node satisfies the following characteristics: 1) For scalar instruction groups mapped to a single SIMD operation instruction (single node), the operation types of each instruction are the same, and the operation has the same parameter structure, including at least: the number of parameters is the same, and the data width of the parameters is the same.

[0024] Based on the extension method of the Use-Def Chain, obtain the position N of each parameter on the UD chain; then there must exist another node B in the graph, which contains one and only such instruction: the result of the operation of the instruction is used as the parameter at this parameter position by some instruction in node A; based on this, establish the dependency of A on B, and call the Nth parameter node of A B. 2) For node A mapped to the rearrangement instruction, it always includes two parameter nodes, namely the first parameter node and the second parameter node, which point to the first instruction group (node ​​instruction group) and the second instruction group (node ​​instruction group) respectively; wherein, the first instruction group and the second instruction group are the two sub-instruction groups (node ​​instruction groups) formed after the original instruction group (node ​​instruction group) corresponding to node A is divided according to the VF reduction partitioning scheme. 3) There should be no dependencies or parameters for other types of nodes.

[0025] For each node, insert the corresponding SIMD execution instruction according to the type of each node; and determine the dependency relationship between the SIMD operation instructions corresponding to each node according to the dependency relationship between each node. That is, for a single node, the Nth parameter of the SIMD instruction corresponding to that node is the operation result of the SIMD operation instruction corresponding to the Nth parameter node of that node.

[0026] Each of the nodes contains a type identifier, which is used to characterize the node type corresponding to the node. In one embodiment, the type identifier includes: 1) unvectorizable identifier; 2) reduced VF vectorizable identifier; 3) normal vectorizable identifier; 4) deletion identifier.

[0027] Specifically, the unvectorizable identifier is used to indicate that the instruction group corresponding to the node is an execution group that cannot be vectorized; The reduced VF vectorization identifier is used to characterize that the instruction group corresponding to the node is the instruction group that performs reduced VF segmentation; The normal vectorization identifier is used to indicate that the instruction group corresponding to the node is an instruction group that performs normal vectorization; The deletion identifier is used to indicate that the instruction group corresponding to the node is an instruction group that should be ignored and not processed.

[0028] Please see Figure 2 The diagram shows a flowchart of the automatic vectorization method for compilation provided by the present invention in one embodiment.

[0029] like Figure 2 As shown, the method includes: S100: Extract various sub-instruction groups from the program block, and construct an instruction group queue based on the extracted sub-instruction groups; The seed instruction group is a set of Store instructions in a program block that have consecutive access addresses and access data types. Different seed instruction groups are independent of each other, that is, the Store instructions contained in various sub-instruction groups are different, and there is no dependency relationship between the Store instructions within the seed instruction group.

[0030] Specifically, the access data type and access address corresponding to each Store instruction in the program block are obtained; Store instructions with the same access data type and consecutive access addresses are grouped into the same seed instruction group to construct several seed instruction groups, and the dependencies between Store instructions in each sub-instruction group are checked in turn. When it is found that there is a dependency between Store instruction A contained in the current seed instruction group and Store instruction B in the previous seed instruction group, the current seed instruction group is deleted. The dependencies include, but are not limited to, parameter dependencies, memory dependencies, indirect dependencies, or other existing dependencies. For example, for parameter dependencies, such as a = b + c, parameter a depends on parameter b, and parameter a also depends on parameter c. For memory dependencies, for example: a = store x b = store x In the formula, x represents a memory address; therefore, b depends on a.

[0031] In one specific implementation, when step S100 is executed, as follows: Figure 3 As shown, it includes the following sub-steps: S101, Obtain each Store instruction in the program block; S102, divide each Store instruction into several initial instruction groups according to the dependencies between instructions; Specifically, for a single Store instruction, it checks whether there is a dependency relationship between the Store instruction and other Store instructions; it extracts other Store instructions that do not have a dependency relationship with the current Store instruction, that is, it obtains other Store instructions that can be executed in parallel with the current Store instruction, and divides the current Store instruction and other Store instructions that can be executed in parallel into a set, thereby obtaining an initial instruction group; Continue this step for the remaining Store instructions to obtain the initial instruction groups.

[0032] S103, based on the continuity of the access address and the data type of the access data, each of the initial instruction groups is split to obtain various sub-instruction groups.

[0033] Specifically, for a single initial instruction group, the access address and access data type of each Store instruction in the initial instruction group are extracted; it is determined whether the corresponding access addresses are consecutive and whether the corresponding access data types are the same; Store instructions with consecutive access addresses and the same access data types are grouped into the same group as seed instruction groups in the initial instruction group; this process is performed for each initial instruction group to obtain various sub-instruction groups.

[0034] In this application, the instructions within a single seed instruction group are arranged in the order of their corresponding access addresses; wherein, the access addresses are continuous because the access addresses corresponding to each Store instruction cover a continuous (i.e., uninterrupted) memory space, and each address segment in the memory space is accessed only once.

[0035] More specifically, for a group of Store instructions, the access address continuation means that the access addresses of adjacent Store instructions are consecutive after the Store instructions in the group are sorted from smallest to largest according to their access addresses; that is, the access address of the next Store instruction is the sum or minus the access data size of the access address of the previous Store instruction. For example, for Store instructions A and B, when the access address of Store instruction A is 0x100 and the access address of Store instruction B is 0x104, the corresponding access data size of both is 4 bytes, that is, the address of instruction B is the access address of instruction A (0x100) plus 4 bytes (0x104); based on this, instructions A and B are determined to be instructions with consecutive access addresses.

[0036] After obtaining each seed instruction group, the various sub-instruction groups are arranged to obtain an instruction group queue; optionally, a last-in-first-out stack method is used to arrange the various sub-instruction groups; it should be noted that in other embodiments, other methods can also be used to arrange the various sub-instruction groups.

[0037] In some optional embodiments, after obtaining each seed instruction group, the length corresponding to each seed instruction group is obtained; seed instruction groups with a length less than a preset length threshold are discarded to further improve the vectorization efficiency of the program block; wherein, the length corresponding to the seed instruction group is the number of Store instructions contained in the seed instruction group.

[0038] S200, For each sub-instruction group in the instruction group queue, perform vector design based on the SIMD decision result to obtain the overall initial vector scheme; The vector design based on the SIMD determination result involves sequentially performing SIMD determination on each associated instruction group in the seed instruction group, updating the vectorization scheme corresponding to the seed instruction group according to the determination result, and obtaining the initial vectorization scheme of the seed instruction group after the vectorization design is completed; and summarizing the initial vectorization schemes corresponding to various sub-instruction groups to obtain the total initial vector scheme of the program block. The determination results include maintaining VF, reducing VF, and abandoning vectorization.

[0039] In one specific embodiment, the vector design based on the SIMD decision result is an iterative process involving several loops; for a single seed instruction group, the vector design based on the SIMD decision result is executed as follows: Figure 4 As shown, it includes the following sub-steps: S201, extract a new associated instruction group (which has not been SIMD determined before) from the associated instruction group queue corresponding to the current seed instruction group, and use it as the current instruction group; The associated instruction group queue is a queue pre-built based on the current seed instruction group, used to store each instruction group associated with the current seed instruction group.

[0040] It should be noted that, for the current seed instruction group, when performing the SIMD determination for the first time, the associated instruction group queue only stores the current seed instruction group, and the current seed instruction group is used as the current instruction group to execute subsequent steps.

[0041] S202, perform SIMD determination on the current instruction group, and perform corresponding update processing on the current vectorization scheme corresponding to the current instruction group according to the determination result; and when the determination result is to maintain VF or reduce VF, expand the associated instruction group queue. Specifically, before performing SIMD determination on the current instruction group, the latest vectorization scheme is obtained first, which is used as the current vectorization scheme corresponding to the current instruction group; Based on the hardware characteristics of the target hardware to be compiled, determine whether the current instruction group can be directly replaced by a single SIMD instruction, and determine whether there is a dependency relationship between the parameter instructions in the current instruction group. 1) If all conditions are met (substitutable and without dependency), then the current vectorization method (vectorization conversion method) is determined to be a scheme that preserves VF. A current node corresponding to the current instruction group is added to the current vectorization scheme. The current node is used to record the identifier of the current instruction group and to record the dependency relationship between the current instruction group and the previously recorded instruction group. For example, if the current node a records that the current instruction group contains parameters from an instruction group that has been added to the current vectorization scheme, then the node b depends on the node a (including which column of the parameter matrix of the node b where the node a is located).

[0042] After adding the current node, mark the current VF identifier on the current node (keeping the VF identifier) ​​to update the current vectorization scheme; In addition, extract each instruction parameter in the current instruction group and construct each instruction parameter into a parameter matrix corresponding to the current instruction group; wherein, the parameter matrix is ​​a matrix formed by arranging the instruction parameters contained in each instruction in the current instruction group according to the position of the instruction parameters in the instruction; In this parameter matrix, instruction parameters with the same parameter position are set to the same instruction parameter class; for example, when the instruction type corresponding to the current instruction group is a binary addition operation, the instructions included in the current instruction group include: X1+Y1; X2+Y2; ...; Xn+Yn; The parameter matrix is ​​formed by extracting the instruction parameters (X1,Y1), (X2,Y2), ..., (Xn,Yn) contained in each instruction and arranging them as follows: X1, Y1 X2, Y2 ...; Xn, Yn; In this parameter matrix, X1, X2, ..., Xn represent the first instruction parameter class; Y1, Y2, ..., Yn represent the second instruction parameter class.

[0043] Based on the instruction type of the current instruction group, each instruction parameter class in the current instruction group is subjected to a vectorizability determination. When the determination result is vectorizable, the vectorizable instruction parameter class is extracted, and the set of parameter instructions (parameter instruction group) corresponding to the vectorizable instruction parameter class is further extracted and added as a new instruction group to the current associated instruction group queue to expand the associated instruction group queue, thereby realizing the update of the associated instruction group queue.

[0044] 2) If the conditions are not met simultaneously (cannot be replaced and / or there is a dependency), then further compare the length of the current instruction group (the number of instructions it contains) with the length threshold (e.g., 2); (1) When the length of the current instruction group is greater than the length threshold, the current vectorization method is determined to be the scheme of reducing VF. The current node corresponding to the current instruction group is added to the current vectorization scheme, and the current VF identifier - the reduced VF identifier is marked on the current node. Furthermore, the current instruction group is subjected to optimal partitioning, that is, the current instruction group is divided into a first sub-instruction group and a second sub-instruction group, and the partitioned first sub-instruction group and second sub-instruction group are added to the current associated instruction group queue respectively to expand the associated instruction group queue, thereby realizing the update of the associated instruction group queue.

[0045] (2) When the length of the current instruction group is less than or equal to the length threshold, the current vectorization method is determined to be the scheme of abandoning vectorization; a current node corresponding to the current instruction group is added to the current vectorization scheme, and the current node is marked as an unvectorization identifier - abandoning vectorization identifier; In addition, the current instruction group queue remains unchanged, that is, the associated instruction group queue is not expanded.

[0046] S203, return to step S201 and repeat steps S201 to S203 until the iteration process is completed for all associated instruction groups in the current associated instruction group queue. After the iteration is completed, the latest obtained vectorization scheme is used as the initial vectorization scheme corresponding to the current seed instruction group. The above steps S200 are executed on each of the various sub-instruction groups in the instruction group queue until the recursion terminates, that is, the processing of step S200 is completed on all seed instruction groups; the initial vectorization schemes corresponding to each sub-instruction group are summarized to obtain the total initial vectorization scheme.

[0047] S300, perform redundant structure rewriting on the overall initial vectorization scheme to obtain a simplified vectorization scheme; The redundant structure rewriting involves performing redundancy determination on each node according to the connection order between nodes in the vectorization scheme and the node identifier corresponding to each node, and modifying the node identifier of the nodes determined to be redundant in order to simplify the vectorization scheme and obtain a simplified vectorization scheme.

[0048] The redundant nodes are those whose corresponding node identifiers cannot be vectorized.

[0049] Specifically, when step S300 is executed, such as... Figure 5 As shown, it includes: S301, Perform topological sorting on each node in the overall initial vectorization scheme, so that after sorting, each node is located after the parameter node corresponding to that node. Among them, parameter nodes are nodes that have a dependency relationship with the current node.

[0050] Specifically, based on the dependencies between nodes, the nodes that are depended upon are sorted after the nodes that depend on them.

[0051] S302 determines whether each node is a redundant node by detecting the node identifier of the parameter node corresponding to each node. Specifically, for each node after topological sorting, each node in the vectorization scheme is traversed in the sorting order. It is determined whether the node's own node identifier is a reduced VF identifier. If so, it is further determined whether the node identifier of the corresponding parameter node is an unvectorizable identifier. If so, the node is set as a redundant node.

[0052] S303, set the node identifier of each redundant node to be unvectorizable, and set the node identifier of the parameter node corresponding to the redundant node to be deleted, so as to obtain a simplified vectorization scheme.

[0053] S400: Using a preset cost model, calculate the scalar total execution cost and the corresponding vector total execution cost of the simplified vectorization scheme respectively; detect whether the scalar total execution cost is greater than the vector total execution cost; if so, set the simplified vectorization scheme as the final vectorization scheme, and perform vectorized compilation of the program block based on the final vectorization scheme. In this application, the cost model is formulated based on the performance characteristics of the target hardware and is used to characterize the execution cost corresponding to the execution of various types of instructions by the target hardware. The cost model is based on an instruction execution cost table pre-constructed based on the performance characteristics of the target hardware (compilation target device), including the execution cost corresponding to scalar instructions and vectorized instructions. That is, the cost model contains a correspondence table between various types of instructions and the execution cost of the target hardware. The execution cost includes, but is not limited to, instruction execution time, data flow, or other hardware indicators.

[0054] The total execution cost of the scalar is the expected benefit of vectorizing the parameter instruction group at the front edge of the SIMD instruction set according to the simplified vectorization scheme; the total execution cost of the vector is the expected benefit of vectorizing the parameter instruction group at the back edge of the SIMD instruction set according to the simplified vectorization scheme. The expected benefit is the sum of the execution costs incurred when executing instructions using the target hardware.

[0055] Specifically, the total scalar execution cost corresponding to the simplified vectorization scheme is calculated, including: For each node in the simplified vectorization scheme, obtain the execution cost corresponding to the node identifier; sum the execution costs of each node to obtain the scalar total execution cost of the simplified vectorization scheme.

[0056] Specifically, calculating the total execution cost of the vector corresponding to the simplified vectorization scheme includes: 1) When a node is to maintain the VF vectorized identifier, the execution cost of the node is the SIMD execution cost corresponding to the node instruction group corresponding to that node being replaced with a SIMD instruction; 2) When a node is a reduced VF vectorization flag, the execution cost of the node is the instruction execution cost of merging scalar data in two VF / 2 capacity SIMD registers into a single VF capacity SIMD register; 3) When a node is a non-vectorizable identifier, the execution cost of the node is the instruction execution cost of inserting VF scalar data into the SIMD register.

[0057] The relationship between the total execution cost of the scalar and the total execution cost of the vector is detected. If the total execution cost of the scalar is greater than the total execution cost of the vector, it indicates that vectorized compilation of the program block is better, and the simplified vectorization scheme is set as the final vectorization scheme. If the total execution cost of the scalar is not greater than the total execution cost of the vector, it indicates that vectorized compilation of the program block does not reduce the execution cost of the target hardware, and vectorized compilation of the program block is not performed.

[0058] In one specific embodiment, the implementation method of vectorizing the program block based on the final vectorization scheme is as follows: Figure 6 As shown, it includes: S401, Perform topological sorting on each node in the final vectorization scheme so that each node is placed after all its corresponding parameter nodes; S402 rearranges the execution order of each instruction in the program block so that the instructions contained in the instruction group corresponding to the node are brought together. Specifically, this step, when executed, such as Figure 7 As shown, it includes the following sub-steps: S4021, Initialize an empty instruction sequence (ordered). S4022, filter out irrelevant instructions from the program block, and add the irrelevant instructions to the instruction sequence while maintaining their original order; The irrelevant instruction is an instruction that is not included in the instruction group corresponding to any node; S4023, perform position rearrangement based on instruction sequence for the instructions corresponding to each node in the final vectorization scheme. Specifically, according to the topological sorting order, each node in the final vectorization scheme is accessed; the node accessed in a single instance is taken as the current node, and the instruction group corresponding to the current node is taken as the current instruction group; for the current node, a search order from front to back is adopted to search for the target position instruction Y that meets the preset conditions in the current instruction sequence, and each instruction in the current instruction group corresponding to the current node is inserted before the target position instruction Y; this step is performed for each node in the final vectorization scheme to obtain the sorted instruction sequence.

[0059] The target position instruction Y is used to instruct the instruction to be inserted to be inserted before the target position instruction Y during the insertion instruction. The preset conditions include: Condition 1): The target position instruction Y depends on a certain instruction in the current instruction group; Condition 2): The target location instruction Y is the earliest searched instruction.

[0060] It should be noted that if no target position instruction Y that meets the preset conditions is found (i.e., the instructions in the current instruction sequence do not depend on the instructions in the current instruction group), then each instruction in the current instruction group corresponding to the current node will be inserted to the end of the current instruction sequence.

[0061] It should be noted that when performing the above steps on each node in the final vectorization scheme, if the node identifier of the current node is a reduced VF identifier, then the current node is skipped and the above steps are directly iterated based on the next node.

[0062] S403, based on the node identifiers of each node after topological sorting in the final vectorization scheme, perform corresponding vectorization transformations on the instruction sequence after the execution order is rearranged. Specifically, according to the topological sorting order, each node in the final vectorization scheme is accessed, and based on the node identifier of each node, the corresponding instructions for each node are processed accordingly. When the node is identified as a deletion identifier, the instructions corresponding to that node are ignored; When the node identifier is a non-vectorizable identifier, a load instruction is generated after the instruction group corresponding to that node; the load instruction is used to load data from a scalar register to a SIMD register. When the node identifier is a reduced VF identifier, the instructions generated by the two parameter nodes of the node are taken. According to the order of the two instructions in the instruction sequence, the instruction that is relatively later in the order is selected, and a rearrangement instruction is generated after the instruction. The parameters of the rearrangement instruction are set to the instructions generated by the two parameter nodes of the current node.

[0063] When the node identifier of the current node is to retain the VF identifier, a SIMD instruction is generated after the instruction group corresponding to the node, and the parameters at each position of the SIMD instruction are set to the instruction generated by the parameter node corresponding to the current node. At the same time, all instructions contained in the instruction group corresponding to the current node are deleted.

[0064] Based on the sorting order of each instruction in the instruction sequence, each node in the final vectorization scheme is traversed to achieve vectorized compilation of program blocks based on the final vectorization scheme.

[0065] To prioritize the vectorizability of the first seed instruction set, i.e., to ensure that the optimal segmentation evaluation score calculated during the following execution process meets a preset score threshold requirement; in a specific embodiment, the implementation method of performing optimal segmentation on the current instruction set based on the evaluation score matrix of the current instruction set is as follows: Figure 8 As shown, it includes: S710: Pair each instruction in the current instruction group into two pairs to form paired instruction groups; generate a pairing set based on each paired instruction group; Specifically, for instructions A and B in the current instruction group, where A is the first instruction and B is the second instruction, they are paired in an orderly manner to form a first paired instruction group (A, B) and a second paired instruction group (B, A). Based on this, when the number of instructions in the current instruction group is N, the pairing set generated by this step contains a total of N*(N-1) paired instruction groups.

[0066] S720 performs instruction segmentation iteratively based on each paired instruction group to obtain the first segmentation set, the second segmentation set, and the total segmentation evaluation score corresponding to each paired instruction group.

[0067] Specifically, take one pairing instruction group from each pairing instruction group and set it as the current pairing instruction group; initialize the current first segmentation set, the current second segmentation set, and the current total segmentation evaluation score; After determining the current paired instruction group, the first instruction in the current paired instruction group is placed into the first segmented set, and the second instruction in the current paired instruction group is placed into the second segmented set, which are respectively used as the initial instructions of the first segmented set and the second segmented set; the remaining instructions in the current instruction group are subjected to an instruction segmentation process, which is to place each remaining instruction into the first segmented set and the second segmented set in sequence, that is, first fill the first segmented set and then fill the remaining instructions into the second segmented set.

[0068] The instruction segmentation process includes a first sub-segmentation process and a second sub-segmentation process, both of which are executed cyclically. For the first sub-segmentation process, during a single execution process, such as Figure 9 As shown, it includes the following sub-steps: S721, get the current set to be segmented, and get the first set to be segmented; Wherein, the current set to be segmented is the instruction that has not yet been placed into the first segmentation set and the second segmentation set; the current first segmentation set is the latest first segmentation set corresponding to the current first sub-segmentation process; It should be noted that when the first sub-segmentation process is executed for the first time, the current segmentation first set contains only the first instruction in the current pairing instruction group.

[0069] S722, for each instruction in the current set to be segmented, perform a first segmentation evaluation, so as to select the first optimal segmentation instruction corresponding to the current set to be segmented from each instruction according to the current first segmentation evaluation result and update the total segmentation evaluation score, and transfer the first optimal segmentation instruction to the current first segmentation set; S723, based on the updated current set to be segmented and the current first segmentation set, re-execute the first sub-segmentation process until the first exit condition is met.

[0070] Similarly, the execution process of the second sub-segmentation is the same as that of the first sub-segmentation, and in a single execution, it includes: S721', Get the current set to be segmented, and get the current second set to be segmented; Wherein, the current set to be segmented is the instruction that has not yet been placed into the first segmentation set and the second segmentation set; the current second segmentation set is the latest second segmentation set corresponding to the current second sub-segmentation process; It should be noted that when the second sub-segmentation process is executed for the first time, the current segmentation second set contains only the second instruction in the current pairing instruction group.

[0071] S722', For each instruction in the current set to be segmented, perform a second segmentation evaluation, so as to select the second optimal segmentation instruction corresponding to the current set to be segmented from each instruction according to the current second segmentation evaluation result and update the total segmentation evaluation score, and transfer the second optimal segmentation instruction to the current second segmentation set; S723', based on the updated current set to be segmented and the current second segmentation set, re-execute the second sub-segmentation process until the second exit condition is met.

[0072] Wherein, the first exit condition is that the proportion of the current segmented first set in the current instruction group is greater than a first threshold; the second exit condition is that the proportion of the current segmented second set in the current instruction group is greater than a second threshold; for example, the exit condition is that the size of the current segmented first set and the current segmented second set are both one-half of the current instruction group.

[0073] In a specific implementation, for a single instruction, the execution method of the first instruction to be segmented and evaluated includes: Set the current instruction as the current instruction to be segmented, and obtain the current first best segmentation evaluation score and the current first best segmentation instruction; Obtain the current evaluation score matrix; based on the evaluation score matrix, query the pairing scores between the current instruction to be segmented and each instruction in the current first segmentation set, so as to construct a pairing score set corresponding to the current instruction to be segmented, and set the minimum value in the pairing score set as the current first evaluation score corresponding to the current instruction to be segmented; The evaluation score matrix is ​​an evaluation matrix constructed based on the affinity between instructions. It is used to guide the grouping of instruction groups. That is, given a group of instructions that cannot be directly vectorized (there is no corresponding SIMD instruction), it is divided into two groups (reducing VF). In the grouping process, at least one of the two sub-instruction groups should be able to continue to be vectorized. The evaluation score matrix is ​​used to guide which instructions should be placed in a sub-instruction group in such a process.

[0074] Specifically, it checks whether the current first evaluation score is invalid or whether it is greater than the current first optimal segmentation evaluation score. If so, it updates the first optimal segmentation evaluation score and the first optimal segmentation instruction based on the current first evaluation score and the current segmentation instruction, respectively. That is, it sets the current first evaluation score to the new first optimal segmentation evaluation score and the current segmentation instruction to the new first optimal segmentation instruction. If not, it does not update the first optimal segmentation instruction and the first optimal segmentation evaluation score.

[0075] For each instruction in the current set to be segmented, the first segmentation evaluation process described above is executed to obtain the first optimal segmentation instruction and the corresponding first optimal segmentation evaluation score for the current set to be segmented. That is, when the first segmentation evaluation process for the current set to be segmented is completed, the first optimal segmentation instruction and the first optimal segmentation evaluation score are finally output. The first optimal segmentation instruction is then added to the current first segmentation set, and the first optimal segmentation evaluation score is added to the current total segmentation evaluation score to obtain a new current total segmentation evaluation score.

[0076] It should be noted that, when the first segmentation evaluation process is executed for the first time, the segmentation set is the current instruction group, which is the remaining instruction set after subtracting the current segmentation first set and the current segmentation second set respectively; and when the first segmentation evaluation process is executed for the first time, the initial first optimal segmentation instruction and the initial first optimal segmentation evaluation score are set to invalid values, that is, the first optimal segmentation instruction and the first optimal segmentation evaluation score corresponding to the current segmentation set are initialized.

[0077] Similarly, in a specific implementation, for a single instruction, the execution method of the second instruction to be segmented and evaluated includes: Set the current instruction as the current instruction to be segmented, and obtain the current second best segmentation evaluation score and the current second best segmentation instruction; Obtain the current evaluation score matrix; based on the evaluation score matrix, query the pairing scores between the current instruction to be segmented and each instruction in the current second segmentation set, so as to construct a pairing score set corresponding to the current instruction to be segmented, and set the minimum value in the pairing score set as the current second evaluation score corresponding to the current instruction to be segmented; Check whether the current second evaluation score is invalid or greater than the current second optimal segmentation evaluation score. If so, update the second optimal segmentation evaluation score and the second optimal segmentation instruction based on the current second evaluation score and the current segmentation instruction, respectively. That is, set the current second evaluation score as the new second optimal segmentation evaluation score and the current segmentation instruction as the new second optimal segmentation instruction. If not, do not update the second optimal segmentation instruction and the second optimal segmentation evaluation score.

[0078] For each instruction in the current set to be segmented, the above-mentioned second segmentation evaluation process is executed to obtain the second optimal segmentation instruction and the corresponding second optimal segmentation evaluation score for the current set to be segmented. That is, when the second segmentation evaluation process for the current set to be segmented is completed, the final output is the second optimal segmentation instruction and the second optimal segmentation evaluation score. The second optimal segmentation instruction is then added to the current second segmentation set, and the second optimal segmentation evaluation score is added to the current total segmentation evaluation score to obtain a new total segmentation evaluation score.

[0079] It should be noted that, during the first execution of the second segmentation evaluation process, the segmentation set is the current instruction group, which is the remaining instruction set after subtracting the current segmentation first set and the current segmentation second set respectively; and during the first execution of the second segmentation evaluation process, the initial second optimal segmentation instruction and the initial second optimal segmentation evaluation score are set to invalid values, that is, the second optimal segmentation instruction and the second optimal segmentation evaluation score corresponding to the current segmentation set are initialized.

[0080] In one optional embodiment, the method for obtaining the evaluation score matrix includes: 1) Pair each instruction in the current instruction to be split into pairs to obtain the paired instruction pairs; Specifically, the instruction pairing process is an unordered pairing process, that is, the pairing order between instructions is not considered; for example, for instruction A and instruction B, after pairing, there is only one instruction pair.

[0081] 2) Using the evaluation model, calculate the evaluation score of each instruction pair, and construct the current evaluation score matrix based on the evaluation scores corresponding to each instruction pair; First, construct a set of matching pairs corresponding to each instruction pair; For a single instruction pair, establish an initial set along the Use-Def chain; wherein the initial set contains several pairs of instructions (X, Y). For a single instruction pair (X, Y), check if the operation types of the instruction pair (X, Y) are the same. If the operation types are the same, then according to the parameter matrix, obtain the parameter instruction groups associated with the instruction pair (X, Y) (consisting of the two instructions at each parameter position of the instruction pair); then treat each parameter instruction group as a new instruction pair and add it to the initial set; for each instruction pair (X, Y) in the initial set, perform the above process until no new instruction pair is added to the initial set, and then use the initial set at this time as the matching pair set corresponding to the current instruction pair.

[0082] Secondly, based on the set of matching pairs, the matching score corresponding to each instruction pair is calculated using an evaluation model; The evaluation model includes a mapping relationship between the operation type and the evaluation score.

[0083] For a single instruction pair, after obtaining the matching pair set corresponding to the instruction pair, for each pair of instructions in the matching pair set, the evaluation score corresponding to the instruction pair is calculated using the evaluation model, and the evaluation scores corresponding to each pair of instructions are accumulated to obtain the total evaluation score; the total evaluation score is used as the pairing score corresponding to the instruction pair.

[0084] This step is performed on each instruction pair to obtain the pairing score corresponding to each instruction pair; based on the pairing score corresponding to each instruction pair, the current evaluation score matrix is ​​constructed.

[0085] S730, select the maximum value from the total evaluation scores of the segmentation corresponding to each pairing instruction group, take the pairing instruction group corresponding to the maximum value as the optimal pairing group of the current instruction group, and take the first set of segmentation and the second set of segmentation corresponding to the optimal pairing group as the first sub-instruction group and the second sub-instruction group of the current instruction group.

[0086] To address the problems existing in the prior art, the present invention also provides a terminal, please refer to [link / reference]. Figure 10 A schematic diagram of the structure of the terminal described in this invention is shown; as follows: Figure 10 As shown, the terminal 5 includes a memory 51 and a processor 52 connected to each other; the memory 51 is used to store computer programs, and the processor 52 is used to execute the computer programs stored in the memory, so that when the terminal is executed, it can implement the steps in the automatic vectorization method described in the above embodiment.

[0087] Optionally, the number of memories can be one or more, and the number of processors can be one or more.

[0088] Optionally, the processor in the terminal loads one or more instructions corresponding to a program process into the memory according to the steps in the automatic vectorization method described in the above embodiment, and the processor runs the program stored in the memory, thereby realizing the functions in the automatic vectorization method described above, which will not be elaborated here.

[0089] It should be noted that memory includes, but is not limited to, random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage device. Similarly, processors can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0090] Furthermore, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when invoked by a processor, implements the various steps of the automatic vectorization method described above.

[0091] A computer-readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, and mechanical encoding devices.

[0092] The computer-readable program described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. A network adapter card or network interface in each computing / processing device receives computer-readable program instructions from the network and forwards these instructions to the computer-readable storage medium in the respective computing / processing device.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of compiling automatic vectorization, the method comprising: The method comprises the following steps: extracting various sub-instruction groups in a program block, constructing an instruction group queue based on the extracted various sub-instruction groups; performing vector design based on a SIMD judgment result on the various sub-instruction groups in the instruction group queue to obtain a total initial vectorization scheme; performing redundancy structure rewriting on the total initial vectorization scheme to obtain a simplified vectorization scheme; calculating a scalar total execution cost and a vector total execution cost corresponding to the simplified vectorization scheme respectively by using a preset cost model; detecting whether the scalar total execution cost is greater than the vector total execution cost, and if yes, setting the simplified vectorization scheme as a final vectorization scheme and performing vectorization compilation on the program block based on the final vectorization scheme.

2. The method of claim 1, wherein, The implementation of the step of extracting various sub-instruction groups in a program block comprises the following steps: obtaining each Store instruction in the program block; and dividing each Store instruction into several initial instruction groups according to the dependency relationship between instructions; splitting each initial instruction group according to the continuity of the access address and the data type of the accessed data to obtain various sub-instruction groups; wherein the instructions in a single seed instruction group are arranged in the order of the access address.

3. The method of claim 1, wherein, For a single seed instruction group, the implementation of the step of performing vector design based on a SIMD judgment result comprises the following steps: extracting a new associated instruction group from an associated instruction group queue corresponding to the current seed instruction group as a current instruction group; wherein the associated instruction group queue is a queue constructed in advance based on the current seed instruction group and used for storing instruction groups associated with the current seed instruction group; performing SIMD judgment on the current instruction group, performing corresponding update processing on a current vectorization scheme corresponding to the current instruction group according to the judgment result, and performing expansion processing on the associated instruction group queue when the judgment result is to maintain VF or reduce VF; iteratively updating the current instruction group until all associated instruction groups in the current associated instruction group queue complete the iteration process; and taking the latest obtained vectorization scheme as an initial vectorization scheme corresponding to the current seed instruction group.

4. The method of claim 3, wherein, The step of performing SIMD judgment on the current instruction group and updating the current vectorization scheme corresponding to the current instruction group according to the judgment result comprises the following steps: judging whether the current instruction group can be directly replaced by a single SIMD instruction according to the hardware characteristics of the target hardware, and judging whether there is a dependency relationship between the parameter instructions in the current instruction group; if both conditions are met, it is determined that the current vectorization mode is to maintain VF, a current node corresponding to the current instruction group is added to the current vectorization scheme, and the current node is marked with a VF maintenance identifier. If the above conditions are not met, further compare the size relationship between the length of the current instruction group and the length threshold value; when greater than the length threshold value, determine that the current vectorization mode is reduced VF, add a current node corresponding to the current instruction group in the current vectorization scheme, and mark the current node as a reduced VF identifier; when less than or equal to the length threshold value, determine that the current vectorization mode is abandoned vectorization; add a current node corresponding to the current instruction group in the current vectorization scheme, and mark the current node as an abandoned vectorization identifier.

5. The method of claim 4, wherein, The expansion processing of the associated instruction group queue comprises: When the current vectorization mode is the maintained VF, extract each instruction parameter in the current instruction group, and construct each instruction parameter as a parameter matrix corresponding to the current instruction group; in the parameter matrix, set each instruction parameter with the same parameter position as a same instruction parameter class; according to the instruction type of the current instruction group, execute the vectorable determination on each instruction parameter class in the current instruction group one by one, so as to extract the vectorable instruction parameter class when the determination result is vectorable, and further extract the set of parameter instructions corresponding to the vectorable instruction parameter class as a new instruction group added to the current associated instruction group queue; and, When the current vectorization mode is the reduced VF, execute optimal segmentation on the current instruction group to obtain a first sub-instruction group and a second sub-instruction group; add the segmented first sub-instruction group and the second sub-instruction group to the current associated instruction group queue respectively.

6. The method of claim 1, wherein, The implementation mode of the redundant structure rewriting of the initial vectorization scheme comprises Perform topological sorting on each node in the initial vectorization scheme, so that each node after sorting is located after the parameter node corresponding to the node; Determine whether each node is a redundant node by detecting the node identifier of the parameter node corresponding to each node Set the node identifier of each redundant node itself as non-vectorable, and set the node identifier of the parameter node corresponding to the redundant node as a deletion identifier.

7. The method of claim 5, wherein the vectorization is performed by a compiler. The optimal segmentation of the current instruction group based on the evaluation score matrix of the current instruction group comprises: Pair each instruction in the current instruction group two by two to form each paired instruction group; generate a pairing set based on each paired instruction group; Based on each paired instruction group, execute instruction segmentation in an iterative manner to obtain a segmentation first set, a segmentation second set and a segmentation total evaluation score corresponding to each paired instruction group; According to the maximum value selected from the segmentation total evaluation scores corresponding to each paired instruction group, take the paired instruction group corresponding to the maximum value as an optimal paired group of the current instruction group, and take the segmentation first set and the segmentation second set corresponding to the optimal paired group as a first sub-instruction group and a second sub-instruction group of the current instruction group; wherein The evaluation score matrix is an evaluation matrix constructed according to the affinity between instructions, used to guide the grouping of instruction groups.

8. The method of claim 1, wherein, The vectorization compilation of the program block based on the final vectorization scheme comprises: topology sorting is performed on each node in the final vectorization scheme, so that each node is arranged after all parameter nodes corresponding to the node; the execution order of each instruction in the program block is rearranged, so that each instruction in the instruction group corresponding to the node is gathered together; according to the node identifier of each node in the final vectorization scheme after topology sorting, a corresponding vectorization transformation is performed on the instruction sequence after the execution order is rearranged.

9. The method of claim 8, wherein, The rearrangement of the execution order of each instruction in the program block includes: initializing an empty instruction sequence; filtering out each irrelevant instruction in the program block, and adding each irrelevant instruction to the instruction sequence while maintaining the original order between the irrelevant instructions; wherein the irrelevant instruction is an instruction not included in any instruction group corresponding to a node; for the instructions corresponding to each node in the final vectorization scheme, position rearrangement based on the instruction sequence is performed, including: according to the order of topology sorting, each node in the final vectorization scheme is accessed in turn; the node accessed at a time is taken as a current node, and the instruction group corresponding to the current node is taken as a current instruction group; for the current node, a search order from front to back is adopted to search for a target position instruction in the current instruction sequence that satisfies a preset condition, and each instruction in the current instruction group corresponding to the current node is inserted before the target position instruction; wherein the preset condition includes that the target position instruction depends on a certain instruction in the current instruction group, and the target position instruction is the earliest searched instruction.

10. A terminal, characterized by comprising: including: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes the compilation and automatic vectorization method according to any one of claims 1 to 9.

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