Stacked chip architecture of distributed cache and chip

Abstract

The invention discloses a stacked chip architecture of a distributed cache and a chip. The stacked chip architecture comprises a logic calculation unit and a storage unit which are arranged in a stacked manner; the stacked chip architecture further comprises cache units, one cache unit is correspondingly connected with the logic calculation unit and the storage unit, the number of the cache units is multiple, and the multiple cache units are in topological connection; wherein the cache unit is used for storing a data address corresponding to the storage unit, and the logic calculation unit initiates a memory access request to the cache unit; if the memory access request hits the data address stored in the cache unit, returning the storage data of the storage unit to the logic calculation unit; and if the memory access request does not hit the data address stored in the cache unit, forwarding the memory access request to other cache units. According to the technical scheme, the requirement for high-bandwidth communication with the storage unit can be effectively met.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically to a stacked chip architecture and chip for distributed cache. Background Technology

[0002] As the number of parameters in large-scale artificial intelligence models exceeds trillions, a technology has emerged to connect logic chips and memory chips via 3D stacking to meet the bandwidth requirements of large-scale model inference. By connecting all interfaces of the memory chip to the logic computing chip, the entire memory access bandwidth of the memory chip can be provided. However, the centralized secondary cache memory widely used in current computing architectures is severely incompatible with the memory access characteristics of 3D stacked memory units, facing multiple technical challenges. The main technical problems include: First, the transmission rate of the shared bus cannot match the parallel high bandwidth of multiple memory cells in a 3D stacked memory unit, easily creating a bandwidth bottleneck. Second, if the centralized secondary cache is replaced with a multi-bus interface design to meet the high bandwidth requirements, it will cause physical design difficulties. Dozens of interfaces need to be connected across tens of millimeters on the computing die, resulting in complex circuit layout and severe interference, which is difficult to implement in practical engineering. Third, the traditional centralized secondary cache needs to maintain global data consistency with the primary cache. Whenever any cache line is updated, a full-array broadcast must be triggered to synchronize the data. The synchronization process not only consumes a lot of power, but also presents huge physical difficulties in the signal transmission across the entire chip, further restricting the performance of the 3D stacked architecture. In summary, the existing cache structure cannot meet the high bandwidth requirements of 3D stacked memory units. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a stacked chip architecture that can effectively match the high-bandwidth communication requirements of memory units.

[0004] This application provides a stacked chip architecture, the stacked chip architecture comprising:

[0005] Stacked logical computing units and storage units;

[0006] A cache unit, one of which is connected to the logical computing unit and the storage unit, and multiple cache units are provided, with topological connections between the cache units of the multiple computing cores;

[0007] The cache unit is used to store the data address of the corresponding storage unit, and the logical calculation unit initiates a memory access request to the cache unit.

[0008] If the memory access request belongs to the address area of ​​the data stored in the storage unit, then the cache unit is checked to see if the cache is hit. If the cache is hit, the data is returned directly. If the cache is not hit, the storage unit is accessed further, and then the stored data of the storage unit is returned to the logical calculation unit.

[0009] If the memory access request does not belong to the address range of the data stored in the storage unit, the memory access request will be forwarded to other cache units.

[0010] In one aspect, the cache unit includes:

[0011] An input arbitrator is connected to the logical computing unit. The input arbitrator is used to receive memory access requests belonging to the corresponding logical computing unit and requests forwarded from other cache units, and to forward the memory access requests of the logical computing unit to other cache units.

[0012] A buffer memory, which is connected to the input arbitrator and the storage unit.

[0013] In one aspect, the buffer memory includes a multi-path parallel cache group.

[0014] In one aspect, the stacked chip architecture also includes an on-chip connectivity network for topological connections between multiple cache units, the on-chip connectivity network including multiple routing nodes connected to cache units, the routing nodes being used to forward memory access requests.

[0015] In one aspect, the topology of the on-chip interconnect network is any one of a two-dimensional grid topology, a ring topology, or a crossbar topology.

[0016] In one aspect, the stacked chip architecture further includes an adapter die disposed between the logic computing unit and the memory unit, the adapter die being connected to the through-silicon vias of the logic computing unit and the memory unit, respectively;

[0017] The cache units are all located at the same level as the logical computing units;

[0018] Alternatively, some of the cache units may be configured on the same layer as the adapter die, while other cache units may be configured on the same layer as the logic computing unit;

[0019] Alternatively, all of the cache units may be configured on the same layer as the adapter die.

[0020] In one aspect, a portion of the logic circuitry of the logic computing unit is disposed on the adapter die.

[0021] In one aspect, the storage units are stacked in multiple layers, and the logical computing units are stacked in multiple layers.

[0022] In one aspect, the stacked chip architecture includes a controller;

[0023] The controller connects the input arbiter and the storage unit, which includes a multi-path parallel storage group.

[0024] To address the aforementioned issues, this application also provides a chip comprising the stacked chip architecture described above, wherein the storage unit is one of a static random access memory (SRAM), a dynamic random access memory (DRAM), flash memory, a resistive random access memory (RRAM), or a magnetoresistive random access memory (MAM).

[0025] The beneficial effects of this invention are as follows: by setting up multiple stacked logic computing units and storage units, configuring a cache unit for each corresponding connected logic computing unit and storage unit, and connecting multiple cache units in a topology, when a logic computing unit accesses memory, it prioritizes hitting the local cache unit to obtain data, and forwards the request if it misses the cache unit. This breaks the shared bus bandwidth bottleneck to match the high bandwidth of 3D stacked storage units, avoids the problem of long-distance wiring of multiple bus interfaces, and also reduces the scope of data consistency maintenance from the entire chip to local cache units, reducing power consumption and physical implementation difficulty, thereby meeting the high bandwidth communication requirements with the storage units. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0027] Figure 1 This is a schematic diagram of one embodiment of the stacked chip architecture of this application;

[0028] Figure 2 This is a schematic diagram of another embodiment of the stacked chip architecture of this application;

[0029] Figure 3 This is a schematic diagram of the connection architecture between the cache unit and the storage unit in the stacked chip architecture of this application.

[0030] Figure 4 This is a schematic diagram of the stacked chip architecture of this application. Detailed Implementation

[0031] The embodiments of the technical solution of the present invention will now be described in detail with reference to the accompanying drawings. These embodiments are merely illustrative of the technical solution of the present invention and are therefore intended to limit the scope of protection of the present invention.

[0032] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application should have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0033] like Figure 1 and Figure 3 As shown, this application provides a stacked chip architecture, which includes: stacked logic computing units 10 and storage units 30; multiple logic computing units 10 are provided to adapt to the multi-task parallel processing requirements of 3D stacked chips, such as multi-core, multi-threaded computing of large AI models. The stacked logic computing units 10 and storage units 30 shorten the distance between computing and storage through physical stacking, avoiding data transfer losses in storage-computation separation architecture from a hardware structure perspective.

[0034] The stacked chip architecture also includes cache units 20. Each cache unit 20 connects to the logic computing unit 10 and the storage unit 30. Multiple cache units 20 are configured and interconnected topologically. The logic computing unit 10 is responsible for performing specific computational tasks, such as matrix operations in AI inference and logical judgments in data processing. The storage unit 30 is used to store the raw data, intermediate computation results, and final data required by the logic computing unit 10. The cache unit 20 acts as a data bridge connecting the logic computing unit 10 and the storage unit 30. The cache unit 20 stores the data corresponding to the storage unit 30 and constructs address indexes for the local storage unit 30.

[0035] Storage unit 30 can be Dynamic Random Access Memory (DRAM). A DRAM Bank is a collection of relatively independent storage regions divided within a DRAM chip, serving as the basic unit for DRAM read and write operations. A DRAM chip typically contains multiple DRAM Banks, and cache unit 20 is a cache tile.

[0036] The cache unit 20 is used to cache the data of the corresponding storage unit 30 and record the address. When the logic calculation unit 10 initiates a memory access request to the cache unit 20, the cache unit 20 includes an input arbitrator 210 and a buffer memory 220. If the memory access request address is located in the storage unit 30 connected to the current cache unit 20, the input arbitrator 210 will continue to send the request to the buffer memory 220.

[0037] If the buffer memory 220 contains the requested buffer input data (i.e., the address is the same), then the data stored in the buffer unit 20 is hit, and the stored data in the buffer memory 220 is returned to the logic calculation unit 10. If the buffer memory 220 does not contain the requested buffer input data, then the buffer memory 220 initiates a data request to the storage unit 30. The storage controller 50 further parses the request, accesses the storage unit 30 through a through-silicon via (TSV), obtains the data, and returns it to the buffer memory 220. At this time, if the buffer memory 220 contains the requested buffer input data, it returns the stored data to the logic calculation unit 10.

[0038] In simple terms, when the logical computing unit 10 achieves a memory hit, it directly returns the data from the cache unit 20 without accessing the data in the storage unit 30. When a memory hit occurs, it then accesses the storage unit 30. A memory access request is a data interaction instruction between the logical computing unit 10, the cache unit 20, and the storage unit 30. When performing a computational task, the logical computing unit 10 initiates a request to the cache unit 20 or the storage unit 30 to access or store data.

[0039] If the memory access request address is located in another storage unit 30, the input arbitrator 210 forwards the memory access request to the other cache unit 20 via the routing node 40. When data is stored in another storage unit 30, the request is forwarded to the other cache unit 20, and cross-core data lookup is achieved by relying on the topological connection between cache units 20.

[0040] Meanwhile, the dedicated binding of cache unit 20 to the corresponding logical computing unit 10 allows each cache unit 20 to serve only the storage and computing needs of a single logical computing unit 10, eliminating the need to maintain full chip data consistency, avoiding the high power consumption of traditional centralized cache global broadcast synchronization, and further simplifying hardware design.

[0041] In this embodiment, by setting up multiple stacked logical computing units 10 and storage units 30, a cache unit 20 is configured for each corresponding connected logical computing unit 10 and storage unit 30, and the multiple cache units 20 are topologically connected. When the logical computing unit 10 accesses memory, it first determines whether the data belongs to the local storage unit 30 based on the address. If it does, it enters the cache unit 20 and obtains the data from the local cache unit 20 first. If the address request does not belong to the local storage unit 30, the request is forwarded to the cache unit 20 connected to the target storage unit 30.

[0042] In this embodiment, the cache unit 20 and the storage unit 30 are matched one-to-one to form a distributed design, which breaks the bottleneck of shared bus bandwidth to match the high bandwidth of 3D stacked storage unit 30, avoids the problem of long-distance winding of multiple bus interfaces, and also reduces the scope of data consistency maintenance from the whole chip to the local cache unit 20, reducing power consumption and physical implementation difficulty, thereby matching the high bandwidth communication capability of 3D stacked storage unit 30.

[0043] In one embodiment of this application, the cache unit 20 includes an input arbitrator 210, a routing node 40, and a buffer memory 220.

[0044] Input arbitrator 210 is connected to logic computing unit 10. Input arbitrator 210 is used to receive memory access requests from the corresponding logic computing unit 10 or forward memory access requests from other cache units 20. Input arbitrator 210 and buffer memory 220 work together to support the request scheduling and data temporary storage functions of cache units 20. Input arbitrator 210 is responsible for distributing the flow path of memory access requests. If the address matches the current storage unit 30 region, it is output to the current buffer memory 220; otherwise, it is forwarded to the routing node 40. At the same time, input arbitrator 210 is also responsible for preventing conflicts between forwarded requests and local requests arriving at the same time. It selects only one request and sends it to buffer memory 220, and selects the other request at the next moment. Buffer memory 220 is responsible for temporarily storing the data of the storage unit 30 connected to it. Through the temporal and spatial locality of memory access, it shortens the data access latency.

[0045] The buffer memory 220 connects the input arbiter 210 and the storage unit 30. Traditional storage-operation separation architectures consume significant power during data transfer. In this application, the buffer memory 220 acts as a bridge between the input arbiter 210 and the storage unit 30. On one hand, it receives memory access requests from the input arbiter 210. When a request is successful, it directly locates the data from the corresponding data address in its temporary storage unit 30, eliminating the need to access the underlying storage unit 30 and significantly reducing data transfer distance from millimeters to micrometers. On the other hand, when a request is unsuccessful, it can quickly read the target data through its connection with the storage unit 30. This connection method avoids the problem of multi-interface, long-distance routing in traditional centralized caches and reduces data transfer power consumption through near-data temporary storage. Typically, the storage unit 30 can provide bandwidth of up to 100–200 GB / s.

[0046] In one embodiment of this application, the buffer memory 220 includes multiple cache groups 221. That is, the buffer memory 220 is internally divided into multiple cache groups 221, such as 4-way set-associative or 8-way set-associative. In this case, addresses with the same index in main memory will be mapped to the same group, but can be stored in cache groups 221 on different paths within the same group. Therefore, the multiple-way design allows each memory location to be mapped to multiple locations, avoiding the situation where multiple hot data items contend for the same cache group 221, allowing more frequently used data to remain in the cache, and improving the hit rate.

[0047] See Figure 2 As shown, in one embodiment of this application, the stacked chip architecture further includes an on-chip interconnection network. This network is used for topological connections between multiple cache units 20. The on-chip interconnection network includes multiple routing nodes 40, which are connected to the cache units 20 and are used to forward memory access requests. The stacked chip architecture adds an on-chip interconnection network, and the multiple routing nodes 40 within this network serve as key hubs for interaction. By directly connecting to the cache units 20, they undertake the function of forwarding memory access requests. When a memory access request received by a cache unit 20 is located in another storage unit 30, it can be forwarded to the next-level routing node through the routing node 40. This may involve multiple hops before reaching the cache unit 20 storing the target data. Relying on the distributed layout of the routing nodes 40, the architecture adapts to the physical layout structure of the vertically integrated 3D stacked chips, avoiding long-distance routing problems during direct access. This enables multiple cache units 20 to work collaboratively, matching the distributed bandwidth of the 3D stacked storage chips and meeting the overall chip requirements for low latency and high parallel memory access.

[0048] It should be noted that in one embodiment, the routing node 40 may be part of the cache unit 20, while in another embodiment, it may be independent of the cache unit 20.

[0049] In one embodiment of this application, the on-chip interconnect network topology can be any one of a two-dimensional mesh topology, a ring topology, or a crossbar topology. Different topologies can be matched to memory access requirements in different scenarios.

[0050] For example, the two-dimensional grid topology, with its row-column node arrangement, ensures a regular connection path between cache units 20, adapting to the array layout of storage units 30 in 3D stacked memory chips. It also reduces wiring complexity, avoids long-distance routing interference, and is suitable for interconnecting large-area chips. The ring topology, by connecting cache units 20 to routing nodes 40 end-to-end to form a closed loop, provides a fixed memory access request forwarding path and controllable latency, making it suitable for scenarios with high transmission stability requirements. The crossbar topology enables direct connection between any two cache units 20, eliminating the need for multi-node forwarding of requests, resulting in high bandwidth utilization and making it more suitable for interconnecting small-area chips. The selection of these three topologies ensures that the on-chip interconnect network can flexibly adapt to the computing power, bandwidth, and physical layout of different 3D stacked chips. Furthermore, the distributed request forwarding mechanism of the on-chip network ensures efficient flow of memory access requests between multiple cache units 20, providing support for the stable operation of the distributed cache architecture.

[0051] In one embodiment of this application, the stacked chip architecture further includes an adapter die, which is disposed between the logic computing unit 10 and the memory unit 30, and the adapter die is connected to the through silicon via (TSV) of the logic computing unit 10 and the memory unit 30 respectively.

[0052] The adapter die can have only a redistribution layer, or it can contain some logic, such as placing the controller 50 on the adapter die; or further, some cache units 20 can be placed on the same layer as the adapter die, and another part of the cache units 20 can be placed on the same layer as the logic computing unit 10; or, both the controller 50 and the cache units 20 can be placed on the same layer as the adapter die. In this case, the adapter die is positioned between the logic computing unit 10 and the storage unit 30, and is connected to the through-silicon vias (TSVs) of both. The adapter die can adjust the pin docking positions of the TSVs of both sides through its internal redistribution layer to adapt to the inconsistency between the computing die layout and the storage die layout.

[0053] From the layout scheme of cache unit 20, the first scheme has some cache units 20 on the same layer as the adapter die and some on the same layer as the logic computing unit 10. The second scheme has all cache units 20 on the same layer as the adapter die. Both schemes can make full use of the chip area of ​​the adapter die to increase the cache capacity and leave more area on the logic computing unit 10 for computing power. At the same time, it reduces the overall physical design complexity of the chip and is more suitable for 3D stacking scenarios with high integration requirements.

[0054] In one embodiment of this application, a portion of the logic circuitry of the logic computing unit 10 is disposed on a connecting die. The connecting die itself already serves as a connection hub between the logic computing unit 10 and the memory unit 30, undertaking functions such as through-silicon via (TSV) location adaptation and data transfer. Migrating a portion of the logic circuitry of the logic computing unit 10 to the connecting die further shortens the signal transmission distance, reduces data interaction latency, alleviates the integration pressure on the logic computing unit 10, and optimizes the overall physical layout of the chip. This also allows for full utilization of space, increasing the number of transistors per unit area at the overall chip level.

[0055] In one embodiment of this application, the storage units 30 are stacked in multiple layers, and the logic computing units 10 are stacked in multiple layers. This allows for a significant increase in storage capacity within a unit chip area. For example, in a traditional planar layout, the capacity of a single storage unit 30 is limited by the chip area, while with multiple layers, the capacity increases proportionally with the number of stacked layers, easily meeting the storage needs of trillions of parameters in AI tasks. Simultaneously, the multi-layered stacked storage units 30 can be divided into multiple independent storage partitions, each corresponding to a specific computing core, reducing cross-partition data interaction and further lowering memory access latency.

[0056] From the perspective of the multi-layer stacking of the logic computing units 10, several times the number of computing cores compared to a planar layout can be integrated within a limited space, significantly improving the overall computing power of the chip. More importantly, the multi-layer logic computing units 10 can achieve close inter-layer connections with the corresponding layer's storage units 30 through TSVs.

[0057] The dual multi-layer stacking design also optimizes the physical balance of the chip. The storage unit 30 and the logic computing unit 10 are stacked in multiple layers, and the number of stacking layers can be flexibly adjusted according to actual needs. This avoids problems such as uneven heat dissipation and signal interference caused by excessive stacking of a single type of unit. At the same time, through the topology of the on-chip interconnection network, cross-layer collaboration between different layers of computing cores and storage unit 30 is realized, so that the entire stacked chip architecture can still maintain a high-efficiency and stable operating state under high-density integration.

[0058] In one embodiment of this application, the stacked chip architecture includes a controller 50, which is connected to a cache unit 20 and a storage unit 30. The storage unit 30 specifically stores the raw data, intermediate calculation results, final results, and program instruction set required by the logic calculation unit 10. The storage unit 30 includes a multi-path parallel storage group 310.

[0059] The controller 50 achieves this through a link connecting the cache unit 20 and the storage unit 30: On the one hand, the controller 50 receives memory access requests from the input arbitrator 210 of the cache unit 20, including local requests initiated by the logic computing unit 10 and cross-core requests forwarded by other cache units 20, avoiding operational chaos caused by requests directly impacting the storage unit 30. For example, it prioritizes processing high-priority real-time requests from the logic computing unit 10, or reorders or merges requests from different addresses, reducing the number of open / close rows and invalid operations in the storage unit 30; On the other hand, the controller 50 sends read / write control signals to the storage unit 30 according to the request instructions, ensuring that the storage unit 30 can respond to requests efficiently. For example, when the logic computing unit 10 needs a batch of image feature data, the controller 50 quickly locates the target address in the storage unit 30 and transmits the data to the cache unit 20 in time order, avoiding the high latency problem caused by direct interaction of traditional storage access.

[0060] See Figure 4 As shown, Figure 4 The demonstration shows a stacked chip architecture that achieves efficient integration of logic computing unit 10 and memory unit 30 through TSV (Through Silicon Via) interconnects.

[0061] The logical computing unit 10 and the cache unit 20 are located on the same side. The logical computing unit 10 is responsible for performing various computing tasks; the cache unit 20 is used to temporarily store frequently accessed data to alleviate the contradiction between fast computing speed and slow main memory access.

[0062] The internal structure of the storage unit 30 includes multiple storage banks 310. TSV achieves electrical connections between different chip layers (computation layer, storage layer) by etching vertical vias on the chip and filling them with conductive materials (such as copper), replacing traditional planar wiring and greatly shortening the data transmission distance.

[0063] This application also provides a chip, which includes a stacked chip architecture. The stacked chip architecture includes: a stacked logic computing unit 10 and a storage unit 30; by physically stacking, the distance between computing and storage is shortened, and the data transfer loss of the storage-computation separation architecture is avoided from the hardware structure.

[0064] The stacked chip architecture also includes cache units 20, each cache unit 20 connecting a logic computing unit 10 and a storage unit 30. Multiple cache units 20 are topologically interconnected. The logic computing unit 10 is responsible for executing specific computational tasks, such as matrix operations in AI inference and logical judgments in data processing. The storage unit 30 stores the raw data, intermediate computation results, and final data required by the logic computing unit 10. The cache unit 20 acts as a data bridge connecting the logic computing unit 10 and the storage unit 30, storing data corresponding to the storage unit 30 and building address indexes for the local storage unit 30.

[0065] The cache unit 20 is used to cache the data of the corresponding storage unit 30. When the logic computing unit 10 initiates a memory access request to the cache unit 20, if the memory access request address belongs to the region of the corresponding storage unit 30, it checks whether the data address stored in the cache unit 20 is hit, and then returns the stored data of the storage unit 30 to the logic computing unit 10. When the logic computing unit 10 achieves a memory hit, it directly returns the data of the storage unit 30 without accessing the underlying storage. The memory access request is a data interaction instruction between the logic computing unit 10, the cache unit 20, and the storage unit 30. When performing a computation task, the logic computing unit 10 initiates a request to the cache unit 20 or the storage unit 30 to access or store data.

[0066] If the memory access request address belongs to the region of its storage unit 30, the memory access request is forwarded to other cache units 20. Cross-core data lookup is achieved by relying on the topological connections between cache units 20.

[0067] Meanwhile, the dedicated binding of cache unit 20 to the corresponding storage unit 30 allows each cache unit 20 to serve only the caching needs of a single storage unit 30, eliminating the need to maintain full chip data consistency and further simplifying hardware design.

[0068] Other implementations of the chip in this application refer to the stacked chip architecture described above, and will not be repeated here.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A stacked chip architecture for distributed caching, the architecture comprising: The stacked chip architecture comprises: a logic computing unit and a storage unit arranged in a stack; a cache unit, one of the cache units being connected to the logic computing unit and the storage unit, a plurality of the cache units being arranged in a topology; wherein the cache unit is configured to store data addresses of the corresponding storage unit, and the logic computing unit initiates a memory access request to the cache unit; if the memory access request belongs to an address region of the storage unit storing data, the cache unit is searched for a cache hit, and if a hit is found, the data is directly returned, otherwise, the storage unit is further accessed, and then the logic computing unit is returned with the storage data of the storage unit; if the memory access request does not belong to the address region of the storage unit storing data, the memory access request is forwarded to other cache units.

2. The stacked chip architecture of claim 1, wherein, The cache unit comprises: an input arbiter connected to the logic computing unit, the input arbiter being configured to receive a memory access request belonging to the corresponding logic computing unit and a request forwarded from other cache units, and forward the memory access request of the logic computing unit to other cache units; a buffer memory connected to the input arbiter and the storage unit.

3. The stacked chip architecture of claim 2, wherein, The buffer memory comprises a plurality of cache groups in parallel.

4. The stacked chip architecture of claim 2, wherein, The stacked chip architecture further comprises an on-chip connection network for topology connection between a plurality of the cache units, the on-chip connection network comprising a plurality of routing nodes connected to the cache units, the routing nodes being configured to forward the memory access request.

5. The stacked chip architecture of claim 4, wherein, The topology connection of the on-chip connection network is any one of a two-dimensional grid topology, a ring topology or a crossbar topology.

6. The stacked chip architecture of claim 1, wherein, The stacked chip architecture further comprises a conversion die arranged between the logic computing unit and the storage unit, the conversion die being connected to through silicon vias of the logic computing unit and the storage unit, respectively. All of the cache units and the logic computing unit are arranged in the same layer. Alternatively, part of the cache units are arranged in the same layer as the conversion die, and the other part of the cache units are arranged in the same layer as the logic computing unit. Alternatively, all of the cache units are arranged in the same layer as the conversion die.

7. The stacked chip architecture of claim 6, wherein, Part of the logic circuits of the logic computing unit are arranged on the conversion die.

8. The stacked chip architecture of claim 1, wherein, The storage unit is arranged in a plurality of layers in a stack, and the logic computing unit is arranged in a plurality of layers in a stack.

9. The stacked chip architecture of claim 2, wherein, The stacked chip architecture comprises a controller. The controller is connected to the input arbiter and the storage unit, and the storage unit comprises a plurality of storage groups in parallel.

10. A chip, characterized by The chip comprises the stacked chip architecture according to any one of claims 1 to 9, and the storage unit is one of a static random access memory unit, a dynamic random access memory unit, a flash memory, a resistive random access memory unit or a magnetoresistive random access memory unit.

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