BE-SONOS embedded memory structure and process method

Abstract

The invention discloses a BE-SONOS (Bipolar-Silicon Oxide Nitride Oxide Semiconductor) embedded memory structure. The BE-SONOS embedded memory structure comprises a selection gate, a control gate and a floating gate, the control gate is located on the floating gate, and the floating gate and the control gate are isolated by an insulating dielectric layer; the control gates and the floating gates are divided into a plurality of groups, and the selection gate is of a groove type and is positioned in the substrate between the adjacent control gate and floating gate; channel regions are formed in the substrate on the two sides of the trench-type selection gate; the floating gate is of a composite BE-SONOS multi-layer structure and sequentially comprises a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer and a third oxide layer from bottom to top. According to the invention, the characteristic that an Si dangling bond in the nitride can capture electrons and holes is utilized, the nitride is used as an electron capture layer, and a floating gate of an existing structure is replaced by a BE-SONOS structure, so that the carrier injection efficiency is relatively improved, fewer masks are used in the manufacturing process, the process time is shortened, and the manufacturing efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a BE-SONOS (Bandgap Engineered SONOS) embedded memory structure and manufacturing process. Background Technology

[0002] Embedded memory architecture is an innovative type of non-volatile memory commonly used in MCU applications. The BE-SONOS process is a semiconductor memory process that replaces the floating gate with a nitride.

[0003] The traditional embedded select trench gate flash structure includes a select gate, a floating gate, and a control gate, such as... Figure 1 The image shows a floating-gate memory. The select gate is a trench type, located in the substrate between adjacent floating gates. The floating gate is a polysilicon gate with a floating potential, located below the control gate and surrounded by an insulating dielectric layer.

[0004] Existing embedded memory manufacturing processes require a complete gate fabrication process, including film deposition and multiple photolithography steps. This process is complex, time-consuming, and costly, and the resulting memory devices generally have limited data retention capabilities. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an embedded memory that utilizes the charge trapping properties of nitrides to design a simpler BE-SONOS embedded memory structure.

[0006] To address the above problems, this invention provides a BE-SONOS embedded memory structure, comprising: The BE-SONOS embedded memory includes a select gate, a control gate, and a floating gate; The control gate is located above the floating gate, and the floating gate and the control gate are isolated by an insulating dielectric layer; The control gates and floating gates are in multiple sets, and the selection gate is trench type, located in the substrate between adjacent control gates and floating gates; a channel region is formed in the substrate on both sides of the trench type selection gate; The floating gate is a composite BE-SONOS multilayer structure, which consists of a first oxide layer, a first nitriding layer, a second oxide layer, a second nitriding layer, and a third oxide layer from bottom to top.

[0007] The semiconductor substrate is a silicon substrate or a compound semiconductor.

[0008] Furthermore, in the floating gate, the first oxide layer, the first nitride layer, and the second oxide layer constitute an ONO composite tunneling layer, the second nitride layer is a charge trapping layer to store charge carriers, and the third oxide layer is a charge blocking layer to prevent charge carriers from entering the control gate upwards.

[0009] Furthermore, in the BE-SONOS embedded memory structure, during programming / erase, the ONO composite tunneling layer experiences a band shift under a high electric field due to the high voltage. This reduces the blocking effect of the first nitride layer and the second oxide layer on charge carriers, decreases the effective physical thickness of the tunneling oxide layer, and makes it easier for electrons and holes to tunnel into the charge storage layer of the second nitride layer, thus relatively improving the charge carrier injection efficiency. During data storage, the electric field in the ONO composite tunneling layer is very small, and the energy band does not shift. The ONO multilayer structure and the increased total physical thickness of the tunnel oxide layer effectively prevent direct tunneling of electrons and holes during data retention, thus improving data retention capability.

[0010] A process method for a BE-SONOS embedded memory, comprising: An STI isolation structure is formed on a semiconductor substrate, and a well region is formed by ion implantation. Etch trenches and fill them to form a selection gate; A BE-SONOS multilayer structure is formed by deposition, wherein the BE-SONOS multilayer structure includes an ONO composite tunneling layer, a charge storage layer, and a charge blocking layer; Polysilicon is deposited and etched to form a control gate; Perform LDD injection to complete the contact process.

[0011] Furthermore, the ONO composite tunneling layer comprises, from bottom to top, a first oxide layer, a first nitride layer, and a second oxide layer; the second oxide layer may be silicon oxynitride. The charge storage layer is a second nitride layer, and the charge blocking layer is a third oxide layer.

[0012] Furthermore, the ONO composite tunneling layer is formed using a high-temperature process, which allows the gas to react fully, reduces defects and Si-SiO2 surface states in the tunneling oxide layer, and improves the quality of the deposited film. After the ONO composite tunneling layer is deposited, a high-temperature thermal annealing process is performed. The high-temperature thermal annealing mainly reduces lattice defects and improves the quality of the oxide layer and its interface by rearranging the lattice at high temperature.

[0013] Furthermore, the BE-SONOS embedded memory structure is applicable to 1.5T embedded memory structures.

[0014] Furthermore, the device is suitable for 40nm process.

[0015] The present invention provides a BE-SONOS embedded memory structure and process method, which utilizes the electron and hole trapping properties of Si dangling bonds in nitrides. The nitride is used as an electron trapping layer, and the existing floating gate is replaced by the BE-SONOS structure. The carrier injection efficiency is relatively improved, fewer masks are used in the manufacturing process, the process time is reduced, and the manufacturing efficiency is improved. Attached Figure Description

[0016] Figure 1 This is a cross-sectional schematic diagram of an existing embedded memory structure.

[0017] Figure 2 This is a cross-sectional schematic diagram of the BE-SONOS embedded memory structure provided by the present invention.

[0018] Figure 3 This is a schematic diagram of the BE-SONOS multilayer composite structure of the present invention.

[0019] Figure 4 This is the energy band diagram of each layer of BE-SONOS during the programming of the BE-SONOS embedded memory of this invention.

[0020] Figure 5 This is the energy band diagram of each layer of BE-SONOS during the erasure of the BE-SONOS embedded memory of this invention. Detailed Implementation

[0021] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] This invention proposes a novel BE-SONOS embedded memory structure, replacing the floating gate in existing embedded memories with BE-SONOS, and utilizing the charge-trapping properties of nitrides to design a simpler BE-SONOS embedded select trench memory structure. For example... Figure 2 and Figure 3 As shown. Figure 2 It includes a trench-type select gate, and control gates stacked vertically on the substrate surface, as well as a BE-SONOS composite layer that replaces the traditional floating gate. The select gate is located in the substrate between two parallel control gates, and channel regions are formed in the substrate on both sides of the select gate trench.

[0024] In this invention, the floating gate is replaced by a BE-SONOS structure. Utilizing the electron- and hole-trapping properties of Si dangling bonds in nitrides, the nitride acts as an electron-trapping layer, replacing the floating gate. For example... Figure 3 As shown, the BE-SONOS structure, compared to the single tunneling oxide layer in the traditional SONOS memory cell structure, actually uses a SONONOS stack-up structure, including... Figure 3 The layers are arranged from bottom to top as follows: O1, N1, O2, N2, O3. O1, O2, and O3 are the first oxide layer, the second oxide layer, and the third oxide layer, respectively. The second oxide layer, O2, can be silicon oxynitride. N1 and N2 are the first nitride layer and the second nitride layer, respectively. The tunnel oxide layer is an ONO composite tunneling layer composed of O1, N1, and O2.

[0025] It employs an ONO tunneling oxide layer from bandgap engineering. During programming / erase, due to the large voltage, the energy band shifts under a high electric field, reducing the blocking effect of N1 and O2 on carriers. This reduces the effective physical thickness of the tunneling oxide layer, making it easier for electrons and holes to tunnel into the SiN storage layer, thus relatively improving the carrier injection efficiency.

[0026] like Figure 4 , Figure 5 Combination Figure 3 As shown, Figure 4 The diagram shown is the band structure during BE-SONOS programming: During programming, band shifting can effectively eliminate the blocking characteristics of N1 and O2, reducing the barrier height for electron tunneling.

[0027] Figure 5 The diagram shown is the band structure during BE-SONOS erase: During the erase process, the band shift can effectively eliminate the blocking characteristics of N1 and O2, and reduce the barrier height of hole tunneling.

[0028] During data storage, the electric field in the ONO composite tunneling layer is very small, and the energy band does not shift. Due to the complex structure of ONO (silicon nitride has a higher dielectric constant than SiO2) and the increased total physical thickness of the tunnel oxide layer, direct tunneling of electrons and holes during data retention can be effectively prevented, thus improving data retention capability.

[0029] The manufacturing process of the BE-SONOS embedded memory structure described above is briefly described below: Shallow trench etching is performed on a semiconductor substrate, and an insulating dielectric layer is filled to form an STI isolation structure, defining the isolation region. Then, ion implantation is performed to form well regions, including well regions in the memory region and well regions in other regions, such as the high voltage region.

[0030] The trenches are etched and filled to form the select gate of the BE-SONOS embedded memory.

[0031] A BE-SONOS multilayer structure is deposited, comprising an ONO composite tunneling layer, a charge storage layer, and a charge blocking layer. The ONO composite tunneling layer, located on the substrate surface, comprises O1, N2, and O2 layers, where the O2 layer can be either silicon oxide or silicon oxynitride. The charge storage layer N2 is a silicon nitride layer that traps charge carriers to form data. The O3 layer is a silicon oxide blocking layer that blocks charge carriers, preventing them from penetrating the charge storage layer and reaching the control gate above, thus preventing logic errors.

[0032] It is important to note that the deposition of the ONO composite tunneling layer requires a high-temperature process. This allows the gas to react fully, reducing defects and Si-SiO2 surface states in the tunneling oxide layer, resulting in a higher quality film.

[0033] After the ONO stack is formed, a thermal annealing process is required. High-temperature thermal annealing mainly reduces lattice defects by rearranging the lattice at high temperature, thereby improving the quality of the oxide layer and its interface.

[0034] Polysilicon is deposited and etched to form a control gate; Perform LDD injection to complete the contact process.

[0035] The above embodiment is applicable to 1.5T embedded memory at the 40nm node, and is equally applicable to embedded memory at other process nodes.

[0036] The BE-SONOS embedded memory provided by this invention can significantly reduce manufacturing costs and cycle time, and improve Flashcell efficiency and data retention capabilities.

[0037] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A BE-SONOS embedded memory structure, characterized in that: the BE-SONOS embedded memory comprises a select gate, a control gate and a floating gate; the control gate is located above the floating gate, and the floating gate and the control gate are separated by an insulating medium layer; the control gate and the floating gate are in multiple groups, the select gate is in a trench type, and is located in a substrate between adjacent control gates and floating gates; a channel region is formed in the substrate on both sides of the trench type select gate; the floating gate is a composite BE-SONOS multilayer structure, and comprises, from bottom to top, a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer and a third oxide layer. The semiconductor substrate is a silicon substrate or a compound semiconductor. In the floating gate, the first oxide layer, the first nitride layer and the second oxide layer form an ONO composite tunneling layer, the second nitride layer is a charge trapping layer for storing carriers, and the third oxide layer is a charge blocking layer for blocking carriers from entering the control gate. In the BE-SONOS embedded memory structure, the ONO composite tunneling layer has a large voltage during programming and erasing, and the energy band is offset under a high electric field, the blocking effect of the first nitride layer and the second oxide layer on the carriers is reduced, the effective physical thickness of the tunneling oxide layer is reduced, and the injection efficiency of the carriers is relatively improved. During data storage, the electric field in the ONO composite tunneling layer is small, the energy band is not offset, the total physical thickness of the ONO multilayer structure and the tunneling oxide layer is increased, the direct tunneling of the electrons and the holes during data retention is effectively prevented, and the data retention capability is improved.

2. The BE-SONOS embedded memory structure of claim 1, wherein:

5. A process for manufacturing the BE-SONOS embedded memory according to claim 1, characterized in that: an STI isolation structure is formed on a semiconductor substrate, and a well region is formed by ion implantation; 3. The BE-SONOS embedded memory structure of claim 1, wherein: a trench is etched and filled to form a select gate; 4. The BE-SONOS embedded memory structure of claim 3, wherein: a BE-SONOS multilayer structure is deposited, and the BE-SONOS multilayer structure comprises an ONO composite tunneling layer, a charge storage layer and a charge blocking layer; polysilicon is deposited and etched to form a control gate; LDD implantation is performed, and a contact process is completed. The ONO composite tunneling layer comprises, from bottom to top, a first oxide layer, a first nitride layer and a second oxide layer; and the second oxide layer is silicon oxynitride. The charge storage layer is a second nitride layer, and the charge blocking layer is a third oxide layer. When the ONO composite tunneling layer is formed, a high-temperature process is used to make the gas fully react, reduce defects in the tunneling oxide layer and Si-SiO2 surface states, and improve the quality of the deposited film; after the deposition of the ONO composite tunneling layer is completed, a high-temperature thermal annealing process is performed; the high-temperature thermal annealing is mainly to reduce lattice defects by rearranging the lattice at high temperature, and improve the quality of the oxide layer and the interface. The BE-SONOS embedded memory structure is suitable for a 1.5T embedded memory structure.

6. The process method of BE-SONOS embedded memory as claimed in claim 5, wherein: The device is suitable for a 40nm process. ​ 7. The process method of BE-SONOS embedded memory as claimed in claim 5, wherein: ​ ​ 8. The BE-SONOS embedded memory structure of claim 5, wherein: ​ 9. The BE-SONOS embedded memory structure of claim 5, wherein: ​

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