Semiconductor device and manufacturing method thereof
By depositing metal layers at different temperatures in stages and using CMP technology, the inconsistency problem caused by the metal gate trench loading effect was solved, the planarization process window was expanded, and the performance of semiconductor devices was ensured.
Patent Information
- Application Number
- CN202511588007.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-01-16
AI Technical Summary
In semiconductor manufacturing, as critical dimensions shrink, the loading effect of metal gate trenches leads to inconsistencies in the top surface of the metal gate in different sized gate trench regions. Furthermore, the planarization process window is narrow, making it difficult to ensure that there are no short circuits between metal gates and to avoid some gate top surfaces being too low.
By employing a stepwise deposition of metal layers at different temperatures, a low-temperature metal layer is first deposited in the gate trench with a smaller cross-section, and then a high-temperature metal layer is deposited in the gate trench with a larger cross-section. Combined with CMP process, metal layers with different densities are formed to suppress the loading effect and ensure the consistency of the metal gate top surface in each gate trench.
This expands the process window for planarization, avoids problems such as short circuits in the metal gate and excessively low top surface, and improves the performance of semiconductor devices.
Smart Images
Figure CN121357979A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology
[0002] Traditional MOS devices use polysilicon to fabricate the gate. However, with advancements in manufacturing processes and the shrinking of critical dimensions, advanced logic processes utilize high-dielectric-constant gate dielectrics and metal gates in MOS integrated circuit manufacturing. The process typically employs a gate-last method, where a transistor structure with a polysilicon gate and source / drain regions is first formed. The polysilicon gate is then removed to form a gate trench. Metal material is deposited within this trench, and a planarization process is performed, leaving the remaining metal material within the trench to form the metal gate. Typically, a function modulation layer and a barrier layer are formed before depositing the metal material within the gate trench.
[0003] Using the above process, multiple MOS devices with metal gates can be formed on a substrate. However, research has found that after depositing metal material in the gate trench and performing a planarization process, due to the loading effect, the metal in gate trench regions of different sizes has different grinding rates because of the different upper surface areas. This results in the metal gate top surface formed in gate trenches with larger cross-sections being lower than that formed in gate trenches with smaller cross-sections. Moreover, in order to ensure that different metal gates are disconnected to avoid short circuits, the planarization process time is often increased, which can further reduce the metal gate top surface in larger gate trenches, making it easy to fail to meet requirements. In order to make different metal gates meet the requirements, the process window for the planarization process is very small. Summary of the Invention
[0004] In order to form MOS devices with different metal gate sizes on the same substrate, and to ensure that there is no short circuit between different metal gates when removing part of the metal material using the planarization process to form the corresponding metal gate in the gate trench, while avoiding the top surface of some metal gates being too low and not meeting the requirements, and to expand the process window of the planarization process, the present invention provides a method for fabricating a semiconductor device and a semiconductor device.
[0005] On one hand, the present invention provides a method for fabricating a semiconductor device, the method comprising:
[0006] A semiconductor structure is formed, the semiconductor structure including a substrate and at least two gate recesses formed on the substrate, each gate recess having a gate dielectric layer and a sidewall respectively on its bottom wall and sidewall, the at least two gate recesses including a first gate recess and a second gate recess, the cross-sectional area of the first gate recess being smaller than the cross-sectional area of the second gate recess;
[0007] A first metal layer is deposited on the surface of the semiconductor structure at a first deposition temperature. The surface of the first metal layer that fills the first gate recess and faces away from the bottom wall of the first gate recess is higher than the opening of the first gate recess. The upper surface of the first metal layer that fills the second gate recess and faces away from the bottom wall of the second gate recess is lower than the opening of the second gate recess.
[0008] A second metal layer is deposited on the surface of the first metal layer at a second deposition temperature higher than the first deposition temperature. The second metal layer fills the second gate recess, and the surface of the second metal layer facing away from the bottom wall of the second gate recess is higher than the opening of the second gate recess. The density of the second metal layer is higher than that of the first metal layer.
[0009] A planarization process is performed to remove part of the first metal layer and part of the second metal layer. The remaining first metal layer located in the first gate recess forms the first metal gate, and the remaining first metal layer and second metal layer located in the second gate recess form the second metal gate.
[0010] Optionally, of the at least two gate recesses, the first gate recess is the gate recess with the smallest cross-sectional area; and / or, of the at least two gate recesses, the second gate recess is the gate recess with the largest cross-sectional area.
[0011] Optionally, the first metal layer and the second metal layer comprise aluminum.
[0012] Optionally, the first deposition temperature is 100℃~300℃; and / or, the second deposition temperature is 300℃~500℃.
[0013] Optionally, the planarization process employs CMP.
[0014] Optionally, forming the semiconductor structure includes:
[0015] At least two MOS structures with sacrificial gates are formed in the active region of the substrate. Each MOS structure includes the gate dielectric layer and the corresponding sacrificial gate stacked on the surface of the substrate, the sidewalls covering the gate dielectric layer and the side of the sacrificial gate, and source / drain regions formed on both sides of the sacrificial gate.
[0016] A contact etch barrier layer is formed, wherein the contact etch barrier layer conformally covers the substrate on which the MOS structure is formed;
[0017] An interlayer dielectric layer is formed, which covers the contact etch barrier layer and fills the height difference between the MOS structure and the substrate;
[0018] A planarization process is performed to remove part of the contact etch barrier layer and the interlayer dielectric layer, exposing the sacrificial gate; and
[0019] The sacrificial gate is removed, and the gate recess is formed corresponding to each of the MOS structures.
[0020] Optionally, before depositing the first metal layer, the fabrication method further includes:
[0021] A barrier layer and a work function adjustment layer are sequentially formed within the gate groove in a conformal manner.
[0022] On the other hand, the present invention provides a semiconductor device, the semiconductor device comprising:
[0023] A semiconductor structure includes a substrate and at least two gate recesses formed on the substrate. Each gate recess has a gate dielectric layer on its bottom wall and a sidewall on its sidewall. The sidewall on the side away from the corresponding gate recess also has an interlayer dielectric layer. The at least two gate recesses include a first gate recess and a second gate recess. The cross-sectional area of the first gate recess is smaller than the cross-sectional area of the second gate recess.
[0024] A first metal layer fills the first gate trench and the second gate trench, and forms a first metal gate within the first gate trench; and
[0025] A second metal layer fills the second gate recess and covers the first metal layer within the second gate recess. The second metal layer has a higher density than the first metal layer. The first metal layer and the second metal layer together form a second metal gate within the second gate recess.
[0026] Optionally, of the at least two gate recesses, the first gate recess is the gate recess with the smallest cross-sectional area; and / or, of the at least two gate recesses, the second gate recess is the gate recess with the largest cross-sectional area.
[0027] Optionally, the gate dielectric layer includes an interface dielectric layer formed on the surface of the substrate and a high dielectric constant material layer formed on the surface of the interface dielectric layer.
[0028] In the semiconductor device fabrication method provided by this invention, a first metal layer with a lower deposition temperature is formed in a first gate trench with a smaller cross-sectional area, and a first metal layer with a lower deposition temperature is first formed in a second gate trench with a larger cross-sectional area, followed by a second metal layer with a higher deposition temperature. The density of the second metal layer is higher than that of the first metal layer. During the planarization process, the loading effect in the second gate trench region can be suppressed, resulting in good height consistency between the upper surfaces of the first metal gate formed in the first gate trench and the upper surfaces of the second metal gate formed in the second gate trench. By utilizing the planarization process, it is convenient to ensure that there is no short circuit between the metal gates while avoiding excessively low upper surfaces of some metal gates, thus expanding the process window of the planarization process.
[0029] In the semiconductor device provided by this invention, the first metal layer fills the first gate trench and forms a first metal gate, and the second metal layer fills the second gate trench and covers the first metal layer within the second gate trench. The first metal layer and the second metal layer form a second metal gate within the second gate trench. When the upper surfaces of the first metal gate and the second metal gate are simultaneously formed using a planarization process, since the density of the upper surface of the second metal gate is higher than that of the upper surface of the first metal gate, the problem of the lower upper surface of the second metal gate caused by the load effect can be suppressed, resulting in good height consistency between the upper surfaces of the first metal gate and the second metal gate. This allows the upper surfaces of the metal gates formed in gate trenches of different sizes to be basically flush. The planarization process has a large process window, which can ensure that there is no short circuit between the metal gates while avoiding some metal gates having excessively low upper surfaces, thus helping to improve the performance of the semiconductor device. Attached Figure Description
[0030] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0031] Figures 2A to 2F This is a schematic flowchart of a method for fabricating a semiconductor device according to another embodiment of the present invention. Detailed Implementation
[0032] The semiconductor device and fabrication method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the drawings in this specification are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order in which these steps are performed; some steps may be omitted and / or some other steps not described herein may be added to the method.
[0033] Some embodiments of the present invention include a method for fabricating a semiconductor device. (See also...) Figure 1 , Figures 2A to 2C The fabrication method includes step S1: forming a semiconductor structure 100, the semiconductor structure 100 including a substrate 10 and at least two gate recesses formed on the substrate 10, wherein each gate recess has a gate dielectric layer on its bottom wall and a sidewall on its sidewall, and the at least two gate recesses include a first gate recess T1 and a second gate recess T2, wherein the cross-sectional area of the first gate recess T1 is smaller than the cross-sectional area of the second gate recess T2. Here, "cross-section" refers to a cross section perpendicular to the thickness direction of the substrate 100.
[0034] The substrate 10 can be a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or other substrates known to those skilled in the art for supporting semiconductor devices. In the following description, the substrate 10 is, for example, a silicon substrate. Certain dopant ions can be implanted into the substrate 10 to adjust electrical parameters according to design requirements. Furthermore, isolation structures (such as shallow trench isolation (STI)) and active regions defined by the isolation structures can be formed within the substrate 10.
[0035] In this embodiment of the invention, the semiconductor structure 100 is an intermediate structure formed by performing a semiconductor process to form a MOS device with a metal gate. The intermediate structure can be formed using processes already known in the art, and its formation includes the following exemplary processes.
[0036] First, at least two MOS structures with sacrificial gates are formed in the active region of the substrate 10. Each MOS structure includes a gate dielectric layer and a sacrificial gate stacked on the surface of the substrate 10, sidewalls covering the sides of the gate dielectric layer and the sacrificial gate, and source / drain regions formed on both sides of the sacrificial gate.
[0037] like Figure 2AAs shown, as an example, the substrate 10 has a first active region AA1 and a second active region AA2. A first MOS structure can be formed in the first active region AA1 and a second MOS structure can be formed in the second active region AA2 using known processes. The first MOS structure includes a first gate dielectric layer 110a formed on the surface of substrate 10, a first sacrificial gate PG1 (e.g., made of polysilicon) formed on the first gate dielectric layer 110a, sidewalls covering the sides of the first gate dielectric layer 110a and the first sacrificial gate PG1, and source / drain regions 11 and 12 formed on both sides of the first sacrificial gate PG1. Here, the source / drain regions of the first MOS structure may include, for example, embedded germanium-silicon. The second MOS structure includes a second gate dielectric layer 110b formed on the surface of substrate 10, a second sacrificial gate PG2 (e.g., made of polysilicon) formed on the second gate dielectric layer 110b, sidewalls covering the sides of the second gate dielectric layer 110b and the second sacrificial gate PG2, and source / drain regions 13 and 14 formed on both sides of the second sacrificial gate PG2. Source / drain regions 13 and 14 may be p-type doped. To reduce contact resistance, a metal silicide layer 120 is also formed on the surface of the source / drain regions in the first and second MOS structures.
[0038] Reference Figure 2A Both the first gate dielectric layer 110a and the second gate dielectric layer 110b include an interface dielectric layer 101 and a high dielectric constant material layer HK stacked longitudinally on the surface of the substrate 10. The interface dielectric layer 101 is made of materials such as silicon oxide or silicon oxynitride, and the high dielectric constant material layer HK includes various high dielectric constant materials (dielectric constant greater than 3.8), such as rare earth metal oxide layers or lanthanide metal oxide layers, for example, hafnium oxide (HfO2). Furthermore, a first barrier layer 102 may be formed between the high dielectric constant material layer HK and the first sacrificial gate PG1, and between the high dielectric constant material layer HK and the second sacrificial gate PG2. The first barrier layer 102 can serve as an etch stop layer or a diffusion barrier layer in subsequent processes. The material of the first barrier layer 102 may include at least one of titanium nitride, tantalum nitride, tantalum carbide, tantalum carbide, and molybdenum aluminosilicate, for example, titanium nitride (TiN). The sidewalls may include an offset sidewall SP1 and a main sidewall, the main sidewall being, for example, an ONO stack.
[0039] Still refer to Figure 2ANext, a contact etch barrier layer 131 is formed, which conformally covers the substrate 10 on which the above-mentioned MOS structure is formed. Then, a dielectric material is deposited to form an interlayer dielectric layer 132, which covers the contact etch barrier layer 131 and compensates for the height difference between the MOS structure and the substrate 10. At this time, the upper surface of the interlayer dielectric layer 132 is higher than the top surface of the sidewall. The contact etch barrier layer 131 includes, for example, silicon nitride, and the interlayer dielectric layer 132 includes, for example, silicon oxide. After that, a planarization process (such as CMP) is performed, so that part of the interlayer dielectric layer 132 and part of the contact etch barrier layer 131 are removed and stopped on the sacrificial gate, exposing the top surface of the sacrificial gate. Through this planarization process, the upper surface of the interlayer dielectric layer 132 is flush with the top surface of the sacrificial gate. In this article, "flatness" achieved by planarization process refers to a state in which, within the capability of the planarization process, the height difference between the surfaces of at least two components (such as the interlayer dielectric layer 132 and the sacrificial gate) after planarization meets the flatness requirements. For example, the height difference that meets the flatness requirements is, for example, less than or equal to 5 nm.
[0040] Next, refer to Figure 2B An etching process is performed to remove the sacrificial gates (such as the first sacrificial gate PG1 and the second sacrificial gate PG2) in each MOS structure, and a gate groove is formed corresponding to each MOS structure.
[0041] like Figure 2B As shown, in some embodiments, the high-dielectric-constant material layer HK and the first barrier layer 102 are formed before the sacrificial gate, and the first barrier layer 102 is exposed after the sacrificial gate is removed. However, the present invention is not limited to this. For example, in other embodiments, in the above-described first MOS structure and second MOS structure, the first gate dielectric layer 110a and the second gate dielectric layer 110b do not include the high-dielectric-constant material layer HK, nor do they have the first barrier layer 102. Furthermore, after the sacrificial gate is removed, the exposed gate dielectric layer is removed by an etching process, and an interface dielectric layer, a high-dielectric-constant material layer, and a first barrier layer are sequentially formed on the bottom surface of the exposed substrate 10 (i.e., post-HK process).
[0042] Reference Figure 2B In this embodiment of the invention, at least two gate recesses formed on the substrate 10 include a first gate recess T1 and a second gate recess T2. The cross-sectional area of the first gate recess T1 is smaller than the cross-sectional area of the second gate recess T2, and the cross-sectional area of the metal gate subsequently formed in the first gate recess T1 will be smaller than the cross-sectional area of the metal gate formed in the second gate recess T2. The depths of the first gate recess T1 and the second gate recess T2 are, for example, the same.
[0043] like Figure 2C As shown, in some embodiments, before performing subsequent processes to form a metal gate in the gate recess, the fabrication method further includes: sequentially forming a second barrier layer 103 and a work function adjustment layer 104 in the gate recess in a conformal manner. The work function adjustment layer 104 can be used to match the work function of the subsequently formed metal gate with that of the high dielectric constant material layer HK. Depending on the type of device, the work function adjustment layer 104 may include a p-type work function metal layer or an n-type work function metal layer. The second barrier layer 103 is used to block the diffusion of metal elements, and may specifically include at least one of materials such as titanium nitride, tantalum nitride, tantalum carbide, tantalum carbide, and molybdenum silicide. As an example, the second barrier layer 103 is tantalum nitride (TaN). The work function adjustment layer 104 is, for example, a p-type work function metal layer, such as titanium nitride (TiN). In some embodiments, after forming the work function adjustment layer 104, another barrier layer is formed on the surface of the work function adjustment layer 104.
[0044] Optionally, before forming the metal gate, titanium and titanium nitride (Ti / TiN) are conformally formed in the gate recess, not shown in the figure.
[0045] After the above process, the semiconductor structure 100 described in step S1 is formed. Next, a metal gate is formed within the gate trench. In this embodiment of the invention, the metal material used to form the metal gate is not deposited in one step, but rather formed in stages at different deposition temperatures, as detailed below.
[0046] Reference Figure 1 and Figure 2D The method for fabricating a semiconductor device according to an embodiment of the present invention includes step S2: depositing a first metal layer 140 on the surface of a semiconductor structure 100 at a first deposition temperature, wherein the surface of the first metal layer 140 that fills the first gate recess T1 and faces away from the bottom wall of the first gate recess T1 is higher than the opening of the first gate recess T1, and the upper surface of the first metal layer 140 that fills the second gate recess T2 and faces away from the bottom wall of the second gate recess T2 is lower than the opening of the second gate recess T2.
[0047] The first metal layer 140 can be deposited using processes such as physical vapor deposition or atomic layer deposition. The first deposition temperature is the ambient temperature at which the metal material is deposited onto the surface of the semiconductor structure 100. Setting a higher deposition temperature helps to improve the density of the metal layer. For example, the first deposition temperature is 100°C to 300°C. In this embodiment, the first metal layer 140 includes, for example, aluminum, such as elemental aluminum or aluminum alloys (e.g., aluminum-copper, aluminum-silicon). Since the deposition temperature of the first metal layer 140 is lower than the subsequent second deposition temperature, the material of the first metal layer 140 is referred to as a low-temperature metal material (e.g., low-temperature aluminum). It should be understood that in the following embodiments, the material of the first metal layer 140 is, for example, an aluminum alloy, but it is not limited to aluminum and its alloys; other metal materials may also be included as needed.
[0048] The first metal layer 140 covers the inner surface of each gate trench, the sidewalls outside the gate trench, the top surface of the contact etch barrier layer 131, and the interlayer dielectric layer 132. Because the cross-sectional size of the first gate trench T1 is small, during the metal material deposition process, as the deposition thickness increases, the gaps between the sidewalls of the first gate trench T1 gradually decrease and are eventually closed, meaning the first gate trench T1 is filled by the first metal layer 140. When deposition continues, the low-temperature metal material extends to the outside of the first gate trench T1 in the region of the first gate trench T1, causing the surface of the first metal layer 140 facing away from the bottom wall of the first gate trench T1 to be higher than the opening of the first gate trench T1. Because the cross-sectional size of the second gate trench T2 is larger than that of the first gate trench T1, when the first gate trench T1 is filled, the second gate trench T2 is not filled, causing the upper surface of the first metal layer 140 facing away from the bottom wall of the second gate trench T2 to be lower than the opening of the second gate trench T2. Figure 2D As shown, by controlling the deposition process, when the low-temperature metal material is deposited, the upper surface of the portion of the first metal layer 140 located in the first gate recess T1 region is generally higher than the upper surface of the interlayer dielectric layer 132, and the first metal layer 140 conformally covers the inner wall of the second gate recess T2, while the upper surface of the portion of the first metal layer 140 in the second gate recess T2 region is lower than the upper surface of the interlayer dielectric layer 132.
[0049] Reference Figure 1 and Figure 2EThe method for fabricating a semiconductor device according to an embodiment of the present invention includes step S3: depositing a second metal layer 150 on the surface of a first metal layer 140 at a second deposition temperature higher than the first deposition temperature. The second metal layer 150 fills the second gate recess T2, and the surface of the second metal layer 150 facing away from the bottom wall of the second gate recess T2 is higher than the opening of the second gate recess T2. Due to the higher deposition temperature, the density of the second metal layer 150 is higher than that of the first metal layer 140. In this embodiment, the upper surface of the second metal layer 150 is higher than the upper surface of the interlayer dielectric layer 132. The thickness of the second metal layer 150 is, for example, around 4000 Å.
[0050] The deposition of the second metal layer 150 can be performed using processes such as physical vapor deposition or atomic layer deposition. The second deposition temperature is the cavity temperature at which the metal material is deposited onto the surface of the semiconductor structure 100, as set by the corresponding deposition process. As an example, the second deposition temperature is 300°C to 500°C. The second metal layer 150 may include, for example, aluminum, such as elemental aluminum or aluminum alloys (e.g., aluminum-copper, aluminum-silicon). Since the second deposition temperature is higher than the first deposition temperature, the material of the second metal layer 150 is referred to as a high-temperature metal material (e.g., high-temperature aluminum). In the following embodiments, the material of the second metal layer 150 is, for example, an aluminum alloy, but it is not limited to aluminum and its alloys; other materials may also be included as needed.
[0051] The second metal layer 150 covers the first metal layer 140. By controlling the thickness of the second metal layer 150, it is possible to make the second metal layer 150 fill the second gate recess T2, so that the surface of the second metal layer 150 facing away from the bottom wall of the second gate recess T2 is higher than the opening of the second gate recess T2. In the region of the first gate recess T1, the second metal layer 150 covers the first metal layer 140 outside the first gate recess T1.
[0052] Reference Figure 1 and Figure 2F The method for fabricating a semiconductor device according to an embodiment of the present invention includes step S4: performing a planarization process to remove a portion of the first metal layer 140 and a portion of the second metal layer, with the remaining first metal layer 140 forming a first metal gate MG1 in a first gate recess T1, and the remaining first metal layer 140 and second metal layer 150 forming a second metal gate MG2 in a second gate recess T2. In this embodiment, after the planarization process, the interlayer dielectric layer 132 is exposed and flush with the top surfaces of the remaining first metal layer 140 and second metal layer 150.
[0053] The planarization process in step S4 can be CMP or maskless etching, for example, CMP. During the CMP polishing process, the first metal layer 140 and the second metal layer 150 outside the first gate recess T1 and the second gate recess T2 are removed, and in order to ensure that there is no short circuit between the different metal gates to be formed on the substrate 10, the CMP time can be increased, i.e., over-polishing.
[0054] In conventional grinding processes, since the supply of reactants in each region of the substrate is basically stable, when grinding the same material, the material with a larger surface area consumes and supplies reactants faster, resulting in a faster reaction rate. This causes the area with a larger surface area to have a larger amount of grinding compared to the area with a smaller surface area, thus reducing the surface area, which is called the loading effect. In this embodiment, although the metal upper surface area of the first gate groove T1 region, which has a smaller cross-sectional area, is smaller, and the metal upper surface area of the second gate groove T2 region, which has a larger transverse area, is larger, the metal material filled in the first gate groove T1 is only the first metal layer 140 (such as low-temperature aluminum), which has a lower density and is relatively easier to remove. The second gate groove T2, however, is filled with both the first metal layer 140 (such as low-temperature aluminum) and the second metal layer 150 (such as high-temperature aluminum). The surface of the metal being polished includes the first metal layer 140 located in the peripheral region and the second metal layer 150 located in the middle region. During CMP polishing, because the second metal layer 150 has a higher density, it is relatively more difficult to remove. This can suppress the problem of faster polishing in the second gate groove T2 region caused by the aforementioned load effect, thus balancing the overall polishing rate of the first gate groove T1 region and the second gate groove T2 region. The resulting metal gate upper surface heights are closer and more uniform. Here, "metal gate upper surface height" refers to the distance between the upper surface of the metal gate and the upper surface of the substrate 10 in the thickness direction of the substrate 10. As can be seen, the manufacturing method of the above embodiment helps to control the degree of CMP polishing, and can perform appropriate over-polishing to avoid short circuits between different metal gates. At the same time, it can avoid the metal upper surface of the second gate groove T2 region being too low, which would cause the corresponding metal gate to not meet the requirements, thus widening the process window of the planarization process.
[0055] The first gate recess T1 is, for example, the gate recess with the smallest cross-sectional area among at least two gate recesses formed on the substrate 10, while the second gate recess T2 is, for example, the gate recess with the largest cross-sectional area. Using the above process, the height of the upper surface of the metal gate in the gate recess regions with the smallest and largest cross-sectional areas is more uniform. For gate recesses with a cross-sectional area between the first gate recess T1 and the second gate recess T2, after the above process, wherein the metal material is the first metal layer 140 or a combination of the first metal layer 140 and the second metal layer 150, and the height of the upper surface is more consistent with the height of the upper surface of the metal gate in the gate recess regions with the smallest and largest cross-sectional areas, it can be seen that, using the above process, the height of the upper surface of the metal gate formed in each gate recess is more consistent, for example, basically flush. This can ensure that there is no short circuit between the metal gates, while avoiding that the upper surface of some metal gates is too low, thus expanding the process window of the above planarization process.
[0056] This invention is not limited thereto. In another embodiment, the first gate recess T1 may not be the gate recess with the smallest cross-sectional area, or the second gate recess T2 may not be the gate recess with the largest cross-sectional area. Through the above process, for small gate recesses with a cross-sectional area smaller than the first gate recess T1, the upper surface of the metal gate formed by filling it with the first metal layer 140 in step S2 is the surface of the first metal layer 140. For large gate recesses with a cross-sectional area larger than the second gate recess T2, the metal gate is formed by filling it with the first metal layer 140 and the second metal layer 150 after steps S2 and S3. The upper surface includes the surface of the first metal layer 140 located in the peripheral region and the surface of the second metal layer 150 located in the middle region. When performing the above step S4, the metal density of the small gate groove region is low and the metal density of the large gate groove region is high, which can compensate for the influence of the load effect and make the overall planarization process rate more balanced. After the planarization process is completed, the upper surface height of the metal gates formed corresponding to each gate groove is more consistent, for example, basically flush. This can also ensure that there is no short circuit between the metal gates while avoiding some metal gates having too low an upper surface, thus expanding the process window of the planarization process.
[0057] This invention also relates to a semiconductor device, which can be formed using the fabrication method described in the above embodiments.
[0058] Reference Figures 2A to 2FThe semiconductor device includes a semiconductor structure 100, a first metal layer 140, and a second metal layer 150. The semiconductor structure 100 includes a substrate 10 and at least two gate recesses formed on the substrate 10. Each gate recess has a gate dielectric layer and a sidewall on its bottom wall and sidewall, respectively. The sidewall also has an interlayer dielectric layer 132 on the side away from the corresponding gate recess. The at least two gate recesses include a first gate recess T1 and a second gate recess T2. The cross-sectional area of the first gate recess T1 is smaller than the cross-sectional area of the second gate recess T2.
[0059] A first metal layer 140 fills a first gate recess T1 and a second gate recess T2, and forms a first metal gate MG1 in the first gate recess T1. A second metal layer 150 fills a second gate recess T2 and covers the first metal layer 140 in the second gate recess T2. The density of the second metal layer 150 is higher than that of the first metal layer 140. The first metal layer 140 and the second metal layer 150 form a second metal gate MG2 in the second gate recess T2.
[0060] Optionally, of the at least two gate recesses on the semiconductor structure 100, the first gate recess T1 is the gate recess with the smallest cross-sectional area; and / or, the second gate recess T2 is the gate recess with the largest cross-sectional area.
[0061] In some embodiments, the gate dielectric layer includes an interface dielectric layer 101 formed on the surface of the substrate 10 and a high dielectric constant material layer HK formed on the surface of the interface dielectric layer 101. Furthermore, the first gate recess T1 may also have a work function adjustment layer and a barrier layer surrounding the first metal gate MG1. The second gate recess T2 may also have a work function adjustment layer and a barrier layer surrounding the second metal gate MG2.
[0062] In the semiconductor device of this embodiment, a first metal layer 140 fills a first gate recess T1 to form a first metal gate MG1, and a second metal layer 150 fills a second gate recess T2 and covers the first metal layer 140 within the second gate recess T2. The first metal layer 140 and the second metal layer 150 form a second metal gate MG2 within the second gate recess T2. The density of the second metal layer 150 is higher than that of the first metal layer 140, that is, the density of the upper surface of the second metal gate MG2 is higher than that of the upper surface of the first metal gate MG1. The upper surface of the first metal gate MG1 and the second metal gate MG2 are formed simultaneously using a planarization process. When planarizing the upper surface, the problem of the lower surface of the second metal gate MG2, which has a larger upper surface, caused by the above-mentioned load effect can be suppressed, so that the height difference between the upper surfaces of the first metal gate MG1 and the second metal gate MG2 is smaller and the height of the upper surfaces is more consistent. That is, metal gates with basically flush upper surface heights can be formed in gate grooves of different sizes. Compared with the case where the first metal gate and the second metal gate are metals with the same degree of density, the semiconductor device using the embodiment of the present invention has a larger process window for the planarization process. It can ensure that there is no short circuit between the metal gates while avoiding that the upper surface of some metal gates is too low, which helps to improve the performance of the semiconductor device.
[0063] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from other embodiments, and relevant parts can be understood by referring to them.
[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method of manufacturing a semiconductor device, characterized by, The method comprises: forming a semiconductor structure, the semiconductor structure comprising a substrate, at least two gate recesses formed on the substrate, each of the gate recesses having a gate dielectric layer and a sidewall on a bottom wall and a sidewall respectively, the at least two gate recesses comprising a first gate recess and a second gate recess, a cross-sectional area of the first gate recess being smaller than a cross-sectional area of the second gate recess; depositing a first metal layer on a surface of the semiconductor structure at a first deposition temperature, the first metal layer filling the first gate recess and being higher than an opening of the first gate recess at a surface facing away from the bottom wall of the first gate recess, the first metal layer filling the second gate recess and being lower than the opening of the second gate recess at a portion of a surface facing away from the bottom wall of the second gate recess; depositing a second metal layer on a surface of the first metal layer at a second deposition temperature higher than the first deposition temperature, the second metal layer filling the second gate recess and being higher than the opening of the second gate recess at a surface facing away from the bottom wall of the second gate recess, the second metal layer being denser than the first metal layer; and performing a planarization process to remove part of the first metal layer and part of the second metal layer, the remaining first metal layer in the first gate recess forming a first metal gate, and the remaining first metal layer and the second metal layer in the second gate recess forming a second metal gate. In the at least two gate recesses, the first gate recess is a gate recess with the smallest cross-sectional area; and / or, in the at least two gate recesses, the second gate recess is a gate recess with the largest cross-sectional area.
2. The method of claim 1, wherein The first metal layer and the second metal layer comprise aluminum.
3. The method of claim 1, wherein The first deposition temperature is 100-300°C; and / or, the second deposition temperature is 300-500°C.
4. The method of claim 1, wherein The planarization process uses CMP.
5. The method of claim 1, wherein The forming of the semiconductor structure comprises:
6. The production method according to any one of claims 1 to 5, wherein forming at least two MOS structures with a sacrificial gate in an active region of the substrate, each of the MOS structures comprising the gate dielectric layer and the corresponding sacrificial gate stacked on a surface of the substrate, the sidewall covering the gate dielectric layer and the sidewall of the sacrificial gate, and the source / drain region formed on both sides of the sacrificial gate; forming a contact etching stop layer conformally covering the substrate on which the MOS structures are formed; forming an interlayer dielectric layer covering the contact etching stop layer and filling a height difference between the MOS structures and the substrate; performing a planarization process to remove part of the contact etching stop layer and part of the interlayer dielectric layer, and exposing the sacrificial gate; and removing the sacrificial gate to form the gate recess corresponding to each of the MOS structures. Before depositing the first metal layer, the method further comprises:
7. The production method according to any one of claims 1 to 5, wherein forming a barrier layer and a work function adjusting layer conformally in the gate recess in sequence. The method comprises:
8. A semiconductor device, characterized by comprising: A semiconductor structure, comprising: a substrate; at least two gate recesses formed on the substrate, each of the gate recesses having a gate dielectric layer and a sidewall on a bottom wall and a sidewall, respectively, the sidewall further having an interlayer dielectric layer away from a side of the corresponding gate recess, wherein the at least two gate recesses comprise a first gate recess and a second gate recess, the first gate recess having a cross-sectional area smaller than a cross-sectional area of the second gate recess; a first metal layer filling the first gate recess and the second gate recess and forming a first metal gate in the first gate recess; and a second metal layer filling the second gate recess and covering the first metal layer in the second gate recess, the second metal layer having a higher density than the first metal layer, and the first metal layer and the second metal layer forming a second metal gate in the second gate recess. In the at least two gate recesses, the first gate recess is a gate recess having a smallest cross-sectional area; and / or, in the at least two gate recesses, the second gate recess is a gate recess having a largest cross-sectional area.
9. The semiconductor device of claim 8, wherein, The gate dielectric layer comprises an interface dielectric layer formed on a surface of the substrate and a high dielectric constant material layer formed on a surface of the interface dielectric layer.
10. The semiconductor device of claim 8, wherein,