DDR pinboard, life detection method thereof and storage medium

Abstract

The invention discloses a DDR adapter plate, a life detection method thereof and a storage medium, relates to the technical field of testing, and discloses the DDR adapter plate which comprises a golden finger, an EEPROM, a slot and an IIC address conversion circuit. The EEPROM is electrically connected with the IIC address conversion circuit, the IIC address conversion circuit is electrically connected with an address bus in the IIC bus, one end of the address bus is electrically connected with an IIC address interface of the golden finger, and the other end of the address bus is electrically connected with an IIC address interface of the slot; the IIC address conversion circuit is used for converting an IIC address of an address bus to obtain a target IIC address, and writing the target IIC address into the EEPROM; and the EEPROM is used for storing the number of times of plugging and unplugging corresponding to the adapter plate and the number of times of remaining plugging and unplugging. According to the invention, accurate detection of the service life of the DDR adapter plate is realized, and the test efficiency and quality of the SODIMM are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a DDR adapter board and a life detection method thereof, and a storage medium. BACKGROUND

[0002] At present, the signals of DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory, low four-generation double data rate synchronous dynamic random access memory) UDIMM (Unbuffered Dual In-Line Memory Module, unbuffered dual in-line memory module) and SODIMM (Small Outline Dual In-line Memory Module, small outline dual in-line memory module) can be compatible. In order to adapt to different application scenarios, the gold fingers and the shapes of the DDR4 UDIMM are different from those of the SODIMM. In the SODIMM memory testing and screening, the adapter board is usually used to test the SODIMM on the UDIMM test machine, thereby saving the development and testing costs. The general DDR4 adapter board includes a gold finger, a slot and an SPD (Serial Presence Detect) device. Since the DDR4 adapter board can only realize the conversion of the (DDR4) SODIMM.

[0003] Since the gold fingers and the slot of the DDR4 adapter board will be worn during the plugging process, when the plugging times reach a certain degree, the high-speed signal quality of the DDR will be greatly affected, and even the test failure may be directly caused. Since the DDR4 adapter board cannot count the plugging times, when the SODIMM test fails, it cannot be determined whether the test failure is caused by the DRAM particle problem or the life problem of the gold fingers and the slot of the DDR4 adapter board. It is necessary to spend time and manpower to locate, which affects the test efficiency and quality.

[0004] Therefore, how to detect and record the service life of the DDR adapter board and improve the test efficiency and quality of the SODIMM is a problem to be solved at present.

[0005] The above content is only used to assist in understanding the technical solutions of the present application, and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0006] The main purpose of the present application is to provide a DDR adapter board and a life detection method thereof, and a storage medium, which aims to solve the technical problem of how to detect and record the service life of the DDR4 adapter board and improve the test efficiency and quality of the SODIMM.

[0007] To achieve the above object, the application provides a DDR adapter plate, which comprises a golden finger, an EEPROM, a slot and an IIC address conversion circuit. The EEPROM is electrically connected with the IIC address conversion circuit, the IIC address conversion circuit is electrically connected with an address bus in an IIC bus, one end of the address bus is electrically connected with an IIC address interface of the golden finger, and the other end is electrically connected with an IIC address interface of the slot. The IIC address conversion circuit is used for converting an IIC address of the address bus, obtaining a target IIC address, and writing the target IIC address into the EEPROM. The EEPROM is used for storing a plugged-in times corresponding to the adapter plate and a remaining plugged-in times.

[0008] In an embodiment, the IIC address conversion circuit comprises an inverter, and the address interface of the EEPROM is electrically connected with a preset address bus of the address bus through the inverter.

[0009] In an embodiment, at least one address interface of the EEPROM is electrically connected with a corresponding preset address bus through the inverter, and the other address interfaces are respectively electrically connected with corresponding preset address buses.

[0010] In an embodiment, the IIC address conversion circuit comprises a resistor. At least one address interface of the EEPROM corresponding to a high-level preset address bus is grounded through the resistor, and / or at least one address interface corresponding to a low-level preset address bus is electrically connected with a power supply through the resistor.

[0011] In an embodiment, the processor updates the plugged-in times and the remaining plugged-in times in the EEPROM based on the target IIC address corresponding to the EEPROM.

[0012] In addition, to achieve the above object, the application further provides a life detection method of an adapter plate, which is applied to the DDR adapter plate, and the life detection method of the adapter plate comprises the following steps. When a plugged-in times updating instruction is received, the plugged-in times and the remaining plugged-in times corresponding to the DDR adapter plate are read from the EEPROM based on the target IIC address corresponding to the EEPROM. The plugged-in times and the remaining plugged-in times are updated to obtain updated plugged-in times and updated remaining plugged-in times. The updated plugged-in times and the updated remaining plugged-in times are written into the EEPROM.

[0013] In an embodiment, when the plug-in and plug-out times updating instruction is received, the step of reading the plugged-in times and the remaining plug-in times of the DDR adapter from the EEPROM based on the target IIC address of the EEPROM comprises: Two IIC addresses are obtained through the IIC bus, wherein the two IIC addresses comprise the target IIC address in the EEPROM and the IIC address in the SPD of the SODIMM to be detected; The slave IIC address corresponding to the mainboard IIC bus is obtained, and the target IIC address in the EEPROM is determined from the two IIC addresses based on the slave IIC address; The plugged-in times and the remaining plug-in times of the DDR adapter are read from the EEPROM based on the target IIC address.

[0014] In an embodiment, the step of writing the updated plugged-in times and the updated remaining plug-in times into the EEPROM comprises: It is determined whether the updated remaining plug-in times are greater than a preset value; If the updated remaining plug-in times are greater than or equal to the preset value, the updated plugged-in times and the updated remaining plug-in times are written into the EEPROM.

[0015] In an embodiment, after the step of determining whether the updated remaining plug-in times are greater than or equal to the preset value, the life detection method of the adapter further comprises: If the updated remaining plug-in times are less than the preset value, prompt information that the DDR adapter has reached the maximum test times is output.

[0016] In addition, to achieve the above-mentioned purposes, the present application also provides a storage medium, characterized in that the storage medium is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the life detection method of the adapter.

[0017] The one or more technical solutions provided by the present application have at least the following technical effects: The IIC address conversion circuit converts the IIC address of the address bus, so that the IIC interface address of the EEPROM device is different from the IIC address stored in the SPD of the SODIMM to be detected, so as to distinguish the EEPROM and the SPD, and then the plugged-in times and the remaining plug-in times of the adapter stored in the EEPROM can be accurately read and updated through the IIC address stored in the EEPROM, the service life of the DDR adapter is determined according to the updated plugged-in times or the updated remaining plug-in times, the accurate detection of the service life of the DDR adapter is realized, and the test efficiency and quality of the SODIMM are improved. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the DDR adapter board provided in this application; Figure 2 This is a schematic diagram of the circuit structure of another embodiment of the DDR adapter board of this application; Figure 3 A simplified flowchart illustrating a life testing method for an adapter board provided in an embodiment of this application; Figure 4 This is a schematic diagram of the hardware operating environment involved in the life detection method of the adapter board in this application embodiment.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] The main solution of this application embodiment is as follows: the DDR adapter board includes gold fingers, EEPROM, slots, and IIC address conversion circuit; the EEPROM is electrically connected to the IIC address conversion circuit, the IIC address conversion circuit is electrically connected to the address bus in the IIC bus, one end of the address bus is electrically connected to the IIC address interface of the gold fingers, and the other end is electrically connected to the IIC address interface of the slot; the IIC address conversion circuit is used to convert the IIC address of the address bus to obtain the target IIC address, and write the target IIC address into the EEPROM; the EEPROM is used to store the number of insertions and removals and the remaining number of insertions and removals corresponding to the adapter board.

[0025] Currently, the signals of DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory, low four generations of double data rate synchronous dynamic random access memory) UDIMM (Unbuffered Dual In-Line Memory Module, unbuffered dual in-line memory module) and SODIMM (Small Outline Dual In-line Memory Module, small outline dual in-line memory module) can be compatible, in order to adapt to different application scenarios, the gold finger and the outline of the DDR4 UDIMM are different from the gold finger and the outline of the SODIMM. In the SODIMM memory test and screening, the adapter board is usually used to test the SODIMM on the UDIMM test machine, thereby saving the development and test cost; and the general DDR4 adapter board includes a gold finger, a slot and an SPD (Serial Presence Detect) device, since the DDR4 adapter board can only realize the conversion of the (DDR4) SODIMM.

[0026] Since the gold finger and the slot of the DDR4 adapter board will be worn during the plugging process, when the plugging times reach a certain degree, the high-speed signal quality of the DDR will be greatly affected, and even the test failure may be directly caused. Since the DDR4 adapter board cannot count the plugging times, when the SODIMM test fails, it cannot be judged whether the test failure is caused by the DRAM particle problem or the life problem of the gold finger and the slot of the DDR4 adapter board, and it is necessary to spend time and manpower to locate, thereby affecting the test efficiency and quality.

[0027] Therefore, how to detect and record the service life of the DDR4 adapter board and improve the test efficiency and quality of the SODIMM is a problem to be solved at present.

[0028] The application provides a solution, which converts the IIC address of the address bus through an IIC address conversion circuit, realizes that the IIC interface address of the EEPROM device is different from the IIC address stored in the SPD of the corresponding SODIMM to be detected, so as to distinguish the EEPROM and the SPD, and then the plugged times and the remaining plugging times of the adapter board corresponding to the EEPROM can be accurately read and updated through the IIC address stored in the EEPROM, the service life of the DDR adapter board is determined according to the updated plugged times or the updated remaining plugging times, the accurate detection of the service life of the DDR adapter board is realized, and the test efficiency and quality of the SODIMM are improved.

[0029] Based on this, the embodiment of the application provides a DDR adapter board, which is referred toFigure 1 , Figure 1 Figure 1 is a schematic diagram of a circuit structure of an embodiment of the DDR adapter plate.

[0030] In the embodiment, the DDR adapter plate comprises a golden finger, an EEPROM, a slot and an IIC address conversion circuit 100, and the DDR adapter plate can be a DDR4 adapter plate.

[0031] Please refer to Figure 1 The golden finger of the DDR adapter plate is inserted into the card slot of the corresponding mainboard, so that the DDR adapter plate is electrically connected with the mainboard through the golden finger and the card slot; the golden finger of the SODIMM to be detected is inserted into the slot of the DDR adapter plate, so that the DDR adapter plate is electrically connected with the SODIMM to be detected through the slot and the golden finger of the SODIMM to be detected, thereby realizing the testing of the SODIMM to be detected on the UDIMM testing machine through the DDR adapter plate.

[0032] The EEPROM is electrically connected with the IIC address conversion circuit 100, the IIC address conversion circuit 100 is electrically connected with the address bus in the IIC bus, one end of the address bus is electrically connected with the IIC address interface of the golden finger, and the other end is electrically connected with the IIC address interface of the slot; as shown in Figure 1 and Figure 2 The IIC address conversion circuit 100 is used for converting the IIC address of the address bus, obtaining a target IIC address, and writing the target IIC address into the EEPROM; the EEPROM is used for storing the corresponding number of times of plugging and the number of times of remaining plugging of the adapter plate.

[0033] It should be noted that before the DDR adapter plate is used for the first time, the maximum number of times of using and the number of times of plugging of the DDR adapter plate are written into the EEPROM of the DDR adapter plate, that is, the number of times of remaining plugging stored in the EEPROM is the maximum number of times of using of the DDR adapter plate, and the number of times of plugging and the number of times of remaining plugging in the EEPROM can be updated by the CPU every time the DDR adapter plate is inserted.

[0034] In addition, in the embodiment, the processor updates the number of times of plugging and the number of times of remaining plugging in the EEPROM based on the target IIC address corresponding to the EEPROM.

[0035] In order to accurately read the plugged-in times and the remaining plugged-in times in the EEPROM, the IIC address of the address bus is converted by the IIC address conversion circuit 100 to obtain a target IIC address, and the target IIC address is written into the EEPROM, so that the IIC address stored in the EEPROM is different from the IIC address stored in the SPD of the corresponding SODIMM to be detected, and the CPU can distinguish the SPD and the EEPROM by reading the IIC address in the SPD and the IIC address in the EEPROM, so as to accurately read the plugged-in times and the remaining plugged-in times in the EEPROM according to the target IIC address, update the plugged-in times and the remaining plugged-in times, that is, the plugged-in times + 1 and the remaining plugged-in times - 1, obtain the updated plugged-in times and the updated remaining plugged-in times, and write the updated plugged-in times and the updated remaining plugged-in times into the EEPROM, that is, replace the plugged-in times and the remaining plugged-in times stored in the EEPROM with the updated plugged-in times and the updated remaining plugged-in times, and the service life of the DDR adapter board can be accurately determined according to the updated plugged-in times or the updated remaining plugged-in times, the accurate detection of the service life of the DDR adapter board is realized, and the test efficiency and quality of the SODIMM are improved.

[0036] It should be noted that after the processor reads the plugged-in times and the remaining plugged-in times in the EEPROM, the plugged-in times and the remaining plugged-in times can be verified according to the maximum plugged-in times of the DDR adapter board. If the maximum plugged-in times = the plugged-in times + the remaining plugged-in times, the plugged-in times and the remaining plugged-in times are normal, otherwise, the plugged-in times or the remaining plugged-in times are wrong. At this time, the corresponding plugged-in times can be calculated by using the remaining plugged-in times, that is, the maximum plugged-in times - the remaining plugged-in times, the maximum value between the plugged-in times and the maximum plugged-in times - the remaining plugged-in times is written into the EEPROM, and the remaining plugged-in times is updated.

[0037] In a possible implementation, the IIC address conversion circuit 100 includes an inverter, and the IIC address conversion circuit 100 is electrically connected to the preset address bus of the address bus through the inverter.

[0038] It should be noted that the preset address bus in the address bus of the IIC bus can be reasonably selected by the IIC address interface of the mainboard, for example, the address bus corresponding to the low 3 bits of the IIC address is selected as the preset address bus. Figure 1 and Figure 2As shown in the figure, the IIC address interface of the EEPROM corresponding to the preset address bus is A2, A1 and A0, the IIC address interface of the mainboard is A2, A1 and A0, the IIC address interface of the gold finger, the slot, the gold finger of the SODIMM to be detected and the SPD of the SODIMM in the DDR adapter board is A2, A1 and A0.

[0039] In the embodiment of the application, the IIC address conversion circuit 100 comprises an inverter, and the inverter can be replaced by a NAND gate. The IIC address conversion circuit 100 is electrically connected to the preset address bus of the address bus through the inverter. As shown in the figure, Figure 2 As shown in the figure, when the IIC address interface of the EEPROM corresponding to the preset address bus is A2, A1 and A0, A2, A1 and A0 are connected to one or two address buses in the preset address bus through inverters, and the address interface of the EEPROM is electrically connected to the preset address bus of the address bus through the inverter, that is, any one address interface of the EEPROM is electrically connected to the preset address bus of the address bus through the inverter, or any two address interfaces of the EEPROM are respectively electrically connected to the preset address bus of the address bus through the inverter. For example, when A2, A1 and A0 of the mainboard end are set to 000, the address interface corresponding to A1 is electrically connected to the corresponding preset address bus through the inverter, and the address interfaces corresponding to A2 and A0 are directly electrically connected to the corresponding preset address bus. At this time, the IIC address low 3 bits of the EEPROM in the DDR adapter board is 010, so that the IIC address of the EEPROM is different from that in the SPD.

[0040] As shown in the figure, Figure 2 It can be understood that, as shown in the figure, the three address interfaces in the IIC address interface of the EEPROM can be respectively electrically connected to the preset address bus of the address bus through inverters, for example, the address interfaces of the IIC address low 3 bits of the EEPROM are respectively electrically connected to the preset address bus of the address bus through inverters.

[0041] In a feasible implementation, at least one address interface of the EEPROM is electrically connected to the corresponding preset address bus through the inverter, and the other address interfaces are respectively electrically connected to the corresponding preset address bus.

[0042] In the embodiment of the application, as shown in the figure, Figure 2As shown, an inverter can be arranged between the EEPROM and the preset address bus. For example, when the IIC address interface of the EEPROM corresponding to the preset address bus is A2, A1 and A0, one address interface of the EEPROM is electrically connected to the corresponding preset address bus through an inverter, two address interfaces are electrically connected to the corresponding preset address bus through inverters, or three address interfaces are electrically connected to the corresponding preset address bus through inverters, and the address interface without the inverter is directly electrically connected to the corresponding preset address bus. Thus, the corresponding bit in the IIC address can be reversed through the inverter, so that the IIC address of the EEPROM is different from that in the SPD.

[0043] In a possible implementation, the IIC address conversion circuit 100 includes a resistor; at least one address interface of the EEPROM corresponding to the high-level preset address bus is grounded through the resistor, and / or at least one address interface of the EEPROM corresponding to the low-level preset address bus is electrically connected to the power supply through the resistor.

[0044] It should be noted that the level of the address interface of the EEPROM corresponding to the preset address bus can also be different from that of the mainboard by pulling up or pulling down the resistor. The level of the preset address bus includes a high level and / or a low level. For the high-level preset address bus, the address interface of the EEPROM corresponding thereto can be grounded through the resistor. For the low-level preset address bus, the address interface of the EEPROM corresponding thereto can be electrically connected to the power supply through the resistor.

[0045] In this embodiment, one address interface of the EEPROM corresponding to the high-level preset address bus is grounded through the resistor, and / or one address interface of the EEPROM corresponding to the low-level preset address bus is electrically connected to the power supply through the resistor, and the other address interfaces are directly electrically connected to the corresponding preset address bus.

[0046] Alternatively, two address interfaces of the EEPROM corresponding to the high-level preset address bus are grounded through the resistor, or two address interfaces of the EEPROM corresponding to the low-level preset address bus are electrically connected to the power supply through the resistor, and the other address interfaces are directly electrically connected to the corresponding preset address bus.

[0047] All address interfaces of the EEPROM corresponding to the high-level preset address bus can also be grounded through the resistor, or all address interfaces of the EEPROM corresponding to the low-level preset address bus can be electrically connected to the power supply through the resistor.

[0048] It should be noted that, since the mainboard is provided with a plurality of card slots, in order to distinguish the EEPROMs of the DDR conversion boards inserted into the card slots, the IIC address conversion circuits 100 in the DDR conversion boards are not the same, so as to realize that the IIC addresses in the EEPROMs are different.

[0049] In addition, it should be noted that, as shown in Figure 1 different mainboards, the IIC address corresponding to the preset address bus of each mainboard is different. In this case, a corresponding switch, such as a dial switch, can be set for each preset address bus, a pull-up resistor and a pull-down resistor are set, and a selection switch is set for each address interface of the EEPROM corresponding to the preset address bus. The selection switch can include an off state, a pull-up state, and a pull-down state. In the pull-up state, the address interface of the EEPROM corresponding to the selection switch is electrically connected to the pull-up resistor. In the pull-down state, the address interface of the EEPROM corresponding to the selection switch is electrically connected to the pull-down resistor. Thus, for each preset address bus, it can be selected by the conduction and disconnection of the dial switch whether to directly connect the preset address bus to the address interface of the corresponding EEPROM. If the dial switch is disconnected, the selection switch can be controlled by the level of the preset address bus, so that the address interface of the EEPROM is electrically connected to the pull-up resistor (when the level of the preset address bus is high) or the pull-down resistor (when the level of the preset address bus is low).

[0050] As shown in Figure 1 , Figure 1 In the above, the switch in the IIC address conversion circuit 100 is a dial switch, the dial switch is in the open state on the right side and in the closed state on the left side. The light-colored resistor in the IIC address conversion circuit 100 represents the off state. For example, the dial switch corresponding to A2 is in the off state, the A2 address interface of the EEPROM is electrically connected to the power supply VDDSPD through a resistor, and the ground end is in the off state. The dial switch corresponding to A1 is in the open state, the A2 address interface of the EEPROM is electrically connected to the corresponding address bus through the dial switch, and is in the off state with the power supply VDDSPD and the ground end. The dial switch corresponding to A1 is in the off state, and is in the off state with the power supply VDDSPD. The A2 address interface of the EEPROM is electrically connected to the ground end through a resistor.

[0051] It can be understood that the IIC address conversion circuit 100 can include an inverter and a resistor. At least one address interface of the EEPROM is electrically connected to the corresponding preset address bus through the inverter. At least one address interface of the EEPROM corresponding to the high-level preset address bus is grounded through a resistor, and / or at least one address interface of the EEPROM corresponding to the low-level preset address bus is electrically connected to the power supply through a resistor. The other address interfaces are directly electrically connected to the corresponding preset address bus.

[0052] In the present application, the IIC address of the address bus is converted by the IIC address conversion circuit 100, the IIC interface address of the EEPROM device is different from the IIC address stored in the SPD of the corresponding SODIMM to be detected, so as to realize the differentiation of the EEPROM and the SPD, and then the plugged-in times and the remaining plugged-in times of the adapter plate stored in the EEPROM can be accurately read and updated according to the IIC address stored in the EEPROM, the service life of the DDR adapter plate is determined according to the updated plugged-in times or the updated remaining plugged-in times, the accurate detection of the service life of the DDR adapter plate is realized, and the test efficiency and quality of the SODIMM are improved.

[0053] In addition, the present application also provides a service life detection method of an adapter plate, which refers to Figure 3 , Figure 3 The present application is a flowchart of the first embodiment of the service life detection method of the adapter plate.

[0054] In the present embodiment, the service life detection method of the adapter plate is applied to a DDR adapter plate, and the service life detection method of the adapter plate comprises steps S110-S130: In step S110, when the plugged-in times updating instruction is received, the plugged-in times and the remaining plugged-in times of the DDR adapter plate are read in the EEPROM based on the target IIC address of the EEPROM. In step S120, the plugged-in times and the remaining plugged-in times are updated to obtain the updated plugged-in times and the updated remaining plugged-in times. In step S130, the updated plugged-in times and the updated remaining plugged-in times are written into the EEPROM.

[0055] In the present embodiment, when the DDR adapter plate is plugged in, the tester can trigger the plugged-in times updating instruction through the corresponding key, etc., when the plugged-in times updating instruction is received, the CPU determines the target IIC address of the EEPROM, and reads the plugged-in times and the remaining plugged-in times of the DDR adapter plate in the EEPROM based on the target IIC address. In a feasible implementation manner, step S110 can comprise steps S111-S113: In step S111, two IIC addresses are obtained through the IIC bus, wherein the two IIC addresses comprise the target IIC address in the EEPROM and the IIC address in the SPD of the SODIMM to be detected. In step S112, the slave IIC address corresponding to the mainboard IIC bus is obtained, and the target IIC address in the EEPROM is determined in the two IIC addresses based on the slave IIC address. Step S113, reading the plugged-in times and the remaining plugged-in times of the DDR adapter corresponding to the target IIC address in the EEPROM based on the target IIC address.

[0056] In this embodiment, the CPU obtains two IIC addresses through the IIC bus, the two IIC addresses include the target IIC address in the EEPROM and the IIC address in the SPD of the SODIMM to be detected, and simultaneously obtains the slave IIC address corresponding to the mainboard IIC bus, which includes the addresses set by the IIC address interfaces A2, A1 and A0 of the mainboard.

[0057] Then, the CPU compares the slave IIC address with the two IIC addresses, the IIC address in the SPD is the same as the slave IIC address, and the target IIC address in the EEPROM is different from the slave IIC address, so that the target IIC address stored in the EEPROM can be accurately determined. Based on the target IIC address, the plugged-in times and the remaining plugged-in times of the DDR adapter corresponding to the target IIC address in the EEPROM are read, so that the CPU can accurately read the EEPROM to accurately obtain the plugged-in times and the remaining plugged-in times in the EEPROM.

[0058] After obtaining the plugged-in times and the remaining plugged-in times, the plugged-in times and the remaining plugged-in times are updated to obtain the updated plugged-in times and the updated remaining plugged-in times, i.e. the plugged-in times + 1 and the remaining plugged-in times - 1.

[0059] After obtaining the updated plugged-in times and the updated remaining plugged-in times, the CPU writes the updated plugged-in times and the updated remaining plugged-in times into the EEPROM to update the plugged-in times and the remaining plugged-in times in the EEPROM. In a possible implementation, step S130 can include steps S131-S132. Step S131, determining whether the updated remaining plugged-in times are greater than or equal to a preset value. Step S132, if the updated remaining plugged-in times are greater than or equal to the preset value, writing the updated plugged-in times and the updated remaining plugged-in times into the EEPROM.

[0060] In this embodiment, after obtaining the updated plugged-in times and the updated remaining plugged-in times, it is determined whether the updated remaining plugged-in times are greater than or equal to a preset value, and the preset value can be set to 1, i.e. determining whether the updated remaining plugged-in times are greater than or equal to 1.

[0061] If the updated remaining plug-in times is greater than or equal to the preset value, the updated plug-in times and the updated remaining plug-in times are written into the EEPROM, that is, the updated plug-in times and the updated remaining plug-in times are written into the EEPROM through the target IIC address, so as to update the plug-in times and the remaining plug-in times in the EEPROM, that is, to update the service life of the DDR adapter board.

[0062] In an implementable embodiment, after step S131, the service life detection method of the adapter board further includes: If the updated remaining plug-in times is less than the preset value, step S133 outputs prompt information that the DDR adapter board has reached the maximum test times.

[0063] In the embodiment, if the updated remaining plug-in times is less than the preset value, that is, the updated remaining plug-in times is 0, at this time, the CPU outputs the prompt information that the DDR adapter board has reached the maximum test times, prompting that the service life of the golden finger in the DDR adapter board has been consumed, and the DDR adapter board should be replaced as soon as possible.

[0064] The service life detection method of the adapter board provided in the embodiment includes the following steps: when the plug-in times updating instruction is received, the plug-in times and the remaining plug-in times of the DDR adapter board corresponding to the target IIC address of the EEPROM are read in the EEPROM; then the plug-in times and the remaining plug-in times are updated to obtain the updated plug-in times and the updated remaining plug-in times; and finally the updated plug-in times and the updated remaining plug-in times are written into the EEPROM. The service life of the current DDR adapter board can be accurately determined by reading the plug-in times and the remaining plug-in times in the EEPROM, the accurate detection of the service life of the DDR adapter board is realized, and the test efficiency and quality of the SODIMM are improved.

[0065] It should be noted that the above examples are only used for understanding the present application and do not constitute a limitation on the service life detection method of the adapter board of the present application. More forms of simple transformation based on this technical concept are within the protection scope of the present application.

[0066] The present application further provides a service life detection device of an adapter board, which includes: The reading module is configured to read the plug-in times and the remaining plug-in times of the DDR adapter board corresponding to the target IIC address of the EEPROM when the plug-in times updating instruction is received. The updating module is configured to update the plug-in times and the remaining plug-in times to obtain the updated plug-in times and the updated remaining plug-in times. The write module is configured to write the updated pluggable times and the updated remaining pluggable times into the EEPROM.

[0067] The adapter plate life detection device provided by the present application adopts the adapter plate life detection method in the above embodiments, and can solve the technical problem of how to detect and record the service life of the DDR4 adapter plate and improve the test efficiency and quality of the SODIMM. Compared with the prior art, the adapter plate life detection device provided by the present application has the same beneficial effects as the adapter plate life detection method provided by the above embodiments, and other technical features in the adapter plate life detection device are the same as the features disclosed in the above embodiments, which will not be repeated here.

[0068] The present application provides an adapter plate life detection device, which comprises at least one processor and a memory connected with the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the adapter plate life detection method in the above embodiment one.

[0069] Reference will now be made to the drawings, in which Figure 4 which shows a structural schematic diagram of an adapter plate life detection device suitable for implementing the embodiments of the present application. The adapter plate life detection device in the embodiments of the present application can include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistant), PADs (Portable Application Description), PMPs (Portable Media Player), vehicle terminals (such as vehicle navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. Figure 4 The adapter plate life detection device shown is only an example, and should not impose any limitation on the functions and use range of the embodiments of the present application.

[0070] As Figure 4As shown, the adapter board life detection device can include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 1002 or programs loaded from a storage device 1003 into a random access memory (RAM) 1004. Various programs and data required for the operation of the adapter board life detection device are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the adapter board life detection device to communicate with other devices wirelessly or by wire to exchange data. Although the adapter board life detection device with various systems is shown in the figure, it should be understood that all the systems shown are not required to be implemented or possessed. More or fewer systems can be alternatively implemented or possessed.

[0071] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by a communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.

[0072] The adapter board life detection device provided by the present disclosure adopts the adapter board life detection method in the above embodiments, and can solve the technical problem of how to detect and record the service life of the DDR4 adapter board, and improve the test efficiency and quality of the SODIMM. Compared with the prior art, the adapter board life detection device provided by the present disclosure has the same beneficial effects as the adapter board life detection method provided by the above embodiments, and other technical features in the adapter board life detection device are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0073] It should be understood that various aspects of the disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any appropriate manner in any one or more embodiments or examples.

[0074] The above description is merely illustrative of the application and is not intended to limit the scope of the application. Any variations and modifications that can be made by any person skilled in the art within the spirit and scope of the application are intended to be encompassed by the application. The scope of the application is defined by the appended claims.

[0075] The application provides a computer readable storage medium having computer readable program instructions (i.e. computer programs) stored thereon, the computer readable program instructions being used to perform the life detection method of the adapter plate in the above embodiments.

[0076] The computer readable storage medium provided by the application may, for example, be a U disk, but is not limited to an electric, magnetic, optical, electromagnetic, infrared, or semiconductor system, system, or device, or any combination thereof. More specific examples of the computer readable storage medium can include, but are not limited to, an electric connection having one or more conductive wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination thereof. In the present embodiment, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer readable storage medium can be transmitted by any appropriate medium, including but not limited to an electric wire, an optical cable, an RF (Radio Frequency), etc., or any appropriate combination thereof.

[0077] The above computer readable storage medium can be contained in the life detection device of the adapter plate; or can exist separately and not be assembled into the life detection device of the adapter plate.

[0078] The computer readable storage medium described above carries one or more programs, when the one or more programs are executed by the adapter life detection device, the adapter life detection device is caused to: when a plug-in frequency update instruction is received, read the plugged-in frequency and the remaining plug-in frequency of the DDR adapter in the EEPROM based on the target IIC address of the EEPROM; update the plugged-in frequency and the remaining plug-in frequency to obtain updated plugged-in frequency and updated remaining plug-in frequency; and write the updated plugged-in frequency and the updated remaining plug-in frequency into the EEPROM.

[0079] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0080] The flow diagrams and the block diagrams in the drawings are illustrations of possible architectures, functions, and operations for systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

[0081] The modules described in the embodiments of the present application can be implemented in the form of software or in the form of hardware. In some cases, the name of the module does not constitute a limitation on the module itself.

[0082] The computer readable storage medium provided in the present application is a computer readable storage medium, which stores computer readable program instructions (i.e., a computer program) for executing the life detection method of the adapter plate, and can solve the technical problem of how to detect and record the service life of the DDR4 adapter plate and improve the test efficiency and quality of the SODIMM. Compared with the prior art, the computer readable storage medium provided in the present application has the same beneficial effects as the life detection method of the adapter plate provided in the above embodiments, and will not be described here.

[0083] The present application also provides a computer program product comprising a computer program, which, when executed by a processor, implements the steps of the life detection method of the adapter plate as described above.

[0084] The computer program product provided in the present application can solve the technical problem of how to detect and record the service life of the DDR4 adapter plate and improve the test efficiency and quality of the SODIMM. Compared with the prior art, the computer program product provided in the present application has the same beneficial effects as the life detection method of the adapter plate provided in the above embodiments, and will not be described here.

[0085] The above only describes some embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation, direct / indirect application in other related technical fields based on the technical concept of the present application, and the contents of the present application and the accompanying drawings are included in the patent protection scope of the present application.

Claims

1. A DDR adapter, characterized by, The DDR adapter plate comprises a golden finger, an EEPROM, a slot, and an IIC address conversion circuit; The EEPROM is electrically connected with the IIC address conversion circuit, the IIC address conversion circuit is electrically connected with an address bus in an IIC bus, one end of the address bus is electrically connected with an IIC address interface of the golden finger, and the other end is electrically connected with an IIC address interface of the slot; The IIC address conversion circuit is used for converting an IIC address of the address bus to obtain a target IIC address, and writing the target IIC address into the EEPROM; The EEPROM is used for storing a plugged-in times corresponding to the adapter plate and a remaining plugged-in times.

2. The DDR adapter of claim 1, wherein, The IIC address conversion circuit comprises an inverter, and an address interface of the EEPROM is electrically connected with a preset address bus of the address bus through the inverter.

3. The DDR adapter of claim 2, wherein, At least one address interface of the EEPROM is electrically connected with a corresponding preset address bus through the inverter, and other address interfaces are respectively electrically connected with corresponding preset address buses.

4. The DDR adapter of claim 1, wherein, The IIC address conversion circuit comprises a resistor; At least one address interface of the EEPROM corresponding to a high-level preset address bus is grounded through the resistor, and / or at least one address interface corresponding to a low-level preset address bus is electrically connected with a power supply through the resistor.

5. The DDR adapter plate of any one of claims 1 to 4, wherein, The processor updates the plugged-in times and the remaining plugged-in times in the EEPROM based on the target IIC address corresponding to the EEPROM.

6. A method of detecting the life of an adapter plate, characterized by, The life detection method of the DDR adapter plate of any one of claims 1 to 5 comprises: When a plugged-in times update instruction is received, the plugged-in times and the remaining plugged-in times corresponding to the DDR adapter plate in the EEPROM are read based on the target IIC address corresponding to the EEPROM; The plugged-in times and the remaining plugged-in times are updated to obtain updated plugged-in times and updated remaining plugged-in times; The updated plugged-in times and the updated remaining plugged-in times are written into the EEPROM.

7. The lifespan testing method for the adapter board as described in claim 6, characterized in that, The step of reading the plugged-in times and the remaining plugged-in times corresponding to the DDR adapter plate in the EEPROM based on the target IIC address corresponding to the EEPROM when the plugged-in times update instruction is received comprises: Two IIC addresses are obtained through the IIC bus, wherein the two IIC addresses comprise the target IIC address in the EEPROM and an IIC address in an SPD of a to-be-detected SODIMM; A slave IIC address corresponding to a mainboard IIC bus is obtained, and the target IIC address in the EEPROM is determined from the two IIC addresses based on the slave IIC address; The plugged-in times and the remaining plugged-in times corresponding to the DDR adapter plate in the EEPROM are read based on the target IIC address.

8. The method of claim 6 or 7, wherein The step of writing the updated plugged-in times and the updated remaining plugged-in times into the EEPROM comprises: It is determined whether the updated remaining plugged-in times are greater than or equal to a preset value; If the updated remaining plugged-in times are greater than or equal to the preset value, the updated plugged-in times and the updated remaining plugged-in times are written into the EEPROM.

9. The lifespan testing method for the adapter board as described in claim 8, characterized in that, After the step of determining whether the updated remaining plug-in times is greater than or equal to the preset value, the adapter plate life detection method further comprises: If the updated remaining plug-in times is equal to the preset value, a prompt information that the DDR adapter plate has reached the maximum test times is output.

10. A storage medium, characterized by The storage medium is a computer readable storage medium, and the storage medium stores a computer program. When the computer program is executed by the processor, the steps of the adapter plate life detection method according to any one of claims 6 to 9 are implemented.

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