Message transmission system and method, computer equipment and medium

Abstract

The invention relates to the technical field of computers, and discloses a message transmission system and method, computer equipment and a medium, the system comprises at least one message processing device and an interconnection arbitration module; the message processing device is used for identifying the type of a message when the message transmitted by the message receiving port connected with the message processing device is received; when the type of the message is a multicast message, adding the message into an RAM (Random Access Memory) for storage, and latching message copy information in the RAM; copying a preset number of messages according to the message copying information, and determining a destination port number corresponding to a destination port for receiving each message; determining a configuration rule according to the destination port number; the message is modified according to the configuration rule and then sent to the interconnection arbitration module; and the interconnection arbitration module transmits the modified message to a destination port corresponding to the modified message. The strict requirement for rear-end layout and wiring is reduced, the requirement of the PCIe switching device for the number of multiple ports is met, and the expandability of the system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a message transmission system and method, computer equipment and medium. BACKGROUND

[0002] With the rapid development of computer and communication technology, the Peripheral Component Interconnect Express (PCIe) has become one of the widely used high-speed interface standards in modern computer systems. As a high-performance and highly scalable bus architecture, PCIe enables fast data transmission and communication between various devices, and its application fields cover computers, servers, embedded systems, network devices, etc.

[0003] In a complex PCIe system, the PCIe switch is an important basic component. It is mainly responsible for expanding and connecting the communication between different PCIe devices and ensuring the reliable transmission of data. The PCIe switch is located on the data path and acts as a data forwarder that bridges different PCIe devices. This bridging operation is visible to the devices in the system, that is, after the devices are connected to the PCIe system network through the PCIe switch, they can communicate normally.

[0004] However, the traditional multicast implementation method has the problems of being unable to meet the PCIe switch's demand for the number of ports, poor scalability, etc. Especially as the demand for the number of ports increases, the direct connection between the internal ports requires strict layout and wiring requirements for the back end. SUMMARY

[0005] Therefore, the present application provides a message transmission system and method, computer equipment and medium to solve the problems of the traditional multicast implementation method being unable to meet the PCIe switch's demand for the number of ports and poor scalability.

[0006] In a first aspect, the present application provides a message transmission system, which comprises at least one message processing device and an interconnection arbitration module. Each message processing device is connected to a message receiving port in a message transmission device and connected to the interconnection arbitration module. The interconnection arbitration module is also connected to a message sending port in the message transmission device.

[0007] The packet processing device is used for identifying a packet type when receiving a packet transmitted by a packet receiving port connected to the packet processing device; when the packet type is a multicast packet, storing the packet in a RAM and locking packet replication information in the RAM; replicating the packet a preset number of times according to the packet replication information, and determining a destination port number corresponding to a destination port receiving each copy of the packet; determining a configuration rule according to the destination port number; and sending the packet to an interconnection arbitration module after modifying the packet according to the configuration rule, wherein modifying the packet at least includes modifying a destination address of the multicast packet to a destination address corresponding to the destination port.

[0008] The interconnection arbitration module transmits the modified packet to a corresponding destination port.

[0009] The packet transmission method provided by the application has the following advantages:

[0010] The packet processing device is used for identifying a packet type when receiving a packet transmitted by a packet receiving port connected to the packet processing device; when the packet type is a multicast packet, storing the packet in a RAM and locking packet replication information in the RAM; replicating the packet a preset number of times according to the packet replication information, and determining a destination port number corresponding to a destination port receiving each copy of the packet; determining a configuration rule according to the destination port number; and sending the packet to an interconnection arbitration module after modifying the packet according to the configuration rule, wherein modifying the packet at least includes modifying a destination address of the multicast packet to a destination address corresponding to the destination port.

[0011] In an optional embodiment, the packet processing device comprises a packet distribution module, a packet replication module, and a packet modification module.

[0012] The packet distribution module is used for identifying a packet type when receiving a packet transmitted by a packet receiving port connected to the packet processing device.

[0013] The packet replication module is configured to, when the packet type is a multicast packet, store the multicast packet in the RAM, write packet replication information into the RAM and latch the packet replication information when the packet header information is written in the RAM, determine the packet replication quantity according to the packet replication information, replicate the packet according to the packet replication quantity, and determine the destination port number corresponding to the destination port receiving each copy of the packet; and query the multicast configuration register corresponding to the destination port number according to the destination port number.

[0014] The packet modification module is configured to modify the packet according to the rule in the multicast configuration register and transmit the modified packet to the interconnection arbitration module.

[0015] Specifically, the packet distribution module, the packet replication module and the packet modification module are configured in the packet processing device. The packet type is identified by the packet distribution module. When the packet type is a multicast packet, the packet replication module stores the packet in the RAM for subsequent replication and reading. Specifically, the packet replication information is written into the RAM and latched when the packet header information is written in the RAM. Then, the packet replication quantity is determined according to the packet replication information. The packet is replicated according to the packet replication quantity, and the destination port number corresponding to the destination port receiving each copy of the packet is determined. The multicast configuration register corresponding to the destination port number is queried according to the destination port number. The packet modification rule is stored in the multicast configuration register. The packet modification module can modify the packet according to the rule in the multicast configuration register and transmit the modified packet to the interconnection arbitration module. In this way, the efficiency of packet processing can be improved. Especially for multicast packets, the packet replication module is specially processed. The packet is stored in the RAM, accurately replicated according to the replication information, and the destination port and the corresponding port number are determined to ensure accurate distribution of multicast packets. By querying the multicast configuration register, the packet modification module can modify the packet according to the rule in the multicast configuration register, so that the packet can adapt to different transmission requirements and network environments, improving the flexibility and adaptability of the system.

[0016] In an optional embodiment, the packet includes a plurality of data blocks, and the packet replication module is specifically configured to:

[0017] When the packet type is a multicast packet, the preconfigured first selector and the first register are hit to output a write enable signal, a data write valid signal and a write address valid signal;

[0018] According to the write enable signal, each data block included in the packet is sequentially written into the RAM and stored;

[0019] According to the data block already written in the RAM and the write address valid signal, the address is incremented from the packet header until all data blocks corresponding to the packet are written, and the end address of the packet is recorded.

[0020] determining the message replication information according to a data transmission protocol corresponding to the message;

[0021] writing the message replication information into the RAM for latching.

[0022] Specifically, since each message can include multiple data blocks, the message replication module is specifically configured to output a write enable signal, a data write valid signal, and a write address valid signal after the preconfigured first selector and the first register are hit when it is determined that the message type is a multicast message. The three valid signals ensure that the data blocks can be written into the RAM and record the write address. According to the write enable signal, each data block included in the message is written into the RAM in sequence and stored. According to the data blocks that have been written into the RAM and the write address valid signal, the address is incremented from the message header until all data blocks corresponding to the message are written, and the message end address is recorded, so that when the message is replicated subsequently, the message header address and the message end address can be used to determine when to end the replication of a message. According to the data transmission protocol corresponding to the message, the message replication information is determined to facilitate subsequent operations related to message replication. Finally, the message replication information is written into the RAM for latching.

[0023] In an optional implementation, the message replication information is composed of hexadecimal data, and the message replication information is used to indicate the number of message replication and the destination port number corresponding to the target port receiving each message; wherein the number of message replication is determined according to the number of 1s in the hexadecimal data; and each destination port number is determined according to the position of 1 in the hexadecimal data.

[0024] The message replication module is specifically configured to:

[0025] when it is determined that the write enable signal is valid, jump the state of the state machine that controls the writing and reading of the RAM from an idle state to a running state;

[0026] determine the number of times of reading out the message according to the number of 1s in the hexadecimal data, so as to determine the number of message replication;

[0027] read the data blocks from the RAM until the message end position is reached, so as to replicate a message;

[0028] identify the position of 1 in the hexadecimal data to determine each destination port number;

[0029] query the multicast configuration register corresponding to the destination port number according to the destination port number, and determine the destination port receiving each message.

[0030] When the enabling signal of the multicast message is identified each time, the output to-be-sent data signal, the to-be-sent message data valid signal, and the destination port valid signal are output through the second selector and the second register, so as to output one message, until the messages corresponding to the number of message copies are confirmed to be output, and the operation is ended.

[0031] Specifically, in the method, the number and position of 1 in the hexadecimal data can accurately indicate the number of message copies and the destination port number of each message, realizing accurate control of message copying and improving the accuracy of message distribution. Moreover, the number of message copies is determined according to the number of 1 in the hexadecimal data, and the calculation method is simple and efficient, which can quickly determine the number of message copies required. The position of 1 in the hexadecimal data determines the destination port number, which can accurately specify the receiving port for each copied message, ensuring that the message can be accurately transmitted to the target position. Furthermore, through the control of the state machine, the message reading and copying operation is only performed when the write enabling signal is valid, avoiding unnecessary resource consumption and improving the utilization rate of system resources. Through a series of signal processing and register operations, it can also ensure that each message can be accurately and effectively output to the corresponding destination port, improving the reliability of message transmission. The method has strong scalability. Especially when the number of message copies or the destination port needs to be adjusted, it only needs to modify the message copy information accordingly, which is convenient for system upgrading and maintenance.

[0032] In an optional implementation, the message copy module is further configured to:

[0033] After each data block is read, the state value of the back pressure signal is identified;

[0034] When the state value of the back pressure signal is valid, the next data block is stopped from being read;

[0035] Until the state value of the back pressure signal is invalid, the next data block is continued to be read.

[0036] Specifically, by identifying the state value of the back pressure signal, the next data block is stopped from being read when the back pressure signal is valid, which can effectively avoid congestion in the data processing process and ensure the smoothness of data transmission. When the state value of the back pressure signal is invalid, the next data block is continued to be read. Avoiding system failure or error that may be caused by data accumulation, improving the stability and reliability of the entire system. According to the back pressure signal, the reading operation of the data block is adjusted flexibly, which helps to more reasonably allocate system resources and improve resource utilization efficiency. This method can adapt to different data processing situations, enhancing the adaptability of the system to various working scenarios.

[0037] In an optional implementation, the message copy module is further configured to:

[0038] When the messages are read in sequence according to the message copy quantity, the state of the RAM write and read state machine is jumped to an indication state that the message reading is completed;

[0039] And, at the moment when the state of the RAM write and read state machine is jumped to the indication state that the message reading is completed, the state value of the back pressure signal is controlled to be in the invalid state after a preset time period.

[0040] Specifically, when the messages are read in sequence according to the message copy quantity, the state of the RAM write and read state machine is jumped to an indication state that the message reading is completed, which can clearly indicate the completion of the message reading work, facilitating subsequent operation and processing of the system. However, the state value of the back pressure signal is not immediately controlled to be in the invalid state after the state of the RAM write and read state machine is jumped to the indication state that the message reading is completed, but the state value of the back pressure signal is controlled to be in the invalid state after a preset time period, in order to avoid system errors or abnormalities caused by uncertain factors. By adjusting the state value of the back pressure signal through the preset time, the rhythm of data transmission can be reasonably adjusted. Moreover, after the message reading is completed, the back pressure is timely released, which can also prepare for the next round of data processing or other operations, improving the overall efficiency and resource utilization of the system. Through the clear state jump and control of the back pressure signal, the message replication module and other parts of the system can work better in cooperation, ensuring that the entire system runs more smoothly and efficiently.

[0041] In an optional embodiment, the interconnection arbitration module is specifically configured to:

[0042] match a data transmission path corresponding to each message according to a routing algorithm;

[0043] transmit the message to a destination port according to the data transmission path.

[0044] Specifically, the interconnection arbitration module flexibly matches a corresponding data transmission path for each message according to a routing algorithm, which can improve the efficiency of message transmission and reduce transmission delay. In addition, the adaptability and scalability of the system are improved. In particular, by reasonably matching the data transmission path, network resources can be fully utilized to avoid resource waste and congestion. An effective interconnection arbitration mechanism helps to improve the performance of the entire system, so that data can be quickly and accurately transmitted between different ports.

[0045] In a second aspect, the present application provides a message transmission method, which is applied to the message transmission system of the first aspect and any of the embodiments, the system comprising at least one message processing device and an interconnection arbitration module, each message processing device being connected with a message receiving port in a message transmission device and connected with the interconnection arbitration module, and the interconnection arbitration module being further connected with a message sending port in the message transmission device; the method comprising:

[0046] When receiving a message transmitted by the message receiving port connected with the message processing device, the message processing device identifies the message type; when the message type is a multicast message, the message is stored in the RAM, and the message replication information is latched in the RAM; a preset number of copies of the message are replicated according to the message replication information, and the destination port number corresponding to the destination port receiving each copy of the message is determined; the configuration rule is determined according to the destination port number; and the message is modified according to the configuration rule and then sent to the interconnection arbitration module, wherein the modification of the message at least comprises modifying the destination address of the multicast message to the destination address corresponding to the destination port.

[0047] The interconnection arbitration module transmits the modified message to the corresponding destination port.

[0048] The message transmission device provided by the present application has the following advantages:

[0049] When receiving a message transmitted by the message receiving port connected with the message processing device, the message processing device identifies the message type; when the message type is a multicast message, the message is stored in the RAM, and the message replication information is latched in the RAM; a preset number of copies of the message are replicated according to the message replication information, and the destination port number corresponding to the destination port receiving each copy of the message is determined; the configuration rule is determined according to the destination port number; and the message is modified according to the configuration rule and then sent to the interconnection arbitration module, wherein the modification of the message at least comprises modifying the destination address of the multicast message to the destination address corresponding to the destination port.

[0050] In a third aspect, the present application provides a computer device, comprising: a memory and a processor, which are connected with each other in communication, and the memory stores computer instructions; the processor executes the computer instructions to perform the packet transmission method of the second aspect.

[0051] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions for making a computer execute the packet transmission method of the second aspect.

[0052] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions for making a computer execute the packet transmission method of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0054] Figure 1 is a structural block diagram of a packet transmission system provided by an embodiment of the present application;

[0055] Figure 2 is a structural block diagram of a packet transmission system provided by an embodiment of the present application, taking PCIe Switch as an example;

[0056] Figure 3 is a schematic diagram of the internal structure of a PCIe Switch provided by an embodiment of the present application;

[0057] Figure 4 is a flowchart of a packet processing method specifically executed by a packet replication module provided by the present application;

[0058] Figure 5 is a state jump diagram of a state machine for writing and reading a control RAM provided by the present application;

[0059] Figure 6 is a schematic diagram of a data transmission topology provided by the present application;

[0060] Figure 7 is a schematic diagram of a spidergon topology provided by the present application;

[0061] Figure 8 is a flowchart of a packet transmission method according to an embodiment of the present application;

[0062] Figure 9 Figure 1 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0063] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0064] With the rapid development of computer and communication technologies, PCIe has become one of the widely used high-speed interface standards in modern computer systems. As a high-performance and highly scalable bus architecture, PCIe enables fast data transmission and communication between various devices, and its application fields cover computers, servers, embedded systems, network devices, etc.

[0065] In a complex PCIe system, PCIe Switch is an important basic component. It is mainly responsible for expanding and connecting the communication between different PCIe devices and ensuring the reliable transmission of data. PCIe Switch is located on the data path and acts as a data forwarder that bridges different PCIe devices. This bridging operation is visible to the devices in the system, i.e., after the devices are connected to the PCIe system network through the PCIe Switch, they can communicate normally.

[0066] At present, the traditional multicast implementation method often cannot meet the demand of PCIe Switch for the number of multi-port, and has poor expansibility. As the demand for the number of ports is getting larger and larger, the direct connection between the internal ports has high requirements for the layout and wiring of the back end. Moreover, the unified processing method of unicast / multicast messages has a loss of performance requirements for unicast messages, which affects the real-time performance requirements of unicast message transmission.

[0067] In the related art, a typical 32-port PCIe Switch multicast implementation method is provided, as follows:

[0068] There are 1 upstream port and 31 downstream ports, the message distribution module sends the received single / multicast message to the multicast message modification module, the multicast message modification module modifies the most 32-way multicast message which needs to be output according to the multicast configuration, and then sends the most 32-way multicast message to the most 32 ports.

[0069] Some related technologies only optimize the PCIE system at the application level, and do not provide optimization at the physical implementation layer, that is, there is no method for optimizing the layout and wiring at the backend.

[0070] To solve the above problems, the embodiment of the present application provides a message transmission embodiment, it should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system (computer device) including a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0071] In the embodiment, a message transmission system is provided, which can be used in terminal equipment such as mobile phones, tablet computers, etc. Figure 1 As shown in the structure block diagram of the message transmission system provided by the embodiment of the present application, Figure 1 The system comprises at least one message processing device 101 and an interconnection arbitration module 102, each message processing device 101 is connected with a message receiving port in a message transmission device and connected with the interconnection arbitration module 102; the interconnection arbitration module 102 is also connected with a message sending port in the message transmission device.

[0072] The message processing device 101 is used for identifying the message type when receiving the message transmitted by the message receiving port RX connected with itself; when the message type is a multicast message, the message is stored in the RAM and the message replication information is latched in the RAM; the message is replicated a preset number according to the message replication information, and the destination port number corresponding to the destination port receiving each message is determined; the configuration rule is determined according to the destination port number; the message is modified according to the configuration rule and then sent to the interconnection arbitration module, wherein the modification of the message at least includes modifying the destination address of the multicast message to the destination address corresponding to the destination port;

[0073] The interconnection arbitration module transmits the modified message to the corresponding destination port.

[0074] Specifically, when the packet processing device 101 receives a packet transmitted by a packet receiving port connected to itself, the packet type is first identified. The packet type includes unicast packet, multicast packet, broadcast packet, etc.

[0075] When the packet type is identified as a multicast packet, the packet needs to be added to the RAM for storage. At the same time, the packet replication information also needs to be latched in the RAM. The packet replication information is determined according to the data transmission protocol. In a specific example, the packet data transmission protocol is, for example, PCIe data transmission protocol.

[0076] Then, according to the packet replication information, the packet is replicated a predetermined number of times, and the destination port number corresponding to each packet destination port is determined. The packet replication information can indicate the number of packet replication and the destination port number. Finally, according to the destination port number, the configuration rule is determined, and the packet is modified according to the configuration rule and sent to the interconnection arbitration module. The packet modification at least includes modifying the RAM address to the destination address corresponding to the destination port. Then, the interconnection arbitration module can transmit the modified packet to the corresponding destination port.

[0077] The packet transmission system is taken as an example of PCIe Switch, and the internal structure of PCIe Switch is shown in Figure 2 The PCIe Switch has a total of 64 ports, 1 Upsteam Port (upstream port) and 63 Downsteam Port (downstream port); the receiving ends of the 64 ports are respectively connected to the packet processing device 101 and the interconnection arbitration module, and the packet processing device 101 is connected to the sending end of each port. After the packet processing device 101 processes the received packet, it can be sent to one or more sending ports TX of the 64 ports through the interconnection arbitration module, and then sent to the corresponding receiving equipment through the sending port.

[0078] The packet transmission system provided by the embodiment of the application comprises a packet processing device 101. When receiving a packet transmitted by a packet receiving port connected to the packet processing device 101, the packet processing device 101 identifies the type of the packet. When the type of the packet is a multicast packet, the packet processing device 101 stores the multicast packet in a RAM and latches packet replication information in the RAM. According to the packet replication information, the packet processing device 101 replicates the packet a preset number of times, determines a destination port number corresponding to a destination port receiving each copy of the packet, determines a configuration rule based on the destination port number, and finally sends the packet to an interconnection arbitration module after modifying the packet according to the configuration rule, and transmits the modified packet to the destination port through the interconnection arbitration module. In this process, the packet sending port and the packet receiving port do not need to be connected in a point-to-point manner, but are connected through the interconnection arbitration module. That is, the method avoids the direct connection between two internal ports, reduces the harsh requirements on the back-end layout and wiring, meets the demand of the PCIe switching device for the number of ports, avoids the limitations of the traditional multicast implementation method, and improves the scalability of the system. Moreover, in the method, a series of operations such as identifying the type of the packet, replicating the packet, determining the destination port number, modifying the packet, and transmitting the packet can ensure reliable transmission of data. Furthermore, according to the packet replication information, the destination port number and the configuration rule are determined, the packet is flexibly processed and transmitted, which helps to cope with various communication demands that may occur when the packet processing device 101 is connected to different devices. The device can communicate normally, and the system is also convenient to manage and maintain.

[0079] In the embodiment, a packet transmission system is provided, which can be used in the mobile terminal such as a mobile phone, a tablet computer and the like. Figure 2 The structure block diagram of the packet transmission system according to the embodiment of the application is shown in FIG. 1. Figure 3 As shown in FIG. 1, the packet processing device 101 in the system can comprise a packet distribution module, a packet replication module and a packet modification module. Figure 2 The PCIe Switch is taken as an example for description of the packet transmission system, and the internal structure of the PCIe Switch is shown in FIG. 2. Figure 3 As shown in FIG. 2, the packet distribution module in the packet processing device 101 first receives a packet transmitted by a packet receiving port connected to the packet processing device 101, and identifies the type of the packet.

[0080] The packet replication module is configured to store the multicast packet in the RAM when the type of the packet is a multicast packet, write packet replication information into the RAM and latch the packet replication information when writing the packet header information in the RAM, determine the number of replicated packets according to the packet replication information, replicate the packet according to the number of replicated packets, determine a destination port number corresponding to a destination port receiving each copy of the packet, and query a multicast configuration register corresponding to the destination port number according to the destination port number.

[0081] The packet modification module is configured to modify the packet according to the rules in the multicast configuration register and transmit the modified packet to the interconnection arbitration module.

[0082] Specifically, the packet distribution module is a standard module for transmitting and processing PCIe protocol stack, and mainly completes packet analysis, response and exception handling of the transaction layer of PCIe. The packet analysis is based on PCIe protocol to analyze transaction layer packets (TLPs), i.e., TLP packets, and distinguish different types of packets, such as unicast, multicast and broadcast packet types. The different types of packets are responded, forwarded or handled abnormally.

[0083] The multicast packet replication module is configured to store the multicast packet in the RAM and write the packet replication information into the RAM and latch the packet header information in the RAM when the packet type is determined to be a multicast packet. If the packet type is a unicast packet, the packet directly passes through the MUS and is output after being tapped. For details, refer to Figure 4 .

[0084] Figure 4 In the input packet type tlp_rx_mc (unicast / multicast) signal, the input packet data tlp_rx_data (packet data signal) and tlp_rx_valid (data valid signal) are shunted. Figure 4 In the third selector, 1 represents a multicast type and 0 represents a unicast type. Figure 4 In the input packet type tlp_rx_mc (unicast / multicast) signal, the input packet data tlp_rx_data (packet data signal) and tlp_rx_valid (data valid signal) are shunted.

[0085] When the packet type is 0, the to-be-sent packet data, the to-be-sent packet data valid signal and the destination port valid signal are directly output through the unicast packet bypass. Then, the signals are output after being tapped by the second selector and the second register.

[0086] When the packet type is 1, the received packet data and the received packet data valid signal are output. Then, the write enable signal, the data write valid signal and the write address valid signal are output after being tapped by the first selector and the first register. According to the write enable signal, each data block included in the packet is sequentially written into the RAM and stored. Figure 4tlp_mc_data0 to tlp_mc_data2 in the table, and tlp_mc_dataXX and the like. According to the data block that has been written into the RAM and the write address valid signal, the address is incremented from the beginning of the packet header until all the data blocks corresponding to the packet are written, and the end address of the packet is recorded.

[0087] Specifically, according to the write enable tlp_mc_wen_r of the mc_ram (multicast RAM), the packet data tlp_mc_wdata_r is written into the mc_ram, and the write address tlp_mc_waddr_r is incremented from the beginning of the packet header until the end of the packet tail.

[0088] According to the data transmission protocol corresponding to the packet, the packet replication information is determined.

[0089] In a specific example, the number of packet replications and the transmission channel can be determined according to the PCIE5.0 protocol, and then the corresponding packet replication information is generated.

[0090] Meanwhile, the packet replication information is written into the RAM for latching. For example Figure 4 In the table, the packet replication information is written into the tlp_copy_info register.

[0091] In this process, because each packet can include multiple data blocks, the packet replication module is specifically configured to, when determining that the packet type is a multicast packet, output a write enable signal, a data write valid signal, and a write address valid signal after being punched by the preconfigured first selector and the first register. These three valid signals ensure that the data block can be written into the RAM and the write address is recorded. According to the write enable signal, each data block included in the packet is written into the RAM in sequence and stored. According to the data block that has been written into the RAM and the write address valid signal, the address is incremented from the beginning of the packet header until all the data blocks corresponding to the packet are written, and the end address of the packet is recorded, so that when the packet is replicated subsequently, the end of replicating one packet can be determined according to the packet header address and the packet end address. According to the data transmission protocol corresponding to the packet, the packet replication information is determined, which facilitates subsequent operations related to packet replication. Finally, the packet replication information is written into the RAM for latching.

[0092] In an optional example, the packet replication information is composed of hexadecimal data, and the packet replication information is used to indicate the number of packet replications and the destination port number corresponding to the target port receiving each packet; wherein the number of packet replications is determined according to the number of 1s in the hexadecimal data; and each destination port number is determined according to the position of 1 in the hexadecimal data.

[0093] The packet replication module is specifically configured to:

[0094] When it is determined that the write enable signal is valid, the state of the state machine for controlling the RAM writing and reading is jumped from an idle state to a running state;

[0095] According to the number of 1s in the hexadecimal data, the number of times of cyclic reading of the packet is determined to determine the number of packet replication;

[0096] The data block is read from the RAM until the end position of the packet is reached, so as to replicate one copy of the packet;

[0097] The positions of the 1s in the hexadecimal data are identified to determine each destination port number;

[0098] According to the destination port number, the multicast configuration register corresponding to the destination port number is queried, and the destination port receiving each copy of the packet is determined.

[0099] After each time the multicast packet enable signal is identified, the output data signal, the to-be-sent packet data valid signal, and the destination port valid signal are output through the second selector and the second register, so as to output one copy of the packet, until it is confirmed that the number of copies of the packet corresponding to the number of copies of the packet is output, and then the operation is ended.

[0100] Specifically, the packet replication information is composed of hexadecimal data, wherein the hexadecimal data is composed of 0 and 1. The number of 1s in the hexadecimal data can determine the number of packet replication; the positions of the 1s in the hexadecimal data are used to indicate the destination port number of the target port receiving one copy of the packet. When the packet replication module completes the packet replication operation, the following methods are used:

[0101] Specifically refer to Figure 5The state of the state machine controlling the RAM writing and reading is jumped from the idle state to the running state. Then, the number of times of cyclic reading of the packet is determined according to the number of 1s in the hexadecimal data, that is, the number of packet copies is determined. Then, the data block is read from the RAM until the end of the packet is reached, thereby copying one copy of the packet. The data in the hexadecimal is traversed, and the position of the first 1 in the hexadecimal data is identified in the first traversal, and a destination port number is determined. Then, the multicast configuration register corresponding to the destination port number is queried according to the destination port number, and the destination port receiving the packet is determined according to the destination port number. Then, when the multicast packet enable signal is identified, the packet data, the packet data reception enable signal, and the destination port enable signal are output after being punched through the second selector and the second register. Thus, one copy of the packet can be output. Then, the next cycle is performed, and the packet is repeatedly output according to the above operation. In each cycle, the number of traversed 1s is increased, and the destination port number is determined based on the position of the traversed 1. For example, in the second cycle, two 1s are traversed, and the subsequent operation is performed until all the 1s in the hexadecimal data are traversed. That is, the operation is ended after the packet corresponding to the number of copies of the packet is output.

[0102] That is, while the multicast packet is written into the RAM, the packet data is read from the RAM, and the packet data is cyclically read from the RAM according to the packet copy information of the multicast packet. Assuming that the 64-bit data is 64 bits, which is equivalent to one port represented by each 1 bit, and there are 64 ports as introduced above, there are 64 bits of data in total. The number of times of cyclic reading of the packet is determined according to the number of 1s in the 64-bit data; for example, the 16-bit data is 0x0000_0000_0000_1111, the multicast packet is cyclically read 4 times, and is output to the destination ports 1, 5, 9, and 13. The specific output method is that the first bit that is not 0 in the hexadecimal data is found, it is found that the first bit is the first bit, the multicast packet is output to the first destination port; when the last data at the end of the packet is to be read out, it is judged that the next bit that is not 0 in the hexadecimal data is the fifth bit. Then, after the multicast packet with the destination port 1 is output, the multicast packet is read out again and output to the destination port 5, thereby ensuring that there is no interval in the output of the multicast packet. In succession, the last two destination ports are determined to be 9 and 13, and the multicast packet is output according to the similar operation as described above.

[0103] The specific output process is described in detail in the following Figure 4As shown in the rightmost side of FIG. 1, when the enable signal of the multicast message is identified each time, the output data signal to be sent, the data valid signal of the message to be sent, and the destination port valid signal are output through the second selector and the second register, so as to output one copy of the message, until the number of copies of the message is confirmed to be output, and the operation is ended.

[0104] In addition, Figure 5 The state machine further includes an initialization state indicated by a reset signal. Since this reset condition is not the focus of the present application, it will not be described here.

[0105] In the method, the number and position of 1s in the hexadecimal data can accurately indicate the number of message copies and the destination port number of each copy of the message, realizing accurate control of message replication and improving the accuracy of message distribution. Moreover, the number of 1s in the hexadecimal data is used to determine the number of message copies, which is simple and efficient in calculation and can quickly determine the number of copies of the message that need to be replicated. The position of 1s in the hexadecimal data is used to determine the destination port number, which can accurately specify the receiving port for each copy of the message and ensure that the message can be accurately transmitted to the target position. Furthermore, through the control of the state machine, the reading and replication of the message are only performed when the write enable signal is valid, avoiding unnecessary resource consumption and improving the utilization rate of system resources. Through a series of signal processing and register operations, each copy of the message can be accurately and effectively output to the corresponding destination port, improving the reliability of message transmission. The method has strong scalability. Especially when the number of message copies or the destination port needs to be adjusted, only the message replication information needs to be modified accordingly, which is convenient for system upgrading and maintenance.

[0106] In an optional example, referring to FIG. 2, Figure 4 To reasonably adjust the system's ability to output message data and avoid congestion in the data processing process, the method further includes:

[0107] After reading each data block, the state value of the back pressure signal is identified;

[0108] When the state value of the back pressure signal is valid, the next data block is stopped from being read;

[0109] Until the state value of the back pressure signal is invalid, the next data block is continued to be read.

[0110] Referring to FIG. 3, Figure 4In the first selector, there is also a hold enable signal at the input. This hold enable signal is the back pressure signal, which is used to control the hold signal to be valid and stop reading the next data block when it is determined that there may be congestion in data reading, or before congestion occurs. When it is determined that there is no congestion in data reading, the back pressure signal is invalidated and the next data block is read.

[0111] By identifying the status value of the backpressure signal, stopping the reading of the next data block when the backpressure signal is valid effectively avoids congestion during data processing and ensures smooth data transmission. Conversely, when the backpressure signal is invalid, the reading of the next data block continues. This avoids system failures or errors that may result from data accumulation, improving the stability and reliability of the entire system. Flexible adjustment of data block reading operations based on the backpressure signal helps to allocate system resources more rationally and improve resource utilization efficiency. This method can adapt to different data processing situations, enhancing the system's adaptability to various working scenarios.

[0112] In an optional implementation, the message replication module is further configured to:

[0113] After reading the messages sequentially according to the number of message copies, the state of the RAM write and read state machines will be switched to the indication state that the message reading is complete.

[0114] Furthermore, the starting time is the moment when the state machine of RAM writing and reading transitions to the indication state that the message reading is completed. After a preset time period, the state value of the control reverse pressure signal becomes invalid.

[0115] For details, see Figure 5 As shown, after all multicast messages have been output, the MC_FSM state machine enters the TLP_RD_DONE state (all messages read), ensuring that all data read from the RAM is output. The output end switches the output message according to the current multicast message mode tlp_tx_mc. Once a multicast message has been completely output, the next input message can be processed. During the processing of multicast messages, backpressure is applied to the message input end. When the MC_FSM state machine enters the TLP_RD_IDLE state from TLP_RD_DONE, indicating that the multicast message processing is complete, the backpressure on the input message is released.

[0116] Specifically, the release time is set to begin when the RAM write / read state machine transitions to the state indicating message read completion, with a three-cycle delay to ensure all messages are output successfully. Then, the control backpressure signal is set to an invalid state. At this point, the next message can be processed. The next message may be a multicast / broadcast message or a unicast message.

[0117] In an optional example, the interconnection arbitration module is specifically configured to:

[0118] According to the routing algorithm, match the data transmission path corresponding to each message;

[0119] According to the data transmission path, transmit the message to the destination port.

[0120] In an optional example, according to the routing algorithm, match the data transmission path corresponding to each message, and according to the data transmission path, transmit the message to the destination port. For example, it can include the following ways:

[0121] Configure a data transmission topology structure, and design multiple layers of data transmission sub-structures in the data transmission topology structure. For details, see Figure 6 As shown in the figure, the multiple layers of data transmission sub-structures include input level, intermediate level and output level. Among them, the input level and the output level, and the intermediate level are all configured with multiple modules. All modules of the input level are connected with all modules of the intermediate level, and each module of the intermediate level is connected with all modules of the output level.

[0122] Among them, when a data packet enters the input level module from the input port, the module selects an intermediate level module for connection according to the destination address of the data packet, and sends the data packet to the intermediate level module. After receiving the data packet, the intermediate level module selects an output level module for connection according to the destination address of the data packet, and sends the data packet to the output level module. After receiving the data packet, the output level module sends it to the corresponding destination port.

[0123] The advantage of this way is that as long as there is a free link, connection can be established in any case, and there will be no congestion. In some specific traffic mode, temporary congestion may occur, but by rearranging the connection appropriately, the congestion can be eliminated. Moreover, the data transmission topology structure has good scalability and reliability, and the size of the network can be expanded by increasing the number of modules, and the reliability of the network can be improved by redundant connection.

[0124] In addition to the above way, it can also be realized by spidergon topology routing algorithm, for details, see Figure 7 As shown in the figure, Figure 7 One of the spidergon topology routing algorithm schematic diagram is shown, for details of its working principle, see the specific working principle of the existing spidergon topology, which will not be described here.

[0125] The packet transmission system provided by the embodiment of the present application, the interconnection arbitration module, can flexibly match the corresponding data transmission path for each packet according to the routing algorithm, can improve the efficiency of packet transmission, reduce the transmission delay, and improve the adaptability and scalability of the system. In particular, by reasonably matching the data transmission path, network resources can be fully utilized, and resource waste and congestion can be avoided. The effective interconnection arbitration mechanism helps to improve the performance of the entire system, so that data can be quickly and accurately transmitted between different ports.

[0126] The packet transmission method provided by the embodiment of the present application is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again.

[0127] The packet transmission method provided by the embodiment of the present application is applied to the packet transmission system corresponding to any of the above-mentioned embodiments, the system comprising at least one packet processing device 101 and an interconnection arbitration module 102, each packet processing device 101 being connected with a packet receiving port in a packet transmission device and connected with the interconnection arbitration module 102; the interconnection arbitration module 102 is also connected with a packet sending port in the packet transmission device; as shown in the figure, the method comprises the following steps: Figure 8

[0128] Step S801, when the packet processing device 101 receives the packet transmitted by the packet receiving port connected with itself, the packet processing device 101 identifies the type of the packet.

[0129] Step S802, when the type of the packet is a multicast packet, the packet processing device 101 stores the packet in the RAM and latches the packet replication information in the RAM.

[0130] Step S803, the packet processing device 101 replicates the packet by a preset number according to the packet replication information, and determines the destination port number corresponding to the destination port receiving each packet.

[0131] Step S804, the packet processing device 101 determines the configuration rule according to the destination port number.

[0132] Step S805, the packet processing device 101 sends the packet modified according to the configuration rule to the interconnection arbitration module.

[0133] Among them, modifying the packet at least includes adding the target port number.

[0134] Step S806, the interconnection arbitration module transmits the modified packet to the corresponding destination port.

[0135] The above-mentioned method steps have been described in detail in the above-mentioned system embodiments, and therefore will not be described again here.

[0136] ​The message transmission method provided in this embodiment, the message processing device 101, identifies the message type when it receives a message transmitted from a message receiving port connected to itself. When the message type is a multicast message, the message is added to RAM for storage, and message replication information is latched in RAM. The message is replicated a preset number according to the message replication information, and the destination port number corresponding to the destination port receiving each message is determined. Configuration rules are determined based on the destination port number, and finally, the message is modified according to the configuration rules and sent to the interconnect arbitration module. The interconnect arbitration module then transmits the modified message to the destination port. In this process, there is no need for a "point-to-point connection" between the message sending port and the message receiving port; instead, transmission is uniformly performed through the interconnect arbitration module. That is, this method avoids direct pairwise connections between internal ports, reduces the stringent requirements for backend layout and cabling, meets the multi-port requirements of PCIe switching devices, avoids the limitations of traditional multicast implementations, and improves system scalability. Furthermore, this method ensures reliable data transmission through a series of operations, including identifying message type, copying messages, determining the destination port number, modifying messages, and transmitting them. Moreover, determining the destination port number and configuration rules based on message copying information allows for flexible message processing and transmission, helping to address various communication needs that may arise when the message processing device 101 connects to different devices. This enables devices to communicate normally and also facilitates system management and maintenance.

[0137] This invention also provides a computer device for performing... Figure 7 The message transmission method shown.

[0138] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 9 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0139] The processor 10 can be a central processing unit, a network processing unit, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a generic array logic, or any combination thereof.

[0140] The memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods illustrated in the above embodiments.

[0141] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function. The data storage area can store data created by the use of the computer device according to the presentation of a small program landing page, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some alternative embodiments, the memory 20 can optionally include a memory disposed remotely with respect to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0142] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk. The memory 20 can further include a combination of the above-mentioned types of memories.

[0143] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 can be connected through a bus or other means, Figure 9 For example, the connection through the bus is taken as an example.

[0144] The input device 30 can receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, and the like. The output device 40 can include a display device, an auxiliary lighting device (such as an LED), a tactile feedback device (such as a vibration motor), and the like. The display device includes, but is not limited to, a liquid crystal display, a light emitting diode, a display, and a plasma display. In some alternative embodiments, the display device can be a touch screen.

[0145] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0146] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, the operation of the computer can invoke or provide the method and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file, etc. Correspondingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0147] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A message transmission system, characterized by, The system comprises at least one packet processing device and an interconnection arbitration module, each of the packet processing devices is connected with a packet receiving port in a packet transmission device and connected with the interconnection arbitration module; the interconnection arbitration module is also connected with a packet sending port in the packet transmission device; The packet processing device is used for identifying a packet type when receiving a packet transmitted by the packet receiving port connected with itself; when the packet type is a multicast packet, the packet is stored in a RAM and packet replication information is latched in the RAM; A preset number of packets are replicated according to the packet replication information, and a destination port number corresponding to a destination port receiving each packet is determined; a configuration rule is determined according to the destination port number; and the packet is modified and then sent to the interconnection arbitration module according to the configuration rule, wherein modifying the packet at least comprises modifying a destination address of the multicast packet to a destination address corresponding to the destination port; The interconnection arbitration module transmits the modified packet to a corresponding destination port.

2. The system of claim 1, wherein, The packet processing device comprises a packet distribution module, a packet replication module and a packet modification module; The packet distribution module is used for identifying a packet type when receiving a packet transmitted by the packet receiving port connected with itself; The packet replication module is used for storing the multicast packet in the RAM when the packet type is a multicast packet, and writing the packet replication information into the RAM and latching when writing packet header information in the RAM; The packet replication quantity is determined according to the packet replication information; The packet is replicated according to the packet replication quantity, and a destination port number corresponding to a destination port receiving each packet is determined; a multicast configuration register corresponding to the destination port number is queried according to the destination port number; The packet modification module is used for modifying the packet according to a rule in the multicast configuration register and then transmitting the packet to the interconnection arbitration module.

3. The system of claim 2, wherein, The packet comprises a plurality of data blocks, and the packet replication module is specifically used for: When the packet type is a multicast packet, a first selector and a first register are preconfigured and then hit, to output a write enable signal, a data write valid signal and a write address valid signal; According to the write enable signal, each data block included in the packet is sequentially written into the RAM and stored; According to the data blocks written into the RAM and the write address valid signal, address increment is performed from a packet header until all data blocks corresponding to the packet are written into the RAM, and then a packet end address is recorded; The packet replication information is determined according to a data transmission protocol corresponding to the packet; The packet replication information is written into the RAM and latched.

4. The system of claim 3, wherein, The message copy information is composed of hexadecimal data, and is used to indicate the number of message copies and the destination port numbers corresponding to the target ports receiving each message; wherein the number of message copies is determined according to the number of 1s in the hexadecimal data; and each destination port number is determined according to the position of 1 in the hexadecimal data. The message copy module is specifically configured to: When it is determined that the write enable signal is valid, the state of the RAM write and read state machine is jumped from an idle state to a running state; According to the number of 1s in the hexadecimal data, the number of message cycle readouts is determined to determine the number of message copies; The data block is read from the RAM until the end of the message position is reached, so as to copy one message; The positions of 1s in the hexadecimal data are identified to determine each destination port number; According to the destination port number, a multicast configuration register corresponding to the destination port number is queried, and the destination port receiving each message is determined; When the enable signal of the multicast message is identified each time, the output data signal, the to-be-sent message data valid signal, and the destination port valid signal are output after being tapped through the second selector and the second register, so as to output one message, and the operation is ended after it is confirmed that the number of messages corresponding to the number of message copies is output.

5. The system of claim 3 or 4, wherein, The message copy module is further configured to: After each data block is read, the state value of the back pressure signal is identified; When the state value of the back pressure signal is valid, the next data block is stopped from being read; Until the state value of the back pressure signal is invalid, the next data block is continuously read.

6. The system of claim 5, wherein, The message copy module is further configured to: When the message is sequentially and circularly read according to the number of message copies, the state of the RAM write and read state machine is jumped to an indication state of the end of message reading; And, at the time when the state of the RAM write and read state machine is jumped to the indication state of the end of message reading, after a preset time period, the state value of the back pressure signal is controlled to be invalid.

7. The system according to any of claims 1-4 or 6, characterized in that, The interconnection arbitration module is specifically configured to: According to a routing algorithm, a data transmission path corresponding to each message is matched; According to the data transmission path, the message is transmitted to the destination port.

8. A message transmission method characterized by comprising: The method is applied to the message transmission system as claimed in any one of claims 1-7, the system comprising at least one message processing device and an interconnection arbitration module, each message processing device being connected with a message receiving port in a message transmission device and connected with the interconnection arbitration module; The interconnection arbitration module is further connected with a message sending port in the message transmission device; and the method comprises: The packet processing device identifies a packet type when receiving a packet transmitted by a packet receiving port connected to the packet processing device; when the packet type is a multicast packet, the packet is stored in a RAM, and packet replication information is latched in the RAM; a preset number of packets are replicated according to the packet replication information, and a destination port number corresponding to a destination port receiving each packet is determined; a configuration rule is determined according to the destination port number; and the packet is modified according to the configuration rule and then transmitted to an interconnection arbitration module, wherein modifying the packet at least includes modifying a destination address of the multicast packet to a destination address corresponding to the destination port. The interconnection arbitration module transmits the modified packet to a destination port corresponding to the packet.

9. A computer device, comprising: The packet transmission method comprises the following steps: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the packet transmission method of claim 8.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing a computer to execute the packet transmission method of claim 8.

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