Semiconductor device, cascade amplifier and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor device, a cascade amplifier and a forming method thereof. The semiconductor device includes a substrate having a first conductivity type, a well region formed within the substrate and having a second conductivity type opposite the first conductivity type, and a first transistor formed based on the well region. The first transistor includes a gate contact, a drain contact having a first conductivity type, a source contact having the first conductivity type, and a body contact having a second conductivity type. The semiconductor device also includes an isolation circuit formed over the substrate and coupled between the substrate and a ground voltage through a substrate contact.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device, a cascode amplifier, and a method of forming the same. BACKGROUND

[0002] Millimeter wave frequencies generally refer to signals within a frequency band of about 30 GHz to 300 GHz, which are often used for various applications such as wireless personal area networks ("WPAN"), automotive radar, and image sensing. Various low noise amplifiers (LNAs) for millimeter waves have been disclosed. However, LNAs implemented using compound III-V semiconductors or BJTs are not easily integrated with other components of a receiver, particularly for digital circuits, resulting in higher implementation costs. For example, recent advances in complementary metal-oxide-semiconductor (CMOS) technology enable multi-stage LNAs to be implemented at lower cost for millimeter wave integrated circuits. To achieve sufficient amplification, LNAs are typically implemented by at least two stages, with input, output, and inter-stage matching networks. SUMMARY

[0003] According to an aspect of embodiments of the present application, there is provided a semiconductor device, comprising: a substrate having a first conductivity type; a well region formed within the substrate and having a second conductivity type opposite to the first conductivity type; a first transistor formed based on the well region, wherein the first transistor includes a gate contact, a drain contact having the first conductivity type, a source contact having the first conductivity type, and a body contact having the second conductivity type; and an isolation circuit formed above the substrate and coupled between the substrate and a ground voltage through a substrate contact.

[0004] According to another aspect of embodiments of the present application, there is provided a cascode amplifier, comprising: a first p-type metal-oxide-semiconductor (PMOS) transistor formed above a substrate and including a first gate contact configured to receive an input signal, a first drain contact, a first source contact coupled to a supply voltage, and a first body contact coupled to the first source contact; a second PMOS transistor formed above the substrate and including a second gate contact, a second drain contact coupled to a ground voltage, a second source contact coupled to the first drain contact of the first PMOS transistor, and a second body contact connected to the second source contact; and an isolation circuit configured to couple a first contact of the substrate adjacent to the second PMOS transistor to the ground voltage; wherein the first PMOS transistor and the second PMOS transistor are respectively operable as a common-source stage and a common-gate stage of the cascode amplifier.

[0005] According to yet another aspect of the embodiments of the present application, a method of forming a cascode amplifier is provided, the method comprising: forming a first p-type metal oxide semiconductor (PMOS) transistor above a substrate, the first PMOS transistor operably configured as a first stage of the cascode amplifier. Wherein forming the first PMOS transistor comprises: forming a first gate contact configured to receive an input signal; forming a first drain contact; forming a first source contact configured to be coupled to a supply voltage; and forming a first body contact configured to be coupled to the first source contact. The method further comprises: forming a second PMOS transistor above the substrate, the second PMOS transistor operably configured as a second stage of the cascode amplifier. Wherein forming the second NMOS transistor comprises: forming a second gate contact; forming a second drain contact coupled to a ground voltage; forming a second source contact configured to be coupled to the first drain contact of the first PMOS transistor; and forming a second body contact configured to be coupled to the second source contact. The method further comprises: forming a plurality of metallization layers above the first PMOS transistor and the second PMOS transistor. Wherein forming the plurality of metallization layers comprises: forming an isolation circuit in a respective one of the plurality of metallization layers, wherein the isolation circuit is configured to electrically couple the substrate to the ground voltage. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, according to common practice, the various features are not necessarily drawn to scale, and are merely intended to illustrate the various aspects. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a circuit diagram illustrating an embodiment of a cascode amplifier according to some embodiments.

[0008] Figure 2 is a circuit diagram illustrating another embodiment of a cascode amplifier including a source degeneration circuit according to other embodiments.

[0009] Figures 3-5 is a schematic diagram illustrating various embodiments of an isolation circuit in Figure 1

[0010] Figure 6 is a cross-sectional view of an example transistor of a cascode amplifier in Figure 2

[0011] Figure 7 is a plan view of an example transistor of a cascode amplifier in Figure 6

[0012] ​​​Figure 8 is a cross-sectional view showing two transistors of a cascode amplifier in Figure 1

[0013] Figure 9 is a plan view showing two transistors of a cascode amplifier in Figure 1

[0014] Figure 10 is a flowchart showing an example method of forming a cascode amplifier according to some embodiments.

[0015] Figure 11 is a graph comparing cascode amplifier gain performance according to the present disclosure formed from transistors having an isolation circuit electrically coupling their substrate to ground with cascode amplifier gain performance formed from transistors without such an isolation circuit.

[0016] Figure 12 is a graph comparing cascode amplifier transconductance performance according to the present disclosure formed from transistors having an isolation circuit electrically coupling their substrate to ground with cascode amplifier transconductance performance formed from transistors without such an isolation circuit.

[0017] Figure 13 is a graph comparing cascode amplifier gain and frequency performance according to the present disclosure formed from transistors having an isolation circuit electrically coupling their substrate to ground with cascode amplifier gain and frequency performance formed from transistors without such an isolation circuit.

[0018] Figure 14 is a graph comparing cascode amplifier power added efficiency (PAE) and input power (Pin) performance according to the present disclosure formed from transistors having an isolation circuit electrically coupling their substrate to ground with cascode amplifier PAE and Pin performance formed from transistors without such an isolation circuit.

[0019] Figure 15 is a schematic diagram showing an embodiment of a cascode amplifier using a PMOS substrate and an NMOS substrate according to some embodiments. DETAILED DESCRIPTION

[0020] ​​The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure. For example, in the following description, forming a first component over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the disclosure can refer to a number and / or letter of a reference numeral in various examples. The repetition of the reference numerals is for the sake of simplicity and clarity and does not indicate a relationship between the individual embodiments and / or configurations discussed.

[0021] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] Low noise amplifiers (LNAs) and cascode amplifiers are both important components in radio frequency and microwave circuits, especially in communication systems. They are commonly used at different stages of the signal chain to amplify weak signals while minimizing noise and preserving signal integrity. LNAs are amplifiers specifically designed to amplify weak signals without significantly degrading the signal-to-noise ratio (SNR). LNAs are typically the first stage in a receiver chain, so their performance is critical to the overall system's noise figure. The primary goal of an LNA is to have a low noise figure, which means it introduces minimal additional noise to the signal, which is crucial for maintaining the quality of the received signal. LNAs provide significant amplification, boosting weak signals to a level where they can be processed further without significant degradation. Cascode amplifiers are a two-stage amplifier configuration consisting of a common-emitter (or common-source in FETs) stage and a common-base (or common-gate in FETs) stage, providing high gain, improved bandwidth, and better isolation between input and output. The cascode configuration enhances the overall gain of the amplifier by effectively stacking two transistors, which also helps minimize Miller capacitance (which would otherwise limit bandwidth). Because the configuration reduces the Miller effect, cascode amplifiers have a wider bandwidth, making them suitable for high-frequency applications. The cascode configuration provides better isolation between input and output, improving stability and reducing the risk of oscillation. The cascode configuration can help LNAs achieve higher gain and better isolation without significantly impacting the noise figure. LNAs and cascode amplifiers are often used together in RF designs to leverage the strengths of each amplifier. For example, LNAs are primarily used to amplify weak signals with minimal noise, while the cascode amplifier configuration helps achieve this goal by improving gain and bandwidth characteristics.

[0023] The present disclosure provides various embodiments of a semiconductor device. In some embodiments, the semiconductor device includes a substrate having a first conductivity type; a well region formed within the substrate and having a second conductivity type opposite the first conductivity type; a first transistor formed based on the well region, wherein the first transistor includes a gate contact, a drain contact having the first conductivity type, a source contact having the first conductivity type, and a body contact having the second conductivity type; and an isolation circuit formed above the substrate and coupled between the substrate and a ground voltage by a substrate contact. In some embodiments, the isolation circuit includes a first resistor having a resistance greater than about 10 kOhms. In some embodiments, the semiconductor device includes the first transistor and a second transistor coupled in series to the first transistor, wherein the first transistor is configured to function as a common gate (CG) stage of a cascode amplifier, and the second transistor is configured to function as a common source (CS) stage of the cascode amplifier. In some embodiments, the second transistor includes a source contact and a body contact that are coupled to a supply voltage (e.g., VDD) through a source degeneration circuit, and thus are not directly coupled to the power supply voltage VDD. DD ), thus not directly coupled to the power supply voltage VDD.DD Another isolation circuit is formed on the substrate and configured to couple the substrate to a ground voltage (GND) through a second substrate contact adjacent to the second transistor.

[0024] For a cascode amplifier including two stages, e.g., a common source (CS) stage and a common gate (CG) stage, the output of the CS stage is connected to the input of the CG stage. In one case, in the CG stage, the bulk and the source of the CG stage are not directly connected to a supply voltage (V DD ), there is a substrate-induced loss from a well region (e.g., N-well (NW)) or a substrate (e.g., p-doped substrate) of the CG stage, resulting in gain degradation. In another case, in the CS stage, if the bulk and the source of the CS stage are connected to a supply voltage (V DD ) through a source degeneration circuit (thus not directly connected to the supply voltage V DD ), there is a substrate-induced loss from a well region (e.g., N-well) or a substrate (e.g., p-doped substrate) of the CS stage, resulting in gain degradation. To avoid such gain degradation, it is necessary to minimize the substrate loss from the well region or the substrate. By forming at least one isolation circuit on the substrate and connecting between the substrate and a ground voltage (GND) through a substrate contact adjacent to the CG stage or the CS stage, the substrate-induced loss from the well region or the substrate to the supply voltage V DD can be reduced or even blocked, thereby advantageously reducing the gain degradation of the amplifier. The amplifier can be a low noise amplifier (LNA) or a power amplifier (PA).

[0025] Figure 1 is a circuit diagram illustrating an embodiment of a cascode amplifier 100A according to some embodiments. As shown in Figure 1 , the cascode amplifier 100A includes a cascode gain stage 102A including a common source (CS) stage or a transistor Ml coupled to a common gate (CG) stage or a transistor M2. In some embodiments, the cascode amplifier 100A is formed on a substrate. Each circuit element of the cascode amplifier 100A can be implemented using a p-type metal-oxide-semiconductor (PMOS) technology, an n-type metal-oxide-semiconductor (NMOS) technology, or a complementary metal-oxide-semiconductor (CMOS) technology.

[0026] In some embodiments, as shown in Figure 1 , the source of the CS transistor Ml is directly coupled to a node 110 coupled to a supply voltage (V DD ), the bulk of the CS transistor Ml is coupled to its source, its drain is coupled to the source of the CG transistor M2, and its gate is coupled to an input node 108 to receive an input signal RF IN(e.g., oscillating input signal). In some embodiments, the gate of CS transistor M1 is also connected via resistor R. G1 Coupled to having voltage V G1 The bias voltage source. In some embodiments, node 110 also serves as the output node of the cascaded amplifier 100A, and outputs the signal RF. OUT Output from node 110. In some embodiments, the substrate guard ring 38A of the CS transistor M1 serves as a substrate contact and is coupled to the ground voltage (GND).

[0027] In some embodiments, such as Figure 1 As shown, the source of CG transistor M2 is coupled to the drain of CS transistor M1, the body of CG transistor M2 is coupled to its source, its drain is directly coupled to ground (GND), and its gate is connected via another resistor R. G2 Coupled to having voltage V G2 Another bias voltage source. In some embodiments, the substrate guard ring 38B of the CG transistor M2 serves as a substrate contact and is coupled to ground voltage (GND) via isolation circuit 60. In some embodiments, isolation circuit 60 is formed on the substrate to couple the substrate guard ring 38B to ground voltage (GND). In some embodiments, isolation circuit 60 has a large resistance greater than 1 k ohm.

[0028] Figure 2 This is a circuit diagram illustrating another embodiment of the cascaded amplifier 100B according to other embodiments. In some embodiments, such as Figure 2 As shown, the cascaded amplifier 100B is similar to Figure 1 In the cascade amplifier 100A, except for the CS transistor M1 of the cascade amplifier 100B, a source degradation circuit 50 is included, which connects the source of the CS transistor M1 to a high supply voltage V. DD This ensures that the body and source of the CS transistor M1 are not directly connected to the high supply voltage V. DD Therefore, the substrate guard ring 38A of the CS transistor M1 in the cascaded amplifier 100B is connected to ground voltage (GND) through isolation circuit 60'. (Refer to...) Figure 3 , Figure 4 and Figure 5 Details are described regarding various implementations of the source degradation circuit 50. In some embodiments, isolation circuit 60' is formed on the substrate of cascaded amplifier 100B, which is configured to couple the substrate to ground voltage (GND) via a substrate guard ring 38A, which serves as a substrate contact adjacent to the CS transistor M1. In some embodiments, similar to... Figure 1 The cascaded amplifier 100A shown is, for example Figure 2As shown, isolation circuit 60 is formed on the substrate of cascode amplifier 100B to couple the substrate to a ground voltage through substrate guard ring 38B, which serves as another substrate contact adjacent to CG transistor M2. Each circuit element of cascode amplifier 100B can be implemented using p-type metal-oxide-semiconductor (PMOS) technology, n-type metal-oxide-semiconductor (NMOS) technology, or complementary metal-oxide-semiconductor (CMOS) technology.

[0029] Figure 3 、 Figure 4 and Figure 5 are schematic diagrams illustrating various embodiments of source degeneration circuit 50 in Figure 1 . According to some embodiments. Figure 2 Source degeneration circuit 50 in Figure 3 , in some embodiments, source degeneration circuit 50 in Figure 2 is implemented as a resistor 50A having a large resistance. In some embodiments, the resistance of resistor 50A is equal to or greater than 3 kOhms. In other embodiments, the resistance of resistor 50A is equal to or greater than 10 kOhms. Referring to Figure 4 , in other embodiments, source degeneration circuit 50 in Figure 2 is implemented as a quarter- wavelength transmission line 50B. A quarter- wavelength transmission line 50B is a portion of a transmission line that is exactly one quarter (λ / 4) of the wavelength of the signal frequency. Quarter- wavelength transmission lines 50B can be used in various applications in RF and microwave engineering, such as impedance matching, filters, and antennas. The wavelength (λ) is determined by the signal frequency and the speed of propagation of the wave in the medium, which is affected by the dielectric material of the transmission line. Referring to Figure 5 , in further embodiments, source degeneration circuit 50 in Figure 2 is implemented as an LC resonant circuit 50C, which includes an inductor 52 and a capacitor 54 disposed in parallel with each other and connected in a loop. LC resonant circuit 50C exhibits resonant behavior and can store and exchange energy between inductor 52 and capacitor 54 to oscillate at a particular frequency, called the resonant frequency.

[0030] Figure 6 is a cross-sectional view of an example transistor 600 (M1 or M2) of a cascode amplifier (e.g., 100A or 100B) according to some embodiments. Figure 7 is a plan view 700 of an example transistor 600 in Figure 6 according to some embodiments. In some embodiments, transistor 600 in Figure 6 can be implemented as CG transistor M2 of cascode amplifier 100A in Figure 1 or CG transistor M2 of cascode amplifier 100B in Figure 2In the cascaded amplifier 100B, the CG transistor M2 has a source (S) that is not directly coupled to the supply voltage V. DD In other embodiments, Figure 6 The transistor 600 in the middle can be implemented as Figure 2 In the cascaded amplifier 100B, the CS transistor M1 has a source that is not directly coupled to the supply voltage V. DD Instead, it is coupled to the supply voltage V through the source degradation circuit 50. DD .like Figure 6 and Figure 7 As shown, in order to perform high isolation while maintaining the ground potential of the semiconductor substrate 10 of transistor 600, transistor 600 includes an isolation circuit 60 that couples the semiconductor substrate 10 of transistor 600 to ground voltage (GND) via substrate contacts 38. In some embodiments, the isolation circuit 60 has a resistor with a large resistance greater than about 1 k ohm, which effectively reduces substrate-induced losses.

[0031] In some embodiments, the substrate contact 38 may be implemented as a substrate guard ring. A substrate guard ring is a structure used in semiconductor devices to prevent unwanted electrical noise or interference from affecting circuit performance. The substrate guard ring may be a ring-shaped region or other suitablely shaped region surrounding a specific area of ​​an integrated circuit (IC) or a specific component within the IC. The substrate guard ring may be made of a conductive material, such as heavily doped silicon or a metal (e.g., copper, aluminum, or tungsten). The substrate guard ring helps isolate sensitive parts of the circuit from electrical noise or interference that may be present in the substrate or nearby circuitry. The substrate guard ring also helps provide a safe path for releasing any accumulated static electricity, protecting sensitive components within the substrate guard ring from damage.

[0032] In some embodiments, such as Figure 6 and Figure 7 As shown, transistor 600 (e.g., Figure 1 In the cascaded amplifier 100A, the CG transistor M2 is formed on a semiconductor substrate 10 (e.g., a p-sub or p-sub), which may be doped with a first conductivity type material, such as a p-type material. As will be understood by those skilled in the art, the semiconductor substrate 10 may be formed of various materials, including but not limited to bulk silicon, silicon-phosphorus (SiP), silicon-germanium (SiGe), silicon carbide (SiC), germanium (Ge), silicon-on-insulator (SOISi), silicon-on-insulator (SOIGe), or combinations thereof.

[0033] In some embodiments, such as Figure 6 and Figure 7As shown, a well region or well 12 of a second conductive material (e.g., an n-type material) is formed in the substrate 10. In some embodiments, the well 12 (e.g., an n-well) is formed by doping the semiconductor substrate 10 with a suitable n-type material (such as arsenic, phosphorus, antimony, or other Group V elements), as will be understood by those skilled in the art.

[0034] In some embodiments, such as Figure 6 and Figure 7 As shown, the source and drain contacts of transistor 600 are formed by a P+ region 18 perpendicular to the upper surface of the n-type well region 12. The P+ region 18 is doped with a suitable p-type dopant at a higher concentration than the n-type dopant concentration in the n-type well region 12. The gate G of transistor 600 is formed by depositing a gate oxide 20 on a channel 16, forming a gate dielectric 22 on the gate oxide 20, and forming a gate electrode 24 on the gate dielectric 22. The channel 16 is disposed between the n-type well region 12 and the P+ region 18. Sidewalls 26 may be disposed on the sides of the gate dielectric 22 and the gate electrode 24.

[0035] In some embodiments, such as Figure 6 As shown, a shallow trench isolation (STI) region 28 is laterally adjacent to a P+ region 18 on the upper surface of the n-well 12. The STI region 28 laterally separates the P+ region 18 from the N+ region 30. An STI region 36 is formed on the upper surface of the substrate 10. The STI region 36 separates the N+ region 30 from the adjacent P+ region 38. The P+ region 38 is laterally separated from the STI region 36 on the upper surface of the substrate 10. In some embodiments, the P+ region 18 serves as a source contact of the transistor 600, another P+ region 18 serves as a drain contact in the transistor 600, and the N+ region 30 serves as a body contact of the transistor 600.

[0036] In some embodiments, the p-substrate 10 and the n-well 12 each have their own resistance R. PSUB and R NW Diode 40 is operatively formed at the interface between substrate 10 and n-well 12. A pair of diodes 44 (D SB and D DB The cathodes of the pair of diodes 44 are operably formed at the interface between the n-well 12 and the P+ region 18. The cathodes of the pair of diodes 44 are respectively connected to the resistor R at node 46. SB and resistance R DB Connected to the cathode of diode 40, node 46 is connected to the resistor R of the N-well. NW Connected to N+ region 30. In some embodiments, the anode of diode 40 is connected through the substrate resistance R. PSUBCoupled to P+ region 38. P+ region 38 can form a substrate guard ring and can be used as a substrate contact. In some embodiments, P+ region 38 is coupled to ground voltage (GND) via isolation circuit 60. To achieve high isolation between substrate 10 and ground voltage (GND), isolation circuit 60 is formed with a large resistance R. ISO This is to couple the p-doped substrate contact 38 (p+ region 38) to ground voltage. In some embodiments, the resistance of the isolation circuit 60 is greater than about 10 k ohms. In other embodiments, the resistance of the isolation circuit 60 is greater than about 20 k ohms. Therefore, the isolation circuit 60 of the transistor 600 with such a large resistance can minimize losses caused by the substrate or well region, thereby effectively improving the gain of using such a transistor 600 as at least one stage of a cascaded amplifier.

[0037] In some embodiments, such as Figure 6 As shown, a transistor 600 having a substrate 10 coupled to a ground voltage via an isolation circuit 60 can, as Figure 1 and Figure 2 The CG transistor M2 in the PMOS cascaded amplifier 100A or 100B shown is implemented to reduce or prevent transmission via junction diode 40D. PSUB The substrate-induced loss or well-region-induced loss occurs because the source of transistor 600 is not directly connected to the supply voltage V. DD In other embodiments, such as Figure 6 As shown, the substrate 10 of transistor 600 is coupled to ground voltage through isolation circuit 60, which can be implemented as follows: Figure 2 The PMOS cascaded amplifier 100B shown uses a CS transistor M1, provided that the source contact and body contact of the CS transistor M1 are indirectly coupled to the supply voltage V through the source degradation circuit 50. DD To reduce or prevent transmission via junction diode 40D PSUB Substrate-induced loss or well region-induced loss.

[0038] like Figure 1 , Figure 2 , Figure 6 and Figure 7As shown, in some embodiments, transistor 600 includes a substrate 10 having a first conductivity type (e.g., a p-doped substrate); a well region 12 formed within the substrate 10 and having a second conductivity type opposite to the first conductivity type (e.g., an n-well); and a first transistor (e.g., M2) formed based on the well region 12. In some embodiments, the first transistor (e.g., M2) includes a gate contact 24, a drain contact 18 having a first conductivity type, a source contact 18 having a first conductivity type, and a body contact 30 having a second conductivity type. The source contact 18 and the body contact 30 of transistor 600 are electrically connected to each other. Neither the source contact 18 nor the body contact 30 of transistor 600 is directly connected to a supply voltage ( Figure 1 V in DD In this case, transistor 600 includes isolation circuit 60 formed on substrate 10 and coupled between substrate contact A of substrate guard ring 38 of substrate 10 and ground voltage (GND). In some embodiments, isolation circuit 60 includes a resistor with a resistance greater than about 10 kΩ. In some embodiments, substrate guard ring 38 has a first conductivity type. In some embodiments, the first conductivity type is p-type, while in other embodiments, the first conductivity type is n-type.

[0039] In some embodiments, such as Figure 6 As shown, a junction diode 40 is operatively formed between the well region 12 and the substrate 10. Since an isolation circuit 60 is coupled between the substrate 10 and ground voltage (GND), the junction diode 40 is configured to block charge from the well region 12 toward the substrate 10. In some embodiments, the transistor 600 is configured as a CG transistor M2 in a cascaded amplifier, wherein the source of the transistor 600 is not directly connected to the supply voltage (V). DD In other embodiments, the source of transistor 600 is via, as... Figure 2 The source degradation circuit 50 shown is indirectly connected to the supply voltage (V). DD In the case of ), transistor 600 is configured to function as CS transistor M1 in a cascaded amplifier. In some embodiments, source degradation device 50 includes Figure 3 The resistor in the middle is 50A. Figure 4 50B quarter-wavelength transmission line or Figure 5 At least one of the LC resonant circuits 50C in the circuit.

[0040] Figure 8 This illustrates some embodiments. Figure 1 Cross-sectional view 800 of the two transistors M1 and M2 in the cascaded amplifier 100A. Figure 9 This illustrates a cascaded amplifier 100A according to some embodiments. Figure 1Plan view 900 shows two transistors M1 and M2. As shown, the two transistors M1 and M2 are formed in the first and second regions of the substrate, respectively. (See reference...) Figure 6 The structure of two transistors, M1 and M2, in a cascaded amplifier 100A is described. (Refer to...) Figure 1 , Figure 6 , Figure 8 and Figure 9 The CG transistor M2 includes an isolation circuit 60 with a sufficiently large resistance, coupled between the substrate contact A of the substrate guard ring 38B and the ground voltage (GND). Figure 7 (as shown), to reduce or prevent transmission via junction diode 40D PSUB Substrate-induced loss or well region-induced loss.

[0041] like Figure 1 , Figure 8 and Figure 9 As shown, the cascade amplifier 100A includes a CS transistor M1 coupled to the CG transistor M2. In some embodiments, the cascade amplifier 100A is formed on a substrate 10. Each circuit element of the cascade amplifier 100A can be implemented using p-type metal-oxide-semiconductor (PMOS), n-type metal-oxide-semiconductor (NMOS), or complementary metal-oxide-semiconductor (CMOS) technology. In some embodiments, the source of the CS transistor M1 is coupled to its body (B) via a metal line 82, its drain is coupled to the source of the CG transistor M2, and its gate is coupled to the input node 108 to receive... Figure 1 The input signal (such as the oscillation input signal) RF IN In some embodiments, the gate of the CS transistor M1 is also via... Figure 1 The resistor R in G1 Coupled to having voltage V G1 The bias voltage source. In some embodiments, node 110 also serves as the output node of the cascaded amplifier 100A, such as... Figure 1 As shown, the output signal RF OUT Output from this output node. In some embodiments, such as Figure 1 , Figure 8 and Figure 9 As shown, the substrate guard ring 38A of the CS transistor M1 is coupled to the ground voltage (GND) at position A.

[0042] In some embodiments, such as Figure 1 , Figure 8 and Figure 9 As shown, the source of CG transistor M2 is coupled to the drain of CS transistor M1 via metal line 84, its bulk is coupled to its source via metal line 86, its drain is directly coupled to the GND voltage, and its gate is connected to another resistor R.G2 a second bias voltage source having a voltage V G2 In some embodiments, the substrate guard ring 38B of the CG transistor M2 is coupled to a ground voltage (GND) through an isolation circuit 60. In some embodiments, the isolation circuit 60 is formed on the substrate 10 and coupled between the substrate 10 and the ground voltage (GND) through the substrate guard ring 38B as a substrate contact adjacent to the CG transistor M2.

[0043] Figure 10 is a flowchart illustrating an example method 1000 of forming a cascode amplifier (e.g., 100A as shown in Figure 1 , Figure 8 and Figure 9 . It should be understood that for this and other embodiments, additional operations can be provided before, during, and after the processes discussed in Figure 10 , and that some operations described below can be replaced or eliminated. The order of the operations / processes can be interchanged, and at least some operations or processes can be performed concurrently or at different times. In some embodiments, at least two or more operations or processes overlap in time or are performed nearly simultaneously.

[0044] In some embodiments, the operations of the method 1000 can be used to form a cascode amplifier 100A including forming a first p-type metal oxide semiconductor (PMOS) transistor Ml on a first region of a substrate 10 and operably configured as a common source (CS) stage, forming a second PMOS transistor M2 on a second region of the substrate 10 and configured as a common gate (CG) stage, and connecting a substrate contact 38B of the substrate 10 to a ground voltage (GND) through an isolation circuit 60, where the substrate 10 is adjacent to the second PMOS transistor M2, as shown in Figure 1 , Figure 8 and Figure 9 .

[0045] As shown in Figure 1 , Figure 8 , Figure 9 and Figure 10 , in some embodiments, the operation 1002 includes forming a first p-type metal oxide semiconductor (PMOS) transistor Ml on a first region of a substrate 10 and operably configured as a first stage of a cascode amplifier 100A. In some embodiments, the first stage of the cascode amplifier 100A is the CS transistor Ml. In some embodiments, the semiconductor substrate 10 can be formed of a variety of materials including, but not limited to, bulk silicon, silicon on phosphorous (SiP), silicon germanium (SiGe), silicon carbide (SiC), germanium (Ge), silicon on insulator-silicon (SOI Si), silicon on insulator-germanium (SOI Ge), or combinations thereof.

[0046] In some embodiments, as shown in Figure 1 , Figure 6 , Figure 8 , Figure 9 and Figure 10 , the operation 1002 of forming the first PMOS transistor Ml is performed in front end of line (FEOL) and includes, for example, forming a first gate contact or electrode 24 configured to receive an input signal; forming a first drain contact 18; forming a first source contact 18 configured to be coupled to a supply voltage V DD DD; and forming a first body contact 30 configured to be coupled to the first source contact 18. Various photolithography, etching, and deposition methods can be used to form these elements of the first PMOS transistor Ml.

[0047] Next, as shown in Figure 1 , Figure 8 , Figure 9 and Figure 10 , in some embodiments, the operation 1004 includes forming a second PMOS transistor M2 configured as a second stage of the cascode amplifier 100A on a second region of the substrate 10. In some embodiments, the second stage of the cascode amplifier 100A is a CG transistor M2. The operation 1004 can be performed before, after, or concurrently with the operation 1002.

[0048] In some embodiments, as shown in Figure 1 , Figure 6 , Figure 8 , Figure 9 and Figure 10 , the operation 1004 of forming the second PMOS transistor M2 is performed in FEOL and includes, for example, forming a second gate contact 24; forming a second drain contact 18 coupled to a ground voltage; forming a second source contact 18 configured to be coupled to the first drain contact 18 of the first PMOS transistor Ml; and forming a second body contact 30 configured to be coupled to the second source contact 18. Various photolithography, etching, and deposition methods can be used to form these elements of the second PMOS transistor M2.

[0049] Next, as shown in Figure 1 , Figure 8 , Figure 9 and Figure 10As shown, in some embodiments, operation 1006 includes forming an isolation circuit 60 in a respective metallization layer of a plurality of metallization layers (not shown) in the back-end process (BEOL). In some embodiments, the isolation circuit 60 is configured to electrically couple the substrate 10 to ground voltage (GND) via a substrate contact or substrate guard ring 38B adjacent to the second PMOS transistor M2. In some embodiments, the isolation circuit 60 includes a resistor with a large resistance greater than about 10 kΩ, while in other embodiments the large resistance is greater than about 20 kΩ.

[0050] In some embodiments, references to, for example Figure 1 and Figure 8 In BEOL, the source of CS transistor M1 is coupled to CS transistor M2 via metal line 82, the drain of CS transistor M1 is coupled to the source of CG transistor M2 via metal line 84, and the gate of CS transistor M1 is coupled to input node 108 to receive input signals (e.g., oscillation input signals). IN In some embodiments, the gate of CS transistor M1 is also connected via resistor R. G1 Coupled to having voltage V G1 The bias voltage source, such as Figure 1 As shown. In some embodiments, node 110 also serves as the output node of the cascaded amplifier 100A, such as Figure 1 As shown, the output signal RF OUT Output from this output node. In some embodiments, such as Figure 1 , Figure 8 and Figure 9 As shown, the source of CS transistor M1 is directly coupled to the supply voltage (V). DD In the case of ), the substrate contact or guard ring 38A in CS transistor M1 is directly coupled to the ground voltage (GND).

[0051] In some embodiments, references to, for example Figure 1 and Figure 8 In BEOL, the source of CG transistor M2 is coupled to the drain of CS transistor M1 via metal line 84, the body of CG transistor M2 is coupled to the source of CG transistor M2 via metal line 86, the drain of CG transistor M2 is directly coupled to the GND voltage, and the gate of CG transistor M2 is connected to another resistor R. G2 Coupled to having voltage V G2Another bias voltage source. In some embodiments, the substrate guard ring 38B of the CG transistor M2 is coupled to the ground voltage (GND) via an isolation circuit 60. In some embodiments, in BEOL, the isolation circuit 60, having a large resistance (e.g., greater than 1k ohms), is formed on the substrate 10 and coupled between the substrate 10 and the ground voltage (GND) via the substrate guard ring 38B as a substrate contact adjacent to the CG transistor M2.

[0052] In other embodiments, such as Figure 2 As shown, if the source degradation circuit 50 is formed in one of the metallization layers (e.g., M0, M1, M2, M3, M4, M5... not shown) (e.g., M3) and configured to electrically couple the first source contact of the CS transistor M1 to the supply voltage (V) DD Another isolation circuit 60' can be formed in a metallization layer and configured to electrically couple the substrate 10 to ground voltage (GND). Therefore, by utilizing isolation circuit 60 or isolation circuit 60' in the manner described above, substrate-induced losses can be effectively reduced or even prevented, thereby advantageously improving the gain performance of amplifiers (such as low-noise amplifiers (LNAs) or power amplifiers (PAs)).

[0053] Figure 11 This is a graph showing the relationship between maximum available gain (Gmax) and frequency, comparing the Gmax (track 1102) of a conventional LNA excluding high-isolation circuitry that electrically couples its substrate to ground with the Gmax (track 1104) of an LNA according to this disclosure that includes high-isolation circuitry that electrically couples its substrate to ground. Figure 11 As shown, the trajectory 1104 implemented by the LNA according to this disclosure is superior to the trajectory 1102 implemented by the conventional LNA.

[0054] Figure 12 This is a graph showing the relationship between maximum available transconductance (Gm) and frequency, comparing the Gm (track 1202) of a conventional LNA excluding a high-isolation circuit that electrically couples its substrate to ground with the Gm (track 1204) of an LNA according to this disclosure that includes a high-isolation circuit that electrically couples its substrate to ground. Figure 12 As shown, the trajectory 1204 implemented by the LNA according to this disclosure is superior to the trajectory 1202 implemented by the conventional LNA.

[0055] Figure 13 This is a gain versus frequency diagram comparing the gain of a conventional LNA (track 1302) excluding a high-isolation circuit that electrically couples its substrate to ground with the gain of an LNA according to this disclosure (track 1304). Figure 13 As shown, the trajectory 1304 implemented by the LNA according to this disclosure is superior to the trajectory 1302 implemented by the conventional LNA.

[0056] Figure 14 This is a graph showing the relationship between power-added efficiency (PAE) and input power (Pin), comparing the PAE of a conventional LNA (trace 1402) excluding a high-isolation circuit that electrically couples its substrate to ground with the PAE of an LNA according to this disclosure (trace 1404) including a high-isolation circuit that electrically couples its substrate to ground. Figure 14 As shown, the trajectory 1404 implemented by the LNA according to this disclosure is superior to the trajectory 1402 implemented by the conventional LNA.

[0057] Figure 15 This is a schematic diagram illustrating one embodiment of a complementary metal-oxide-semiconductor (CMOS) cascade amplifier 1500 according to some embodiments, wherein PMOS and NMOS substrates are used. Figure 15 As shown, the CMOS cascaded amplifier 1500 includes a first transistor M1 and a second transistor M2 implemented in a floating deep n-well (“DNW”), and also includes a third transistor M3 and a fourth transistor M4 implemented on a PMOS substrate. Figure 15 As shown, for example, it is used as a CG transistor and is not directly coupled to the supply voltage (V). DD The PMOS transistor M3 includes an isolation circuit 60 that couples the P-doped substrate (P-sub) to ground voltage (GND). In some embodiments, the isolation circuit 60 has a large resistance greater than 1 k ohm. In some embodiments, the CMOS cascade amplifier 1500 can be applied as a scaling cascade amplifier.

[0058] In one aspect of this disclosure, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first conductivity type; a well region formed within the substrate and having a second conductivity type opposite to the first conductivity type; a first transistor formed based on the well region, wherein the first transistor includes a gate contact, a drain contact having the first conductivity type, a source contact having the first conductivity type, and a body contact having the second conductivity type; and an isolation circuit formed above the substrate and coupled between the substrate and a ground voltage via substrate contacts.

[0059] In some embodiments, the isolation circuit includes a first resistor having a resistance greater than about 10 k ohms.

[0060] In some embodiments, the semiconductor device further includes a junction diode operably formed between the well region and the substrate; wherein an isolation circuit is coupled between the substrate and a ground voltage, and the junction diode is configured to block charge from the well region toward the substrate.

[0061] In some embodiments, the substrate contact has a first conductivity type.

[0062] In some embodiments, the source contact and the body contact are electrically connected to each other, and neither the source contact nor the body contact is directly connected to the supply voltage.

[0063] In some embodiments, the first transistor is configured to serve as a common-gate (CG) stage of a cascaded amplifier, and wherein the cascaded amplifier includes a second transistor configured to serve as a common-source (CS) stage.

[0064] In some embodiments, the second transistor includes a gate contact configured to receive an oscillating input signal.

[0065] In some embodiments, the second transistor includes a source contact and a body contact that are coupled to the supply voltage via a source degradation circuit.

[0066] In some embodiments, the source degradation device includes at least one of a second resistor, an LC resonant circuit, or a quarter-wavelength transmission line.

[0067] In some embodiments, the source contact and body contact of the second transistor are directly connected to the supply voltage.

[0068] In some embodiments, the drain contact of the first transistor is coupled to a ground voltage, and the gate contact of the first transistor is coupled to a bias voltage.

[0069] In another aspect of this disclosure, a cascaded amplifier is disclosed. The cascaded amplifier includes: a first p-type metal-oxide-semiconductor (PMOS) transistor formed over a substrate and including a first gate contact configured to receive an input signal, a first drain contact, a first source contact coupled to a supply voltage, and a first body contact coupled to the first source contact; a second PMOS transistor formed over the substrate and including a second gate contact, a second drain contact coupled to a ground voltage, a second source contact coupled to the first drain contact of the first PMOS transistor, and a second body contact connected to the second source contact; and an isolation circuit configured to couple the first contact of the substrate adjacent to the second PMOS transistor to the ground voltage. The first PMOS transistor and the second PMOS transistor are operably used as a common-source stage and a common-gate stage of the cascaded amplifier, respectively.

[0070] In some embodiments, the first source contact is coupled to the supply voltage via a source degradation circuit, and wherein a second contact adjacent to the substrate of the first PMOS transistor is connected to the ground voltage via another isolation circuit.

[0071] In some embodiments, the source degradation circuit includes at least one of a resistor, an LC resonant circuit, or a quarter-wavelength transmission line.

[0072] In some embodiments, the first PMOS transistor is formed within a first n-well region, the first n-well region formed within a p-doped substrate.

[0073] In some embodiments, the second PMOS transistor is formed within a second n-well region, the second n-well region formed within the p-doped substrate.

[0074] In another aspect of the disclosure, a method of forming a cascode amplifier is disclosed. The method includes forming a first p-type metal-oxide-semiconductor (PMOS) transistor above a substrate, the first PMOS transistor operably configured as a first stage of the cascode amplifier; forming a second PMOS transistor above the substrate, the second PMOS transistor operably configured as a second stage of the cascode amplifier; and forming a plurality of metallization layers above the first PMOS transistor and the second PMOS transistor. Forming the first PMOS transistor includes forming a first gate contact configured to receive an input signal; forming a first drain contact; forming a first source contact configured to be coupled to a supply voltage; and forming a first body contact configured to be coupled to the first source contact. Forming the second PMOS transistor includes forming a second gate contact; forming a second drain contact coupled to a ground voltage; forming a second source contact configured to be coupled to the first drain contact of the first PMOS transistor; and forming a second body contact configured to be coupled to the second source contact. Forming the plurality of metallization layers includes forming an isolation circuit in a respective one of the plurality of metallization layers, wherein the isolation circuit is configured to electrically couple the substrate to the ground voltage.

[0075] In some embodiments, the isolation circuit includes a resistor having a resistance greater than about 10 kOhms.

[0076] In some embodiments, forming the plurality of metallization layers further includes forming a source degeneration circuit in a respective one of the metallization layers, wherein the source degeneration circuit is configured to electrically couple the first source contact to the supply voltage; and forming another isolation circuit in a respective one of the metallization layers, wherein the other isolation circuit is configured to electrically couple the substrate to the ground voltage.

[0077] In some embodiments, the other isolation circuit includes another resistor having a resistance greater than about 10 kOhms.

[0078] As used herein, the terms“about” and“approximately” generally mean values that can vary depending on the particular technical node associated with the subject semiconductor device. Based on the particular technical node, the term“about” can mean a value of a given quantity that varies, for example, within a range of 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0079] The foregoing summarizes features of several embodiments in order that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they can easily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure and that they can make various changes, substitutions and alterations within the scope of the disclosure without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device comprising: a substrate having a first conductivity type; a well region formed within the substrate and having a second conductivity type opposite the first conductivity type; a first transistor formed based on the well region, wherein the first transistor includes a gate contact, a drain contact having the first conductivity type, a source contact having the first conductivity type, and a body contact having the second conductivity type; and an isolation circuit formed over the substrate and coupled between the substrate and a ground voltage by a substrate contact. The isolation circuit includes a first resistor having a resistance greater than 10 kOhms.

2. The semiconductor device of claim 1, wherein, 3. The semiconductor device of claim 1, further comprising: a junction diode operably formed between the well region and the substrate; wherein the isolation circuit is coupled between the substrate and the ground voltage, and the junction diode is configured to block charge from the well region toward the substrate. The source contact and the body contact are electrically connected to each other, and neither the source contact nor the body contact is directly connected to a supply voltage.

4. The semiconductor device of claim 1, wherein, The first transistor is configured to function as a common-gate stage of a cascode amplifier, and wherein the cascode amplifier includes a second transistor configured to function as a common-source stage.

5. The semiconductor device of claim 1, wherein, The second transistor includes a gate contact configured to receive an oscillating input signal.

6. The semiconductor device of claim 5, wherein, The second transistor includes a source contact and a body contact commonly coupled to a supply voltage via a source degeneration circuit.

7. The semiconductor device of claim 5, wherein, The drain contact of the first transistor is coupled to the ground voltage, and the gate contact of the first transistor is coupled to a bias voltage.

8. The semiconductor device of claim 1, wherein, 9. A cascode amplifier comprising: a first PMOS transistor formed over a substrate and including a first gate contact configured to receive an input signal, a first drain contact, a first source contact coupled to a supply voltage, and a first body contact coupled to the first source contact; a second PMOS transistor formed over the substrate and including a second gate contact, a second drain contact coupled to a ground voltage, a second source contact coupled to the first drain contact of the first PMOS transistor, and a second body contact connected to the second source contact; and an isolation circuit configured to couple a first contact of the substrate adjacent to the second PMOS transistor to the ground voltage; wherein the first PMOS transistor and the second PMOS transistor are respectively operable as a common-source stage and a common-gate stage of a cascode amplifier.

10. A method of forming a cascode amplifier comprising: forming a first PMOS transistor over a substrate, the first PMOS transistor operable configured as a first stage of the cascode amplifier, wherein forming the first PMOS transistor includes: forming a first gate contact configured to receive an input signal; forming a first drain contact; forming a first source contact configured to be coupled to a supply voltage; and forming a first body contact configured to be coupled to the first source contact; ​ forming a second PMOS transistor above the substrate, the second PMOS transistor operably configured as a second stage of the cascode amplifier, wherein forming the second NMOS transistor comprises: forming a second gate contact; forming a second drain contact coupled to a ground voltage; forming a second source contact configured to be coupled to the first drain contact of the first PMOS transistor; and forming a second body contact configured to be coupled to the second source contact; and forming a plurality of metallization layers above the first PMOS transistor and the second PMOS transistor, wherein forming the plurality of metallization layers comprises: forming an isolation circuit in a respective one of the plurality of metallization layers, wherein the isolation circuit is configured to electrically couple the substrate to the ground voltage.

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