Data storage device and method and electronic equipment

Abstract

The invention relates to a data storage device and method and electronic equipment, the device comprises a controller, a first FIFO module and a second FIFO module, the controller is used for determining a first data volume stored by the first FIFO module and a second data volume stored by the second FIFO module; according to the first data volume and the second data volume, a received data block is selected to be written into the first FIFO module or the second FIFO module, and / or data migration between the first FIFO module and the second FIFO module is managed; and the second FIFO module is used for sequentially outputting the data blocks according to the write-in sequence. According to the embodiment of the invention, the advantages of the first FIFO module 2 and the second FIFO module 3 can be considered at the same time, so that the requirements of high performance, low power consumption and high resource utilization rate of the FIFO memory in the fields of high-speed data communication, real-time signal processing, high-performance calculation and the like are met.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of integrated circuit design, and in particular, to a data storage device, method and electronic device. BACKGROUND

[0002] A FIFO (First Input First Output) memory is a first-in first-out dual-port buffer, which is widely used in integrated circuit chips as a circuit structure, and can be used for buffering data, clock domain isolation, controlling the order of data access, and realizing accurate matching between different transmission rate systems.

[0003] In the related art, the design of a FIFO memory often simply uses a register array as storage or simply uses a random access memory (RAM) as storage. However, for a FIFO memory that simply uses a register array as storage, the power consumption is high, especially when the storage capacity requirement is high, and the continuous work of a large number of registers will consume a large amount of power. For a FIFO memory that simply uses a RAM as storage, due to the complexity of the read-write mechanism of the RAM, there is a long waiting time from issuing a read-write request to completing the actual read-write operation of the data. This will seriously affect the overall performance of the system in application scenarios with high requirements for data transmission real-time performance, such as high-speed data communication, real-time signal processing, and the like.

[0004] With the development of digital integrated circuits, in high-performance integrated circuits, it is required that a FIFO memory meet the requirements of fast access speed and low energy consumption at the same time. At this time, a FIFO memory that simply uses a RAM as storage or a FIFO memory that simply uses a register array as storage cannot meet the performance requirements. SUMMARY

[0005] The present disclosure provides a data storage device, method and electronic device.

[0006] According to an aspect of the present disclosure, a data storage device is provided, comprising: a controller, a first FIFO module, a second FIFO module, the second FIFO module having a faster speed than the first FIFO module, the controller, the first FIFO module and the second FIFO module being connected with each other; the controller being configured to determine a first data amount stored in the first FIFO module and a second data amount stored in the second FIFO module, select a first FIFO module or a second FIFO module to write a received data block according to the first data amount and the second data amount, and / or manage data migration between the first FIFO module and the second FIFO module; and the second FIFO module being configured to sequentially output data blocks in a writing order.

[0007] In a possible implementation manner, the controller is configured to, in response to receiving a write operation on the data storage device, perform at least one of the following steps: in a case where the first data amount is empty and the second data amount is less than a capacity of the second FIFO module, writing the received data block into the second FIFO module; in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, writing the received data block into the first FIFO module; and in a case where the second data amount is equal to the capacity of the second FIFO module, writing the received data block into the first FIFO module.

[0008] In a possible implementation manner, the controller is configured to, in response to receiving a read operation on the data storage device, control the second FIFO module to preferentially perform a read operation to output a data block, so that the second data amount stored in the second FIFO module is less than the capacity of the second FIFO module.

[0009] In a possible implementation manner, in a case where the first data amount is not empty, a read operation on the first FIFO module is triggered to output a data block from the first FIFO module to the second FIFO module.

[0010] In a possible implementation manner, an instruction delay time of the second FIFO module performing a read operation is one cycle, and an instruction delay time of the first FIFO module performing a read operation is two cycles.

[0011] In a possible implementation manner, the controller is configured to, in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, control the first FIFO module to migrate a data block to the second FIFO module.

[0012] In a possible implementation manner, the first FIFO module uses a RAM as storage, and the second FIFO module uses a register array as storage.

[0013] In a possible implementation manner, the first FIFO module includes a first single-port RAM unit and a second single-port RAM unit, the first single-port RAM unit and the second single-port RAM unit are physically isolated, and the controller is configured to write the received data blocks into the first single-port RAM unit and the second single-port RAM unit alternately, so that, when the controller writes the received data blocks into the first single-port RAM unit, the data blocks are read from the second single-port RAM unit synchronously, or, when the controller writes the received data blocks into the second single-port RAM unit, the data blocks are read from the first single-port RAM unit synchronously.

[0014] In a possible implementation manner, the first FIFO module includes a crossbar, and the crossbar is configured to select, according to an indication of the controller, in a case where the first data amount is empty and the second data amount is less than a capacity of the second FIFO module, transmitting the data blocks to the second FIFO module in a transparent manner, and / or in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, reading the written data blocks from the first single-port RAM unit or the second single-port RAM unit to the second FIFO module.

[0015] In a possible implementation manner, a first write data output terminal of the controller is connected with a write data input terminal of the first single-port RAM unit, a first write enable output terminal of the controller is connected with a write enable input terminal of the first single-port RAM unit, a first write address output terminal of the controller is connected with a write address input terminal of the first single-port RAM unit, a first read enable output terminal of the controller is connected with a read enable input terminal of the first single-port RAM unit, and a first read address output terminal of the controller is connected with a read address input terminal of the first single-port RAM unit; a second write data output terminal of the controller is connected with a write data input terminal of the second single-port RAM unit, a second write enable output terminal of the controller is connected with a write enable input terminal of the second single-port RAM unit, a second write address output terminal of the controller is connected with a write address input terminal of the second single-port RAM unit, a second read enable output terminal of the controller is connected with a read enable input terminal of the second single-port RAM unit, and a second read address output terminal of the controller is connected with a read address input terminal of the second single-port RAM unit; a data pass-through terminal of the controller is connected with a first input terminal of the crossbar switch, an output terminal of the first single-port RAM unit is connected with a second input terminal of the crossbar switch, an output terminal of the second single-port RAM unit is connected with a third input terminal of the crossbar switch, a selection signal output terminal of the controller is connected with a control terminal of the crossbar switch, and an output terminal of the crossbar switch is connected with a data input terminal of the second FIFO module.

[0016] In a possible implementation manner, the controller comprises a counter, and the controller determines a first data amount stored in the first FIFO module and a second data amount stored in the second FIFO module by using the counter.

[0017] In a possible implementation manner, the second FIFO module is connected with the controller through a handshake type input interface and sequentially outputs the written data blocks through a handshake type output interface.

[0018] According to an aspect of the present disclosure, a data storage method is provided, which is applied to a data storage device including a controller, a first FIFO module, and a second FIFO module, the second FIFO module having a faster speed than the first FIFO module, the controller, the first FIFO module, and the second FIFO module being connected with each other, the method including: determining, by the controller, a first data amount stored in the first FIFO module and a second data amount stored in the second FIFO module; selecting, by the controller, to write a received data block into the first FIFO module or the second FIFO module according to the first data amount and the second data amount, and / or managing data migration between the first FIFO module and the second FIFO module; and outputting data blocks in sequence according to a write order by the second FIFO module.

[0019] In a possible implementation manner, the selecting, by the controller, to write the received data block into the first FIFO module or the second FIFO module according to the first data amount and the second data amount includes: in response to receiving a write operation on the data storage device, performing at least one of the following steps by the controller: in a case where the first data amount is empty and the second data amount is less than a capacity of the second FIFO module, writing the received data block into the second FIFO module; in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, writing the received data block into the first FIFO module; and in a case where the second data amount is equal to the capacity of the second FIFO module, writing the received data block into the first FIFO module.

[0020] In a possible implementation manner, the managing, by the controller, of the data migration between the first FIFO module and the second FIFO module includes: in response to receiving a read operation on the data storage device, controlling, by the controller, the second FIFO module to preferentially execute a read operation to output a data block, so that the second data amount stored in the second FIFO module is less than the capacity of the second FIFO module, and an instruction delay time of the second FIFO module for executing the read operation is a single cycle; and in a case where the first data amount is not empty, triggering a read operation on the first FIFO module to output a data block to the second FIFO module, and an instruction delay time of the first FIFO module for executing the read operation is two cycles.

[0021] In a possible implementation mode, the controller manages the data migration between the first FIFO module and the second FIFO module, including: when the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, the controller controls the first FIFO module to migrate the data block to the second FIFO module.

[0022] In a possible implementation mode, the first FIFO module uses RAM as storage, and the second FIFO module uses a register array as storage.

[0023] In a possible implementation mode, the first FIFO module includes a first single-port RAM unit and a second single-port RAM unit, the first single-port RAM unit and the second single-port RAM unit are physically isolated, and the method further includes: the controller writes the received data block into the first single-port RAM unit and the second single-port RAM unit alternately, so that when the controller writes the received data block into the first single-port RAM unit, the data block is read from the second single-port RAM unit synchronously, or when the controller writes the received data block into the second single-port RAM unit, the data block is read from the first single-port RAM unit synchronously.

[0024] In a possible implementation mode, the first FIFO module further includes a crossbar, and when the first data amount is empty and the second data amount is less than the capacity of the second FIFO module, the received data block is written into the second FIFO module, including: the crossbar selects to pass the data block to the second FIFO module according to the indication of the controller when the first data amount is empty and the second data amount is less than the capacity of the second FIFO module; and / or, when the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, the controller controls the first FIFO module to migrate the data block to the second FIFO module, including: when the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, the written data block is selected to be read from the first single-port RAM unit or the second single-port RAM unit to the second FIFO module.

[0025] In a possible implementation manner, a first write data output terminal of the controller is connected to a write data input terminal of the first single-port RAM unit, a first write enable output terminal of the controller is connected to a write enable input terminal of the first single-port RAM unit, a first write address output terminal of the controller is connected to a write address input terminal of the first single-port RAM unit, a first read enable output terminal of the controller is connected to a read enable input terminal of the first single-port RAM unit, and a first read address output terminal of the controller is connected to a read address input terminal of the first single-port RAM unit; a second write data output terminal of the controller is connected to a write data input terminal of the second single-port RAM unit, a second write enable output terminal of the controller is connected to a write enable input terminal of the second single-port RAM unit, a second write address output terminal of the controller is connected to a write address input terminal of the second single-port RAM unit, a second read enable output terminal of the controller is connected to a read enable input terminal of the second single-port RAM unit, and a second read address output terminal of the controller is connected to a read address input terminal of the second single-port RAM unit; a data pass-through terminal of the controller is connected to a first input terminal of the crossbar switch, an output terminal of the first single-port RAM unit is connected to a second input terminal of the crossbar switch, an output terminal of the second single-port RAM unit is connected to a third input terminal of the crossbar switch, a selection signal output terminal of the controller is connected to a control terminal of the crossbar switch, and an output terminal of the crossbar switch is connected to a data input terminal of the second FIFO module.

[0026] In a possible implementation manner, the controller comprises a counter, and the controller determines the first data amount stored in the first FIFO module and the second data amount stored in the second FIFO module by using the counter.

[0027] In a possible implementation manner, the second FIFO module is connected to the controller through a handshake type input interface and sequentially outputs the written data blocks through a handshake type output interface.

[0028] According to an aspect of the present disclosure, an electronic device is provided, which comprises the data storage apparatus as described above.

[0029] According to an aspect of the present disclosure, a computer readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method described above.

[0030] The data storage device of the embodiment of the present disclosure comprises a controller, a first FIFO module, and a second FIFO module, the speed of the second FIFO module is faster than the speed of the first FIFO module, the controller, the first FIFO module, and the second FIFO module are connected with each other; the controller is configured to determine a first data amount stored in the first FIFO module and a second data amount stored in the second FIFO module; according to the first data amount and the second data amount, select to write a received data block into the first FIFO module or the second FIFO module, and / or manage data migration between the first FIFO module and the second FIFO module; and the second FIFO module is configured to sequentially output data blocks in a writing order. Since the speed of the second FIFO module 3 is faster than the speed of the first FIFO module 2, the energy consumption of the second FIFO module 3 is also more than the energy consumption of the first FIFO module 2. Therefore, the data storage device of the embodiment of the present disclosure can optimize the timing performance of the first FIFO module 2 using the second FIFO module 3, optimize the high energy consumption of the second FIFO module 3 using the first FIFO module 2, and take into account the advantages of the first FIFO module 2 and the second FIFO module 3 at the same time, so as to meet the needs of high-performance, low-power, and high-resource utilization of FIFO memory in the fields of high-speed data communication, real-time signal processing, and high-performance computing.

[0031] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the present disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0033] Figure 1 A structural schematic diagram of a data storage device according to an embodiment of the present disclosure is shown.

[0034] Figure 2 A structural schematic diagram of another data storage device according to an embodiment of the present disclosure is shown.

[0035] Figure 3 A flowchart of a data storage method according to an embodiment of the present disclosure is shown.

[0036] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in different drawings represent the same or similar elements. Although various aspects of embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0038] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0039] In the description of the present disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0040] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0041] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0042] The term "and / or" herein is only a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0043] In addition, for a better illustration of the present disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand, however, that the present disclosure can be practiced without certain specific details, which are set forth in some instances. In some instances, well-known methods, apparatuses, elements and circuits have not been described in detail in order to avoid obscuring the present disclosure.

[0044] In the related art, the FIFO memory can simply use a register array as storage, and such a design scheme completely builds the FIFO memory on the register array. In the implementation process, the writing and reading of data blocks can be controlled by designing a special read-write control logic circuit. When a data block is written, the control logic circuit sequentially stores the data block into the corresponding register according to the write pointer, and the write pointer is automatically incremented to point to the next register position after each data block is stored. Similarly, when reading, the data block is read from the corresponding register according to the read pointer, and the read pointer is incremented. The register array is composed of a large number of flip-flops, which not only occupies a large area, but also consumes a lot of power to maintain the state of each flip-flop. In the scenario of building a large-capacity FIFO memory, a large number of registers are needed, which significantly increases the corresponding power consumption. Taking the image data buffer in a mobile device as an example, if a pure register array FIFO memory is used, during a long image data processing process, high power consumption not only accelerates the consumption of battery power, shortens the device battery life, but also causes the chip to heat up seriously. High temperature can affect the electron migration rate in the chip, increase the probability of circuit failure, and reduce the stability and service life of the chip. Moreover, in large-scale application scenarios such as data centers, the high-power FIFO of a large number of devices will significantly increase the overall power cost and increase the operating burden.

[0045] In the related art, the FIFO memory can also simply use a RAM as storage, and the read-write operation of the RAM includes a complex circuit control process. From the writing process, the address signal needs to be transmitted to the address decoder first, and the corresponding storage unit is found through decoding, and then the data block writing operation is performed. This process involves multiple signal transmission and logic processing steps. Similarly, when reading, there is a significant delay from address decoding to data block reading and transmission. In the field of high-speed data communication, such as the data interaction scenario between a 5G base station and a core network, the read-write delay of the FIFO memory is large, which can cause data transmission to be stuck, cannot meet the real-time requirements, and even cause data loss, which seriously affects the communication quality. In real-time signal processing, such as real-time analysis of radar signals, large delay can cause inaccurate analysis of target signals and miss critical information.

[0046] The data storage device provided by the embodiments of the present disclosure aims to solve the technical problems existing in the FIFO design in large-scale integrated circuits in the related art. For the FIFO using a register array as storage, the high power consumption problem is solved by innovative circuit architecture design (for example, introducing a low-power storage unit), the overall energy consumption is reduced, the storage structure is improved or a new storage technology is adopted, the storage capacity of the register array in the limited chip area is improved, and the resource utilization rate is improved. For the FIFO using RAM as storage, efforts are made to optimize the read-write control logic, improve the storage unit structure, and reduce the read-write delay, improve the data processing speed, and explore new read-write mechanisms to improve the overall performance of the FIFO to meet the needs of high-speed data communication, real-time signal processing, high-performance computing and other fields for high-performance, low-power, high-resource utilization of FIFO.

[0047] Figure 1 The structure of a data storage device according to an embodiment of the present disclosure is shown in a schematic diagram, as shown in Figure 1 The data storage device includes a controller 1, a first FIFO module 2, and a second FIFO module 3, the speed of the second FIFO module 3 is faster than that of the first FIFO module 2, and the controller 1, the first FIFO module 2 and the second FIFO module 3 are connected to each other; the controller 1 is used to determine the first data amount stored in the first FIFO module 2 and the second data amount stored in the second FIFO module 3; according to the first data amount and the second data amount, the received data block is written into the first FIFO module 2 or the second FIFO module 3, and / or the data migration between the first FIFO module 2 and the second FIFO module 3 is managed; the second FIFO module 3 is used to output data blocks in sequence (for example, first-in first-out) according to the writing order.

[0048] Exemplarily, the data block can be data with fixed bits, which can be determined according to the storage word length in the first FIFO module 2 and the second FIFO module 3, that is, the number of binary bits stored in each storage unit in the first FIFO module 2 and the second FIFO module 3, for example, the size of the data block can be 8-bit binary number, 16-bit binary number, 64-bit binary number, etc., and the embodiments of the present disclosure do not limit the specific size of the data block.

[0049] Exemplarily, the first data amount represents the total number of data blocks already stored in the first FIFO module 2, and the second data amount represents the total number of data blocks already stored in the second FIFO module 3.

[0050] For example, assume that the total capacity of the first FIFO module 2 is 100, and the first FIFO module 2 can store a maximum of 100 data blocks, and the total capacity of the second FIFO module 3 is 5, and the second FIFO module 3 can store a maximum of 5 data blocks.

[0051] When the second FIFO module 3 is not full (for example, the second data amount is less than 5) and the first FIFO module 2 is not empty (for example, the first data amount is greater than 0), the controller 1 can instruct the data storage device to perform data migration between the first FIFO module 2 and the second FIFO module 3 inside the data storage device to hide the access latency of the first FIFO module 2, so that the data storage device has the speed of the second FIFO module 3. In addition, in order to maintain the first-in-first-out order of the data blocks, when the second FIFO module 3 is not full (for example, the second data amount is less than 5) and the first FIFO module 2 is not empty (for example, the first data amount is greater than 0), the controller 1 will select to write the newly received data block into the first FIFO module 2, so as to avoid that when the second FIFO module 3 is not full, the data block is incorrectly written into the second FIFO module 3, and the newly entered data block is inserted in front of the data block temporarily stored in the first FIFO module 2.

[0052] When the second FIFO module 3 is not full (for example, the second data amount is less than 5) and the first FIFO module 2 is empty (for example, the first data amount is equal to 0), in order to ensure the fastest response of the data storage device, the controller 1 will select to write the newly received data block into the second FIFO module 3.

[0053] When the second FIFO module 3 is full (for example, the second data amount is equal to 5), the controller 1 can use the advantage of the large capacity of the first FIFO module 2 to select to write the newly received data block into the first FIFO module 2.

[0054] In this way, when the data storage device is not empty, the second FIFO module 3 can save the non-empty state, and when the data storage device receives a request to read a data block, the data storage device can output the data block at the speed of the second FIFO module 3.

[0055] Since the speed of the second FIFO module 3 is faster than the speed of the first FIFO module 2, the energy consumption of the second FIFO module 3 is also higher than the energy consumption of the first FIFO module 2. Therefore, the data storage device of the embodiment of the present disclosure can use the second FIFO module 3 to optimize the timing performance of the first FIFO module 2, use the first FIFO module 2 to optimize the high energy consumption of the second FIFO module 3, and at the same time, take into account the advantages of the first FIFO module 2 and the second FIFO module 3, so as to meet the demand for high performance, low power consumption, and high resource utilization of the FIFO memory in the fields of high-speed data communication, real-time signal processing, and high-performance computing.

[0056] In a possible implementation manner, the first FIFO module 2 uses a random access memory (RAM) as the storage, and the second FIFO module 3 uses a register array as the storage.

[0057] In a possible implementation manner, the controller 1 is connected with the first FIFO module 2 and the second FIFO module 3 as a control component in the data storage device, can statistically obtain the first data amount stored in the first FIFO module 2 and the second data amount stored in the second FIFO module 3 in real time, and make a decision according to the first data amount and the second data amount, and select to write the data block received by the controller 1 into the first FIFO module 2 or the second FIFO module 3, so as to reasonably allocate the storage for the data block. In addition, the controller 1 can also manage the data migration operation between the first FIFO module 2 and the second FIFO module 3 according to the first data amount and the second data amount, to realize flexible allocation of the data.

[0058] The controller 1 can be a chip or a circuit capable of performing numerical calculation and / or information processing according to a pre-set or stored instruction. For example, the controller 1 can be a system on chip (SoC), a microcontroller unit (MCU), an application specific integrated circuit (ASIC), a tensor processing unit (TPU), a field programmable gate array (FPGA) or other programmable logic devices, and the controller 1 can also be implemented by a hardware circuit composed of special analog components, digital circuit components and the like, and the specific implementation manner of the controller 1 is not limited in the present disclosure.

[0059] In a possible implementation manner, the controller 1 comprises a counter, and the controller 1 can use the counter to statistically obtain the first data amount stored in the first FIFO module 2 and the second data amount stored in the second FIFO module 3.

[0060] For example, the counter can use a variable ram_has_data_count to record the first data amount stored in the first FIFO module 2, and use a variable fifo_has_data_count to record the second data amount stored in the second FIFO module 3.

[0061] Whenever a data block is moved from the first FIFO module 2 to the second FIFO module 3, i.e. a data block is taken out from the first FIFO module 2 and sent into the second FIFO module 3, the counter can perform ram_has_data_count-- and fifo_has_data_count++. Wherein -- is a decrement operator for reducing the value of a variable by one, and ++ is an increment operator for increasing the value of a variable by one.

[0062] Whenever the controller 1 writes a received data block into the first FIFO module 2, the counter can perform ram_has_data_count++.

[0063] Whenever the controller 1 writes a received data block into the second FIFO module 3, the counter can perform fifo_has_data_count++.

[0064] Whenever a data block is read out from the second FIFO module 3, the counter can perform fifo_has_data_count--.

[0065] In this way, the counter can record the number of times of writing and reading of data blocks in the first FIFO module 2 and the second FIFO module 3 through the increment or decrement operation on the variable, and reflect the first data amount stored in the first FIFO module 2 and the second data amount stored in the second FIFO module 3 in real time.

[0066] In a possible implementation manner, the controller 1 can know the storage situation of the first FIFO module 2 and the second FIFO module 3 according to the first data amount and the second data amount counted in real time, so as to preferentially use the second FIFO module 3 to write the received data block into the second FIFO module 3, and make the first FIFO module 2 in a shutdown or power-off state, and only activate the first FIFO module 2 to write the received data block into the first FIFO module 2 in a required scenario (for example, the amount of data to be processed is greater than the capacity of the second FIFO module 3).

[0067] In a possible implementation manner, the first FIFO module 2 and the second FIFO module 3 can be used to store data blocks simultaneously, and the controller 1 can manage data migration between the first FIFO module 2 and the second FIFO module 3 according to the first data amount and the second data amount counted in real time. Through background data migration between the first FIFO module 2 and the second FIFO module 3, the access delay of the first FIFO module 2 (using RAM as storage) is hidden, that is, when the second FIFO module 3 (using a register array as storage) is not full and the first FIFO module 2 is not empty, data migration from the RAM storage to the register array is performed in the data storage device according to the instruction of the controller 1, so that when a read request of the data storage device is received, data can be directly read from the register group, and the access speed at this time is still equivalent to that of the register type FIFO.

[0068] In the data storage device, the capacity of the first FIFO module 2 with a read delay of 2 cycles is greater than that of the second FIFO module 3 supporting single-cycle readout. For ease of understanding, the data storage device of the embodiment of the present disclosure is described below by taking the second FIFO module 3 as a register type FIFO with a capacity of 3 (up to 3 data blocks can be stored) as an example. It should be understood that the embodiment of the present disclosure does not specifically limit the specific capacity of the second FIFO module 3, and the capacity can be set according to the actual application scenario.

[0069] In a possible implementation manner, the controller 1 is configured to, in response to receiving a write operation on the data storage device, perform at least one of the following steps: in a case where the first data amount is empty and the second data amount is less than the capacity of the second FIFO module 3, writing the received data block into the second FIFO module 3; in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module 3, writing the received data block into the first FIFO module 2; and in a case where the second data amount is equal to the capacity of the second FIFO module 3, writing the received data block into the first FIFO module 2.

[0070] In this way, the data block can be preferentially written into the second FIFO module 3, but if there is a queued data block in the first FIFO module 2, the data block is written into the first FIFO module 2 first, so as to avoid time sequence disorder caused by “inserting” the data block.

[0071] For example, in a case where the first data amount is empty and the second data amount is less than the capacity of the second FIFO module 3, the controller 1 writes the received data block into the second FIFO module 3.

[0072] Assume that a variable ram_has_data_count is used to record the first data amount stored in the first FIFO module 2, and a variable fifo_has_data_count is used to record the second data amount stored in the second FIFO module 3. When the second data amount fifo_has_data_count < 3 and the first data amount ram_has_data_count = 0, the priority of the second FIFO module 3 is higher than that of the first FIFO module 2, and the controller 1 directly writes the received data block into the second FIFO module 3 to achieve the fastest response.

[0073] In this way, for the data amount less than the capacity of the second FIFO module 3, the data storage device of the embodiment of the present disclosure only uses the second FIFO module 3 to store data, and the behavior of the data storage device at this time is equivalent to that of a register-type FIFO, which has the characteristic of fast access speed.

[0074] Exemplarily, the controller 1 writes the received data block into the first FIFO module 2 when the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module 3.

[0075] Assume that a variable ram_has_data_count is used to record the first data amount stored in the first FIFO module 2, and a variable fifo_has_data_count is used to record the second data amount stored in the second FIFO module 3. When the second data amount fifo_has_data_count < 3 and the first data amount ram_has_data_count > 0, the controller 1 writes the received data block into the first FIFO module 2, so as to avoid that the data block is incorrectly written into the second FIFO module 3 when the second FIFO module 3 is not full, and the newly entered data block is inserted before the data block temporarily stored in the first FIFO module 2.

[0076] Exemplarily, the controller 1 writes the received data block into the first FIFO module 2 when the second data amount is equal to the capacity of the second FIFO module 3.

[0077] Assume that a variable ram_has_data_count is used to record the first data amount stored in the first FIFO module 2, and a variable fifo_has_data_count is used to record the second data amount stored in the second FIFO module 3. When the second data amount fifo_has_data_count = 3, it indicates that the capacity of the second FIFO module 3 is full, and the controller 1 can write the received data block into the first FIFO module 2.

[0078] In this way, in the case where the second FIFO module 3 is full of data, the first FIFO module 2 using RAM as storage is forced to write, so as to take advantage of its large capacity.

[0079] In one possible implementation, the controller 1, in response to receiving a read operation on the data storage device, performs the following steps: controlling the second FIFO module 3 to preferentially perform a read operation to output a data block, so that the second data amount stored in the second FIFO module 3 is less than the capacity of the second FIFO module 3, and the instruction delay time of the second FIFO module 3 performing the read operation is one cycle; in the case where the first data amount is not empty, triggering a read operation on the first FIFO module 2, so that the first FIFO module 2 outputs a data block to the second FIFO module 3, and the instruction delay time of the first FIFO module 2 performing the read operation is two cycles.

[0080] In this way, data can be preferentially read from the second FIFO module 3 (one cycle delay), and if the first data amount stored in the first FIFO module 2 is greater than 0, indicating that the first FIFO module 2 is not empty, a read operation of the first FIFO module 2 can be triggered (2 cycle delay), and the read data block is supplemented into the second FIFO module 3, so as to maintain the non-empty state of the second FIFO module 3, so that the data storage device behaves like the second FIFO module 3, and has the characteristic of fast access speed.

[0081] For example, the controller 1, in the case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module 3, controls the first FIFO module 2 to migrate a data block written by the first FIFO module 2 to the second FIFO module 3.

[0082] Suppose that a variable ram_has_data_count is used to record the first data amount stored in the first FIFO module 2, and a variable fifo_has_data_count is used to record the second data amount stored in the second FIFO module 3. When the second data amount fifo_has_data_count < 3 and the first data amount ram_has_data_count > 0, a read operation of the first FIFO module 2 is triggered, and the read data block is supplemented into the second FIFO module 3, so as to keep the second FIFO module 3 in a non-empty state through data migration between the first FIFO module 2 and the second FIFO module 3, so as to timely take out the stored data block when a read request is performed on the data storage device.

[0083] In one possible implementation, considering that there is a 2-cycle delay in the read operation of the RAM memory, the second FIFO module 3 (using a register array as storage) supports single-cycle read, and when a large number of read operations occur for the data storage device, the data migration from the first FIFO module 2 to the second FIFO module 3 can not be completed in time, which can cause the access speed of the data storage device to be reduced to the speed of the first FIFO module 2 (using RAM as storage). Therefore, according to the actual use scenario, the second FIFO module 3 can be set to be deep enough to reduce the probability of occurrence of the case.

[0084] For example, the first FIFO module 2 can use a dual-port RAM as storage, and since there is a 2-cycle delay in each read operation of the dual-port RAM, the capacity of the second FIFO module 3 (using a register array as storage) can be set to be an integer greater than or equal to 3, so as to trade space for time of the register array, and improve the read speed of the data storage device as a whole, so as to make the read speed as close as possible to the read speed of the second FIFO module 3.

[0085] For example, the first FIFO module 2 can use two single-port RAMs as storage, one single-port RAM has odd addresses, and the other single-port RAM has even addresses, so as to alternately store the data blocks written by the controller. Considering that there is a 2-cycle delay in the read operation of the RAM memory, the first FIFO module 2 has a 4-cycle (2*2) delay, and the capacity of the second FIFO module 3 (using a register array as storage) can be set to be an integer greater than or equal to 5, so as to trade space for time of the register array, and improve the read speed of the data storage device as a whole, so as to make the read speed as close as possible to the read speed of the second FIFO module 3.

[0086] For example, the second FIFO module 3 can output the written data blocks in the order of first-in first-out.

[0087] The data storage device of the embodiment of the present disclosure can use the second FIFO module 3 to optimize the timing performance of the first FIFO module 2, and use the first FIFO module 2 to optimize the high energy consumption of the second FIFO module 3, while taking into account the advantages of the first FIFO module 2 and the second FIFO module 3, so as to meet the demand for high performance, low power consumption, and high resource utilization of the FIFO memory in the fields of high-speed data communication, real-time signal processing, and high-performance computing.

[0088] Figure 2 Fig. 1 shows a structure schematic diagram of another data storage device according to an embodiment of the present disclosure, which comprises a controller 1, a first FIFO module 2 using RAM as storage, a second FIFO module 3 using register array as storage, and the controller 1, the first FIFO module 2 and the second FIFO module 3 are connected with each other. Figure 2

[0089] As shown in Fig. 1, the controller 1 is the front end of the data storage device, which is used to receive a data block in_data from an external processor (such as CPU, GPU, etc.). In order to process the data transmission between the controller 1 and the external processor across clock domains, the communication protocol between the controller 1 and the external processor can adopt a handshake protocol. For example, when the processor (sender) is ready to send the data block in_data to the controller 1 (receiver), the processor can send a first identification signal in_vid to the controller 1; when the controller 1 is ready to receive the data block in_data, the controller 1 can send a second identification signal in_rdy to the processor; at this time, the controller 1 and the external processor successfully handshake, and the external processor can send the data block in_data to the controller 1. Figure 2

[0090] Among them, the first identification signal in_vid is used to indicate whether the data block in_data is valid, and the second identification signal in_rdy is used to indicate whether the controller 1 (receiver) is ready to receive data. Only when both the first identification signal in_vid and the second identification signal in_rdy are valid, the data transmission will occur, so as to ensure that the data block is transmitted at the right time.

[0091] After receiving the data block in_data, the controller 1 can select to write the data block in_data to the first FIFO module 2 or the second FIFO module 3 according to the control logic.

[0092] In the design of high-speed data pipeline, the related art using RAM FIFO implementation will face the contradiction of storage architecture selection.

[0093] If single-port storage unit (SPRAM) is used, the chip area can be reduced, for example, about 30%-40% of the chip area, and the specific data will be affected by the process. However, due to the single-port storage unit (SPRAM), the read and write operations must be performed at different times, which results in that only single data transmission can be completed in each clock cycle, and the theoretical throughput is limited (for example, the peak bandwidth = 1 transaction / cycle).

[0094] ​​If a dual-port memory unit (DPRAM) is used, read and write operations can be supported in parallel (e.g., theoretical bandwidth = 2 transactions / cycle), meeting the requirement of full-speed pipeline operation. However, independent read and write port circuits and arbitration logic need to be added, resulting in an increase in the area of the memory unit. For example, compared with a single-port memory unit of the same capacity, the area can be increased by about 40%-60%, and the specific data can be affected by the process.

[0095] It can be seen that, in order to further improve the overall performance of the data storage device, the RAM needs to be reasonably used to reduce the area, while the final system performance also needs to be considered. As shown in Figure 2 The first FIFO module 2 of the embodiment of the present disclosure includes a first single-port RAM unit 21, a second single-port RAM unit 22, and a crossbar 23. The first single-port RAM unit 21 and the second single-port RAM unit 22 are physically isolated.

[0096] In a possible implementation manner, the controller 1 writes the received data block in_data into the first FIFO module 2, including: alternately writing the received data block in_data into the first single-port RAM unit 21 and the second single-port RAM unit 22, so that, when the controller 1 writes the received data block in_data into the first single-port RAM unit 21, the written data block is synchronously read from the second single-port RAM unit 22, or, when the controller 1 writes the received data block in_data into the second single-port RAM unit 22, the written data block is synchronously read from the first single-port RAM unit 21.

[0097] Optionally, the controller 1 can alternately write the received data block in_data into the first single-port RAM unit 21 and the second single-port RAM unit 22 through a write state machine. The first single-port RAM unit 21 can be used to store data blocks of odd addresses, and the second single-port RAM unit 22 can be used to store data blocks of even addresses. In this way, when the data blocks are subsequently moved from the first FIFO module 2 to the second FIFO module 3, it is considered that the data blocks written first are moved out first, and at the same time, the data blocks need to be alternately taken from the first single-port RAM unit 21 and the second single-port RAM unit 22 to the second FIFO module 3.

[0098] Thus, although the first single-port RAM unit 21 and the second single-port RAM unit 22 cannot read and write data simultaneously by themselves, when the first single-port RAM unit 21 is in a write cycle, the second single-port RAM unit 22 enters a read cycle synchronously, and when the second single-port RAM unit 22 is in a write cycle, the first single-port RAM unit 21 enters a read cycle synchronously, by regarding the first single-port RAM unit 21 and the second single-port RAM unit 22 as a whole, the first FIFO module 2 realizes synchronization of reading and writing while reducing chip area.

[0099] As shown in FIG. 1, the controller 1 includes a first write data output terminal P11, a first write enable output terminal P12, a first write address output terminal P13, a first read enable output terminal P14, and a first read address output terminal P15. Figure 2 The first write data output terminal P11 of the controller 1 is connected to a write data input terminal A1 of the first single-port RAM unit 21, and the controller 1 can transmit a data block in_data as write data ram_write_data1 to the first single-port RAM unit 21 through the first write data output terminal P11 and the write data input terminal A1.

[0100] The first write enable output terminal P12 of the controller 1 is connected to a write enable input terminal A2 of the first single-port RAM unit 21, and is used to transmit a write enable signal ram_write_enable1 to the first single-port RAM unit 21.

[0101] The first write address output terminal P13 of the controller 1 is connected to a write address input terminal A3 of the first single-port RAM unit 21, and is used to transmit a write address signal ram_write_address1 to the first single-port RAM unit 21.

[0102] The first read enable output terminal P14 of the controller 1 is connected to a read enable input terminal A4 of the first single-port RAM unit 21, and is used to transmit a read enable signal ram_read_enable1 to the first single-port RAM unit 21.

[0103] The first read address output terminal P15 of the controller 1 is connected to a read address input terminal A5 of the first single-port RAM unit 21, and is used to transmit a read address signal ram_read_address1 to the first single-port RAM unit 21.

[0104] The second write data output terminal P16 of the controller 1 is connected to a write data input terminal B1 of the second single-port RAM unit 22, and the controller 1 can transmit a data block in_data as write data ram_write_data2 to the second single-port RAM unit 22 through the second write data output terminal P16 and the write data input terminal B1.

[0105] The second write enable output P17 of the controller 1 is connected to the write enable input B2 of the second single-port RAM unit 22 for transmitting a write enable signal ram_write_enable2 to the second single-port RAM unit 22;

[0106] The second write address output P18 of the controller 1 is connected to the write address input B3 of the second single-port RAM unit 22 for transmitting a write address signal ram_write_address2 to the second single-port RAM unit 22;

[0107] The second read enable output P19 of the controller 1 is connected to the read enable input B4 of the second single-port RAM unit 22 for transmitting a read enable signal ram_read_enable2 to the second single-port RAM unit 22;

[0108] The second read address output P20 of the controller 1 is connected to the read address input B5 of the second single-port RAM unit 22 for transmitting a read address signal ram_read_address2 to the second single-port RAM unit 22.

[0109] For example, the controller 1 can write the first single-port RAM unit 21 and the second single-port RAM unit 22 alternately by a write state machine. The state of the write state machine can include 0 and 1, and the state of the write state machine can be changed once, for example, from 0 to 1, or from 1 to 0, every time a data block is written into the first FIFO module 2.

[0110] If the state of the write state machine is 0, the write enable signal ram_write_enable1 is valid, and the data block in_data can be sent into the first single-port RAM unit 21 as the write data ram_write_data1 at the position indicated by the write address signal ram_write_address1.

[0111] If the state of the write state machine is 1, the write enable signal ram_write_enable2 is valid, and the data block in_data can be sent into the second single-port RAM unit 22 as the write data ram_write_data2 at the position indicated by the write address signal ram_write_address2.

[0112] Similarly, the controller 1 can read the first single-port RAM unit 21 and the second single-port RAM unit 22 alternately by a read state machine. The state of the read state machine can include 0 and 1, and the state of the read state machine can be changed once, for example, from 0 to 1, or from 1 to 0, every time a data block is read from the first FIFO module 2.

[0113] If the state of the readout state machine is 0, the read enable signal ram_read_enable1 is valid, and the first single-port RAM unit 21 can read the first written data block ram_out_data1 at the position indicated by the address signal ram_read_address1.

[0114] If the state of the readout state machine is 1, the read enable signal ram_read_enable2 is valid, and the second single-port RAM unit 22 can read the first written data block ram_out_data2 at the position indicated by the address signal ram_read_address2.

[0115] The data bypass port P21 of the controller 1 is connected to the first input terminal C1 of the crossbar switch 23, and the controller 1 can transmit the data block in_data as bypass data in_data_bypass to the crossbar switch 23 through the data bypass port P21 and the first input terminal C1 of the crossbar switch 23, so as to transmit the data block in_data received by the controller 1 to the second FIFO module 3 through the crossbar switch 23.

[0116] The output terminal A6 of the first single-port RAM unit 21 is connected to the second input terminal C2 of the crossbar switch 23, for transmitting the written data block ram_out_data1 to the crossbar switch 23.

[0117] The output terminal B6 of the second single-port RAM unit 22 is connected to the third input terminal C3 of the crossbar switch 23, for transmitting the written data block ram_out_data2 to the crossbar switch 23.

[0118] The selection signal output terminal P22 of the controller 1 is connected to the control terminal C4 of the crossbar switch 23, for providing the control signal ctl to the crossbar switch 23, and the output terminal C5 of the crossbar switch 23 is connected to the data input terminal of the second FIFO module 3.

[0119] In a possible implementation, the crossbar switch 23 is configured to select, according to the indication of the controller 1, in the case that the first data amount is empty and the second data amount is less than the capacity of the second FIFO module 3, to transmit the data block in_data to the second FIFO module 3, and in the case that the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module 3, to read the written data block from the first single-port RAM unit 21 or the second single-port RAM unit 22 to the second FIFO module 3.

[0120] For example, the control signal ctl can include a first state, a second state, and a third state. When the first data amount is empty and the second data amount is less than the capacity of the second FIFO module 3, the control signal ctl is in the first state, and the crossbar switch 23 can transmit the data block in_data_bypass output by the controller 1 (i.e., the data block in_data received by the controller 1) as the output data inner_fifo_in_data to the second FIFO module 3 according to the indication of the control signal ctl.

[0121] When the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module 3, if the state of the readout state machine is 0 and the read enable signal ram_read_enable1 is enabled, the control signal ctl is in the second state, and the crossbar switch 23 can read the data block ram_out_data1 written in the position indicated by the address signal ram_read_address1 from the first single-port RAM unit 21 as the output data inner_fifo_in_data to the second FIFO module 3 according to the indication of the control signal ctl.

[0122] When the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module 3, if the state of the readout state machine is 1 and the read enable signal ram_read_enable2 is enabled, the control signal ctl is in the third state, and the crossbar switch 23 can read the data block ram_out_data2 written in the position indicated by the address signal ram_read_address2 from the second single-port RAM unit 22 as the output data inner_fifo_in_data to the second FIFO module 3 according to the indication of the control signal ctl.

[0123] In this way, the crossbar switch 23 can dynamically select the data transmission path according to the indication of the controller 1, and the first FIFO module 3 is activated only when needed, thereby reducing the static power consumption. Moreover, the subsequent read operation on the data storage device is completed through the second FIFO module 3, thereby achieving single-cycle response of the read data and improving the read speed.

[0124] In a possible implementation, the second FIFO module 3 is connected to the controller 1 through a handshake type input interface and sequentially outputs the written data blocks through a handshake type output interface.

[0125] As Figure 2As shown, in order to reduce the transmission error caused by timing, the data transmission between the second FIFO module 3 and the upstream and downstream modules can adopt a handshake protocol. The second FIFO module 3 is connected to the controller 1 through a handshake type input interface and outputs the written data block through a handshake type output interface.

[0126] For example, when the controller 1 detects that the crossbar 23 (sender) is ready to send the output data block inner_fifo_in_data to the second FIFO module 3 (receiver), the controller 1 can send an identification signal inner_fifo_in_vid to the second FIFO module 3; when the second FIFO module 3 is ready to receive the data block inner_fifo_in_data, the second FIFO module 3 can send an identification signal inner_fifo_in_rdy to the controller 1; at this time, the second FIFO module 3 and the controller 1 successfully handshake, and the controller can instruct the crossbar 23 to move the data block inner_fifo_in_data to the second FIFO module 3 through a control signal ctl.

[0127] The identification signal inner_fifo_in_vid is used to indicate whether the data block inner_fifo_in_data input into the second FIFO module 3 is valid, and the identification signal inner_fifo_in_rdy is used to indicate whether the second FIFO module 3 (receiver) is ready to receive the data block. Only when both the identification signal inner_fifo_in_vid and the identification signal inner_fifo_in_rdy are valid, the data block transmission occurs, thereby ensuring that the data block is transmitted at the correct time.

[0128] Similarly, when the second FIFO module 3 (sender) is ready to send the output data block out_data to the downstream module (receiver), the second FIFO module 3 can send an identification signal out_vid to the downstream module; when the second FIFO module 3 receives the identification signal out_rdy from the downstream module, it indicates that the downstream module is ready to receive the data block, at this time, the second FIFO module 3 and the downstream module successfully handshake, and the second FIFO module 3 can output the data block out_data to the downstream module.

[0129] The identification signal out_vid is used to indicate whether the output data block out_data of the second FIFO module 3 is valid, and the identification signal out_rdy is used to indicate whether the downstream module (receiver) is ready to receive the data block. Only when both the identification signal out_vid and the identification signal out_rdy are valid, the data block transmission occurs, thereby ensuring that the data block is transmitted at the correct time.

[0130] In this way, by setting the handshake interface, it can be ensured that the data block is transmitted at the right time, and the accuracy of data transmission is improved.

[0131] In summary, the data storage device of the embodiment of the present disclosure can optimize the timing performance of the first FIFO module 2 using the second FIFO module 3, optimize the high energy consumption of the second FIFO module 3 using the first FIFO module 2, and take into account the advantages of the first FIFO module 2 and the second FIFO module 3 at the same time, to meet the demand for high performance, low power consumption, and high resource utilization of FIFO memory in the fields of high-speed data communication, real-time signal processing, and high-performance computing.

[0132] Among them, the first FIFO module 2 is only activated when needed, for example, for a scenario where the data volume is less than the capacity of the second FIFO module 3, only the second FIFO module 3 can be used to store data, at this time, the behavior of the data storage device is equivalent to a register type FIFO, not only the access speed is fast, but also the static power consumption is greatly reduced.

[0133] When the second FIFO module 3 is full of data, the data block can be written into the first FIFO module 2 using RAM as storage to take advantage of its large capacity and low power consumption. Compared with a pure register stack FIFO, the data storage device combining the first FIFO module 2 and the second FIFO module 3 greatly reduces the chip area; further, if the first FIFO module 2 uses two physically isolated first single-port RAM unit 21 and second single-port RAM unit 22, compared with a dual-port storage unit (DPRAM), using two single-port RAMs can further reduce the chip area.

[0134] In addition, through the data migration between the first FIFO module 2 and the second FIFO module 3, the second FIFO module 3 is kept in a non-empty state, so that when a read request is performed on the data storage device, the stored data block can be taken out in time, that is, all read operations on the data storage device are completed through the second FIFO module 3, which are all single-cycle read operations.

[0135] It can be understood that the above-mentioned various method embodiments of the present disclosure can be combined with each other to form combined embodiments without violating the principle logic. Limited by the length, the present disclosure will not be repeated. Those skilled in the art can understand that in the above-mentioned method of the specific embodiment, the specific execution order of each step should be determined by its function and possible internal logic.

[0136] In addition, the present disclosure also provides a data storage device, an electronic device, a computer readable storage medium, and a program, which can be used to implement any one of the data storage methods provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding description in the method part, and will not be repeated.

[0137] Figure 3 A flow chart of a data storage method according to an embodiment of the present disclosure is shown in FIG. 1. Figure 3 As shown in FIG. 1, the method is applied to a data storage device, which comprises a controller, a first FIFO module, and a second FIFO module, the second FIFO module having a faster speed than the first FIFO module, the controller, the first FIFO module, and the second FIFO module being connected to each other, and the method comprises:

[0138] In step S11, the controller determines a first data amount stored in the first FIFO module and a second data amount stored in the second FIFO module.

[0139] In step S12, the controller selects to write a received data block into the first FIFO module or the second FIFO module according to the first data amount and the second data amount, and / or manages data migration between the first FIFO module and the second FIFO module.

[0140] In step S13, the second FIFO module sequentially outputs data blocks in a write order.

[0141] In a possible implementation manner, step S12 can comprise: in response to receiving a write operation on the data storage device, the controller performs at least one of the following steps: in a case where the first data amount is empty and the second data amount is less than a capacity of the second FIFO module, writing the received data block into the second FIFO module; in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, writing the received data block into the first FIFO module; and in a case where the second data amount is equal to the capacity of the second FIFO module, writing the received data block into the first FIFO module.

[0142] In a possible implementation manner, step S12 can comprise: in response to receiving a read operation on the data storage device, the controller controls the second FIFO module to preferentially perform a read operation to output a data block, so that the second data amount stored in the second FIFO module is less than the capacity of the second FIFO module, and an instruction delay time of the second FIFO module performing the read operation is a single cycle; and in a case where the first data amount is not empty, triggering a read operation on the first FIFO module to output a data block from the first FIFO module to the second FIFO module, and an instruction delay time of the first FIFO module performing the read operation is two cycles.

[0143] In a possible implementation manner, the step S12 can include: in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, the controller controls the first FIFO module to migrate the data block to the second FIFO module.

[0144] In a possible implementation manner, the first FIFO module uses a RAM as a storage, and the second FIFO module uses a register array as a storage.

[0145] In a possible implementation manner, the first FIFO module includes a first single-port RAM unit and a second single-port RAM unit, the first single-port RAM unit is physically isolated from the second single-port RAM unit, and the method further includes: the controller writes the received data block into the first single-port RAM unit and the second single-port RAM unit alternately, so that, in a case where the controller writes the received data block into the first single-port RAM unit, the data block is read from the second single-port RAM unit synchronously, or, in a case where the controller writes the received data block into the second single-port RAM unit, the data block is read from the first single-port RAM unit synchronously.

[0146] In a possible implementation manner, the first FIFO module includes a crossbar, and in a case where the first data amount is empty and the second data amount is less than the capacity of the second FIFO module, the received data block is written into the second FIFO module, which includes: the crossbar selects, according to an indication of the controller, in a case where the first data amount is empty and the second data amount is less than the capacity of the second FIFO module, to transmit the data block to the second FIFO module; and / or, in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, the controller controls the first FIFO module to migrate the data block to the second FIFO module, which includes: in a case where the first data amount is not empty and the second data amount is less than the capacity of the second FIFO module, the written data block is selected to be read from the first single-port RAM unit or the second single-port RAM unit to the second FIFO module.

[0147] In a possible implementation manner, a first write data output terminal of the controller is connected to a write data input terminal of the first single-port RAM unit, a first write enable output terminal of the controller is connected to a write enable input terminal of the first single-port RAM unit, a first write address output terminal of the controller is connected to a write address input terminal of the first single-port RAM unit, a first read enable output terminal of the controller is connected to a read enable input terminal of the first single-port RAM unit, and a first read address output terminal of the controller is connected to a read address input terminal of the first single-port RAM unit; a second write data output terminal of the controller is connected to a write data input terminal of the second single-port RAM unit, a second write enable output terminal of the controller is connected to a write enable input terminal of the second single-port RAM unit, a second write address output terminal of the controller is connected to a write address input terminal of the second single-port RAM unit, a second read enable output terminal of the controller is connected to a read enable input terminal of the second single-port RAM unit, and a second read address output terminal of the controller is connected to a read address input terminal of the second single-port RAM unit; a data pass-through terminal of the controller is connected to a first input terminal of the crossbar switch, an output terminal of the first single-port RAM unit is connected to a second input terminal of the crossbar switch, an output terminal of the second single-port RAM unit is connected to a third input terminal of the crossbar switch, a selection signal output terminal of the controller is connected to a control terminal of the crossbar switch, and an output terminal of the crossbar switch is connected to a data input terminal of the second FIFO module.

[0148] In a possible implementation manner, the controller comprises a counter, and step S11 can comprise: determining, by the controller, a first data amount stored in the first FIFO module and a second data amount stored in the second FIFO module by using the counter.

[0149] In a possible implementation manner, the second FIFO module is connected to the controller through a handshake type input interface and sequentially outputs the written data blocks through a handshake type output interface.

[0150] In some embodiments, the apparatus provided by the embodiments of the present disclosure has functions or comprises modules that can be used to execute the methods described in the above method embodiments, and the specific implementation can be referred to the description of the above method embodiments, which will not be described here again for simplicity.

[0151] The embodiments of the present disclosure also provide a computer readable storage medium having stored computer program instructions, and the computer program instructions are executed by a processor to implement the above method. The computer readable storage medium can be a volatile or non-volatile computer readable storage medium.

[0152] The embodiments of the present disclosure also provide an electronic device comprising the data storage apparatus described above.

[0153] The embodiment of the disclosure further provides a computer program product, comprising computer readable code or a nonvolatile computer readable storage medium carrying computer readable code, when the computer readable code is executed in the processor of the electronic device, the processor in the electronic device executes the above method.

[0154] The electronic device can be provided as a terminal, a server or other forms of devices.

[0155] Figure 4 A block diagram of an electronic device 1900 according to an embodiment of the disclosure is shown. For example, the electronic device 1900 can be provided as a server or a terminal device. Referring to Figure 4 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by a memory 1932 (such as the data storage device described above) for storing instructions executable by the processing component 1922, such as an application program. The application program stored in the memory 1932 can include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0156] The electronic device 1900 can also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 can operate based on an operating system stored in the memory 1932, such as a server operating system (Windows Server TM ), a graphical user interface operating system (OS X TM ), a multi-user multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or the like.

[0157] In an exemplary embodiment, a non-volatile computer readable storage medium, such as the memory 1932 comprising computer program instructions executable by the processing component 1922 of the electronic device 1900 to complete the above method, is also provided.

[0158] The disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0159] Computer readable storage media can be tangible storage devices that can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0160] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0161] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0162] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0163] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other data storage device. When the computer readable program instructions are loaded into the computer and other programmable data processing apparatus, a series of operational steps are implemented that provide processes such that the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0164] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0165] The flow diagrams and the block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logic functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0166] The computer program product can be embodied in a tangible medium of

[0167] The above description of the various embodiments is intended to be illustrative in all aspects, rather than being restrictive. Those skilled in the art can refer to the description of the various embodiments to make modifications and / or improvements.

[0168] Those skilled in the art can understand that, in the above-described method of the specific embodiments, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible inherent logic.

[0169] If the technical solutions of the present application involve personal information, the product applying the technical solutions of the present application has been explicitly informed of the personal information processing rules before processing the personal information, and has obtained the personal independent consent. If the technical solutions of the present application involve sensitive personal information, the product applying the technical solutions of the present application has obtained the personal independent consent before processing the sensitive personal information, and at the same time meets the requirement of "explicit consent". For example, at the personal information collection device such as camera, a clear and prominent mark is set to inform that it has entered the personal information collection range and will collect personal information. If the individual voluntarily enters the collection range, it is considered to agree to collect personal information. Or on the device for processing personal information, through the pop-up information or by asking the individual to upload his personal information, the individual's authorization is obtained under the condition that the device uses obvious mark / information to inform the individual of the personal information processing rules. The personal information processing rules can include personal information processor, personal information processing purpose, processing method and personal information type, etc.

[0170] The above has described various embodiments of the present disclosure, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles, practical application or improvement of technology in the market of the embodiments, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data storage device, characterized in that, include: The system includes a controller, a first FIFO module, and a second FIFO module, wherein the second FIFO module is faster than the first FIFO module, and the controller, the first FIFO module, and the second FIFO module are interconnected. The controller is configured to determine a first amount of data stored in the first FIFO module and a second amount of data stored in the second FIFO module; and, based on the first amount of data and the second amount of data, select to write the received data block into the first FIFO module or the second FIFO module, and / or manage the data migration between the first FIFO module and the second FIFO module. The second FIFO module is used to output data blocks sequentially according to the writing order.

2. The apparatus according to claim 1, characterized in that, In response to receiving a write operation on the data storage device, the controller performs at least one of the following steps: If the first data volume is empty and the second data volume is less than the capacity of the second FIFO module, the received data block is written into the second FIFO module; If the first data volume is not empty and the second data volume is less than the capacity of the second FIFO module, the received data block is written into the first FIFO module; When the second data volume is equal to the capacity of the second FIFO module, the received data block is written into the first FIFO module.

3. The apparatus according to claim 1, characterized in that, In response to receiving a read operation on the data storage device, the controller controls the second FIFO module to prioritize the read operation and output data blocks, so that the amount of the second data stored in the second FIFO module is less than the capacity of the second FIFO module.

4. The apparatus according to claim 3, characterized in that, If the first data volume is not empty, a read operation is triggered on the first FIFO module so that the first FIFO module outputs a data block to the second FIFO module.

5. The apparatus according to claim 4, characterized in that, The instruction delay time for the second FIFO module to perform a read operation is one cycle; the instruction delay time for the first FIFO module to perform a read operation is two cycles.

6. The apparatus according to claim 1, characterized in that, The controller is configured to control the migration of data blocks from the first FIFO module to the second FIFO module when the first data volume is not empty and the second data volume is less than the capacity of the second FIFO module.

7. The apparatus according to claim 1, characterized in that, The first FIFO module uses RAM as storage, and the second FIFO module uses a register array as storage.

8. The apparatus according to any one of claims 1 to 7, characterized in that, The first FIFO module includes a first single-port RAM unit and a second single-port RAM unit, wherein the first single-port RAM unit and the second single-port RAM unit are physically isolated. The controller is configured to write the received data blocks into the first single-port RAM unit and the second single-port RAM unit in turn, so that when the controller writes the received data blocks into the first single-port RAM unit, it synchronously reads data blocks from the second single-port RAM unit, or when the controller writes the received data blocks into the second single-port RAM unit, it synchronously reads data blocks from the first single-port RAM unit.

9. The apparatus according to claim 8, characterized in that, The first FIFO module further includes a cross switch, which is used, according to the controller's instruction, to select to pass the data block to the second FIFO module when the first data volume is empty and the second data volume is less than the capacity of the second FIFO module, and / or to select to read the written data block from the first single-port RAM unit or the second single-port RAM unit to the second FIFO module when the first data volume is not empty and the second data volume is less than the capacity of the second FIFO module.

10. The apparatus according to claim 9, characterized in that, The controller's first write data output terminal is connected to the write data input terminal of the first single-port RAM unit, the controller's first write enable output terminal is connected to the write enable input terminal of the first single-port RAM unit, the controller's first write address output terminal is connected to the write address input terminal of the first single-port RAM unit, the controller's first read enable output terminal is connected to the read enable input terminal of the first single-port RAM unit, and the controller's first read address output terminal is connected to the read address input terminal of the first single-port RAM unit. The controller's second write data output terminal is connected to the write data input terminal of the second single-port RAM unit, the controller's second write enable output terminal is connected to the write enable input terminal of the second single-port RAM unit, the controller's second write address output terminal is connected to the write address input terminal of the second single-port RAM unit, the controller's second read enable output terminal is connected to the read enable input terminal of the second single-port RAM unit, and the controller's second read address output terminal is connected to the read address input terminal of the second single-port RAM unit. The controller's data pass-through terminal is connected to the first input terminal of the cross switch, the output terminal of the first single-port RAM unit is connected to the second input terminal of the cross switch, the output terminal of the second single-port RAM unit is connected to the third input terminal of the cross switch, the controller's selection signal output terminal is connected to the control terminal of the cross switch, and the output terminal of the cross switch is connected to the data input terminal of the second FIFO module.

11. The apparatus according to any one of claims 1 to 7, characterized in that, The controller includes a counter, which is used to determine a first amount of data stored in the first FIFO module and a second amount of data stored in the second FIFO module.

12. The apparatus according to any one of claims 1 to 7, characterized in that, The second FIFO module is connected to the controller through a handshake-type input interface and sequentially outputs the written data blocks through a handshake-type output interface.

13. A data storage method, characterized in that, The method is applied to a data storage device, the data storage device comprising: a controller, a first FIFO module, and a second FIFO module, wherein the second FIFO module has a faster speed than the first FIFO module, and the controller, the first FIFO module, and the second FIFO module are interconnected. The method includes: The controller determines the first amount of data stored in the first FIFO module and the second amount of data stored in the second FIFO module; The controller selects to write the received data block into the first FIFO module or the second FIFO module based on the first data volume and the second data volume, and / or manages the data migration between the first FIFO module and the second FIFO module; The second FIFO module outputs data blocks sequentially according to the writing order.

14. An electronic device, characterized in that, The electronic device includes the data storage device according to any one of claims 1 to 12.

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