Fault information storage method and device, electronic equipment and storage medium

Abstract

The invention discloses a fault information storage method and device, electronic equipment and a storage medium, and belongs to the field of memories. The method comprises the following steps: responding to a target mode register to finish one-time memory error detection and scrubbing ECS result recording, and reading first address information with a memory error or second address information with the memory error recorded in the target mode register, the first address information is the address information corresponding to the memory error with successful error correction, and the second address information is the address information corresponding to the memory error with failed error correction; fault information corresponding to the memory error is stored in a nonvolatile memory, the fault information comprises the first address information or the second address information and identification information, and the identification information is used for identifying whether error correction of the memory error succeeds or not.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of storage, and particularly relates to a fault information storage method and device, an electronic device and a storage medium. BACKGROUND

[0002] With the development of mobile Internet and artificial intelligence technology, the bandwidth, capacity and reliability of terminal devices on memory are increasingly improved. For example, in the related art, a dynamic random access memory (DRAM) can adopt a low power double data rate (LPDDR) 6 standard, which can improve performance and enhance memory reliability through integrated error detection and scrub (ECS) functions. The ECS function can periodically check and scrub errors in memory data.

[0003] In actual application, the result of correcting errors in memory may be successful or unsuccessful, and therefore, how to store the result information of correcting errors in memory for analyzing errors in memory is a technical problem to be solved in the related art. SUMMARY

[0004] The embodiments of the application provide a fault information storage method and device, an electronic device and a storage medium, which can store the result information of correcting errors in memory, and can analyze errors in memory.

[0005] In a first aspect, the embodiments of the application provide a fault information storage method, which comprises: in response to a target mode register completing error detection and scrub (ECS) result recording of memory, reading first address information of memory errors or second address information of the memory errors recorded in the target mode register, wherein the first address information is address information corresponding to memory errors corrected successfully, and the second address information is address information corresponding to memory errors corrected unsuccessfully; and storing fault information corresponding to the memory errors in a nonvolatile memory, wherein the fault information comprises the first address information or the second address information, and identification information, and the identification information is used to identify whether the memory errors are corrected successfully.

[0006] In a second aspect, an embodiment of the present application provides a fault information storage apparatus, comprising: a reading module configured to read first address information of a memory error or second address information of the memory error recorded in a target mode register in response to the target mode register completing error checking and scrubbing (ECS) result recording of a memory, wherein the first address information is address information corresponding to a memory error that is successfully corrected, and the second address information is address information corresponding to a memory error that fails to be corrected; and a storage module configured to store fault information corresponding to the memory error in a nonvolatile memory, wherein the fault information comprises the first address information or the second address information, and identification information used to identify whether the memory error is successfully corrected.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the method according to the first aspect.

[0008] In a fourth aspect, an embodiment of the present application provides a readable storage medium, wherein the readable storage medium stores programs or instructions, and the programs or instructions are executed by a processor to implement the steps of the method according to the first aspect.

[0009] In a fifth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is configured to run programs or instructions to implement the method according to the first aspect.

[0010] In a sixth aspect, an embodiment of the present application provides a computer program product stored in a storage medium, and the computer program product is executed by at least one processor to implement the method according to the first aspect.

[0011] In the embodiment of the present application, after the target mode register completes error checking and scrubbing (ECS) result recording of a memory, first address information of a memory error or second address information of the memory error recorded in the target mode register is read, wherein the first address information is address information corresponding to a memory error that is successfully corrected, and the second address information is address information corresponding to a memory error that fails to be corrected, and fault information corresponding to the memory error is stored in a nonvolatile memory, wherein the fault information comprises the first address information or the second address information, and identification information used to identify whether the memory error is successfully corrected. Thus, the result information of the memory error correction can be stored in the nonvolatile memory, and the memory can be evaluated by analyzing the fault information corresponding to the memory error, so as to improve the reliability of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a flowchart of a fault information storage method provided by an embodiment of the present application; Figure 2 is a flowchart of another fault information storage method provided by an embodiment of the present application; Figure 3 is a structural schematic diagram of a fault information storage device provided by an embodiment of the present application; Figure 4 is a structural schematic diagram of another fault information storage device provided by an embodiment of the present application; Figure 5 is a structural schematic diagram of an electronic device provided by an embodiment of the present application; Figure 6 is a hardware structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0014] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually a category, and are not limited to the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in an "or" relationship.

[0015] The fault information storage scheme provided by the embodiments of the present application will be described in detail below with reference to the drawings, specific embodiments and application scenarios.

[0016] Figure 1 A flowchart of a fault information storage method provided by an embodiment of the present application is shown, the method 100 can be executed by an electronic device, which can be a terminal device, for example, a mobile phone, a tablet personal computer (Tablet Personal Computer), etc. As shown in the figure, Figure 1 The method mainly includes the following steps.

[0017] S110, in response to the ECS result of the memory being recorded in the target mode register, reading the first address information of the memory error or the second address information of the memory error recorded in the target mode register.

[0018] The first address information is address information corresponding to a memory error that is successfully corrected, and the second address information is address information corresponding to a memory error that is not successfully corrected.

[0019] In the embodiments of the present application, the host of the electronic device can enable the ECS function through the protocol-defined mode register (Mode Register, MR) configuration, and can set a scrub cycle, for example, 1 hour, or can be instructed by the host to perform the ECS action, and when the scrub cycle is reached or the host instruction is received, it can be detected whether a memory error occurs. If no error is detected, the current process ends, and if a memory error occurs, for example, abnormal memory data, the memory error is corrected. The result of the correction may be successful or unsuccessful, that is, the memory error can be divided into correct error and uncorrect error. If the memory error is successfully corrected, the target mode register records the first address information of the memory error, and if the memory error is not successfully corrected, the target mode register records the second address information of the memory error.

[0020] In some embodiments, if multiple memory errors occur, some of the memory errors may be successfully corrected, and the target mode register records the first address information corresponding to these memory errors. Another part of the memory errors may be unsuccessfully corrected, and the target mode register records the second address information corresponding to these memory errors. Alternatively, the multiple memory errors may all be successfully corrected, and the target mode register records the first address information corresponding to the multiple memory errors. Alternatively, the multiple memory errors may all be unsuccessfully corrected, and the target mode register records the second address information corresponding to the multiple memory errors.

[0021] For example, the ECS function of LPDDR6 can be used, the ECS function is enabled by setting MR111 OP[5] to 1, and the Auto ECS mode is enabled by setting MR111 OP[0] to 1 (Manual ECS function can also be enabled by setting MR111 OP[4] to 1). The Auto ECS mode is a periodic ECS action automatically performed within the specification of the protocol, and the Manual mode is an ECS action performed when a special instruction is sent by the host; the two modes can also be switched. Table 1 shows an example of the definition of MR111.

[0022] Table 1.

[0023] It should be noted that although the above describes the various MR registers taking LPDDR6 as an example, it is not limited thereto, and in actual application, with the change of the protocol, the various MR registers described above can be other numbered MR registers.

[0024] In some embodiments, the target mode register can include one or more mode registers. For example, the address information of the memory can be indicated by a storage block (Bank) and a row (Row), and the target mode register can include two mode registers, one of which can be used to record the Bank address corresponding to the address information, and the other can be used to record the Row address corresponding to the address information. Alternatively, the target mode register can include three mode registers, one of which can be used to record the Bank address corresponding to the address information, one can be used to record the high 8 bits of the Row address corresponding to the address information, and the other can be used to record the low 8 bits of the Row address corresponding to the address information.

[0025] In some embodiments, the address information corresponding to the memory error can be stored in a predetermined operand (Operand, OP, also referred to as a field) of the target mode register, and the first address information or the second address information can be obtained by reading the value of the predetermined operand.

[0026] In some embodiments, in order to facilitate differentiation, the first address information and the second address information can be recorded through different operands (Operand, OP, also referred to as fields) of the target mode register, and in these embodiments, the reading of the first address information or the second address information can be determined based on the operand recording the first address information or the second address information.

[0027] For example, in the LPDDR6 protocol, the second address information of the error correction failure can be recorded in MR113 OP[3:0], MR116 OP[7:0], and MR117 OP[7:0]; the first address information of the error correction success can be recorded in MR113 OP[3:0], MR116 OP[7:0], and MR117 OP[7:0], and the first address information and / or the second address information can be read from the corresponding fields of these registers.

[0028] Among them, the recording of the second address information can be: The OP[3:0] field of the MR113 register records the Bank[3:0] information of the correction failure address; The OP[7:0] field of the MR116 register records Row address[15:8] information of the correction failure address The OP[7:0] field of the MR117 register records Row address[7:0] information of the correction failure address The recording of the first address information can include: The OP[7:0] field of the MR113 register records Bank[3:0] information of the correction success address The OP[7:0] field of the MR115 register records Row address[7:0] information of the correction success address The OP[7:0] field of the MR114 register records Row address[15:8] information of the correction success address Combining the three addresses can generate a complete error physical address, and recording the corresponding ECS Error Flag can completely record the error address and whether the correction is successful.

[0029] The ECS Error Flag indicates whether it is an Uncorrect Error or a Correct Error, for example, MR112 OP[6] is set to 1 to indicate an Uncorrect Error, that is, a correction failure, and MR112 OP[7] is set to 1 to indicate a Correct Error, that is, a correction success. Table 2 shows some types of ECS errors.

[0030] Table 2.

[0031] Through the above embodiments, by combining the specific fields of multiple (for example, MR113, MR114, MR115, MR116, and MR117) registers, the physical address information of the error occurrence is completely restored, and accurate data support is provided for memory fault positioning.

[0032] S112, storing fault information corresponding to the memory error in the nonvolatile memory, wherein the fault information includes the first address information or the second address information corresponding to the memory error, and identification information.

[0033] The identification information is used to identify whether the memory error correction is successful.

[0034] In the embodiments of the present application, the value of the identification information can be determined based on the information recorded in the corresponding mode register, that is, identifying that the memory error correction is successful or identifying that the memory error correction fails. For example, the value of the identification information is determined by the above-mentioned ECS Error Flag.

[0035] In some embodiments, if multiple memory errors occur, some of the memory errors can be memory errors that are successfully corrected, some of the memory errors can be memory errors that are unsuccessfully corrected, all of the memory errors can be memory errors that are successfully corrected, or all of the memory errors can be memory errors that are unsuccessfully corrected. For the memory errors that are successfully corrected, the first address information corresponding to the memory errors is stored in the non-volatile memory, and the value of the identification information corresponding to the memory errors is set to a first value that identifies successful correction.

[0036] Through the above technical solution, after the target mode register completes memory error detection and ECS result recording once, the first address information of the memory error or the second address information of the memory error recorded in the target mode register is read, wherein the first address information is address information corresponding to a memory error that is successfully corrected, and the second address information is address information corresponding to a memory error that is unsuccessfully corrected. The fault information corresponding to the memory error is then stored in the non-volatile memory, so that the fault information corresponding to the memory error can be obtained from the non-volatile memory, and the memory can be evaluated by analyzing the fault information corresponding to the memory error, thereby improving the reliability of the memory.

[0037] In some embodiments, in S112, the target file can be created in the non-volatile memory, and the fault information can be stored through the target file. In these embodiments, a file for storing the fault information corresponding to the current memory error can be created after each reading of the first address information or the second address information. Through these embodiments, the fault information can be conveniently read in subsequent use.

[0038] Of course, it is not limited thereto, and in actual applications, a file can also be created in S112, and the fault information can be recorded in the pre-created file.

[0039] In some embodiments, the name of the target file can be the completion time of ECS, for example, 20250903142546.bin (2025-09-03 14:25:46). Through these embodiments, the completion time of the ECS operation can be directly reflected through the file name of the target file, and the order of occurrence of the memory errors can be reflected through the file name sorting.

[0040] Of course, it is not limited thereto, and in actual applications, other naming methods can also be used to reflect the completion time of the ECS performed on the memory error, i.e., the order of occurrence of the memory error, through the creation time of the target file.

[0041] In some embodiments, creating a target file in the non-volatile memory for storing the fault information can include: creating the target file in a preset partition of the non-volatile memory, and storing the fault information in the target file, wherein a space size of the preset partition is a fixed value. For example, a special universal flash storage (UFS) partition (e.g., Data / Log / ECS_Log) can be divided into a fixed space size (e.g., 4 MB) for storing fault information corresponding to memory errors. The files in the partition can be automatically sorted according to the creation time, and when the partition is full, the file with the earliest creation time can be automatically deleted. Through these embodiments, by dividing a fixed size of space to store fault information, it can be avoided that too much fault information is stored to cause waste of storage space.

[0042] In some embodiments, after S112, the method can further include the following steps: Step 1, based on the fault information corresponding to the memory errors stored in a preset time period, obtaining a health feature index of the memory in the preset time period.

[0043] In these embodiments, the stored fault information can be periodically read and analyzed for memory errors. For example, the host can read the files in the preset partition every 24 hours, and calculate the health feature index of the memory in the 24 hours.

[0044] Step 2, based on the health feature index of the memory in the preset time period, determining a warning level of the memory; In these embodiments, the risk level of the memory can be determined based on the health feature index of the memory in the preset time period, and the corresponding warning level can be determined.

[0045] Step 3, performing a warning operation corresponding to the determined warning level.

[0046] Through these embodiments, error information can be collected and analyzed in real time, and the transition from passive error correction to active warning can be realized, and potential memory failures can be detected in advance.

[0047] In some embodiments, the health feature index includes at least one of the following: 1) a first number of the first address information; in this embodiment, the number of addresses of correct Error recorded in the stored target file can be counted.

[0048] 2) a second number of the second address information; in this embodiment, the number of addresses of uncorrect Error recorded in the stored target file can be counted.

[0049] 3) address concentration, used to indicate the relevance of the addresses of the memory that fail in the preset time period. In this embodiment, the number of same Banks, same Rows, and adjacent Rows in the address information recorded in the target file stored in the preset time period can be counted and summed to obtain the address concentration.

[0050] For example, the memory error addresses recorded in two adjacent times (the first address information and / or the second address information) can be compared, and the value of the address concentration is increased by 1 if any of the following conditions is met: same Bank, same Row, or adjacent Row.

[0051] Through the above embodiments, the evaluation mode of single memory error count can be broken through, and the spatial dimension (address concentration) and the severity dimension (the number of correctable memory errors and uncorrectable memory errors) are used to construct a memory health evaluation model, so as to comprehensively depict the state of the memory.

[0052] In some embodiments, the warning level includes a first warning level, a second warning level, and a third warning level, the risk level corresponding to the first warning level is lower than the risk level corresponding to the second warning level, and the risk level corresponding to the second warning level is lower than the risk level corresponding to the third warning level. In these embodiments, the determination of the warning level of the memory based on the health feature indicators of the memory in the preset time period includes one of the following: The warning level is determined to be the first warning level when one of the following conditions is met: the first number is less than or equal to a first threshold, the address concentration is less than or equal to a second threshold, and the second number is less than or equal to a third threshold. The warning level is determined to be the second warning level when one of the following conditions is met: the first number is greater than or equal to a fourth threshold and less than a fifth threshold, the address concentration is greater than the second threshold and less than or equal to a sixth threshold, and the second number is greater than the third threshold and less than or equal to a seventh threshold. The warning level is determined to be the third warning level when one of the following conditions is met: the first number is greater than the fifth threshold, the address concentration is greater than the sixth threshold, and the second number is greater than the seventh threshold. Wherein, the first threshold is less than the fourth threshold, the second threshold is less than the fifth threshold, and the third threshold is less than the sixth threshold.

[0053] For example, the first threshold value can be 5, the fourth threshold value can be 20, the second threshold value can be 0, the fifth threshold value can be 1, the third threshold value can be 0, and the sixth threshold value can be 1. For example, the warning levels can be determined according to Table 3, wherein the first warning level can be a first warning level in Table 3, the second warning level can be a second warning level in Table 3, and the third warning level can be a third warning level in Table 3.

[0054] Table 3.

[0055] In some embodiments, the values of the first threshold value to the sixth threshold value can be dynamically adjusted, for example, based on the ECS scrub cycle and the memory usage scenario, to dynamically adjust the values of the first threshold value to the sixth threshold value, thereby avoiding the problem of poor adaptability of fixed threshold values and providing warning accuracy.

[0056] It should be noted that the determination of the warning level can be determined in other ways in addition to the above-mentioned threshold values, for example, a machine learning algorithm can be introduced to train a memory failure prediction model based on historical data to further improve the warning accuracy and advance.

[0057] In some embodiments, in addition to the above-mentioned three dimensions, other dimensions such as memory error frequency can be added to the judgment dimension of the warning level.

[0058] In some embodiments, the execution of the warning operation corresponding to the determined warning level comprises one of the following: 1) In the case where the warning level is the first warning level, record the failure information corresponding to the memory error and track the change trend of the memory failure; in the case of the first warning level, the system can record the failure information in the background and track the change trend without disturbing the user.

[0059] 2) In the case where the warning level is the second warning level, isolate the address where the memory error occurs; in the case of the second warning level, the address where the memory error occurs can be forcibly isolated to avoid the user from using these memories again.

[0060] 3) In the case where the warning level is the third warning level, isolate the address where the memory error occurs and output a prompt information. In the case of the third warning level, on the basis of the warning mechanism of the second warning level, a system notification interface can be called to pop up a prompt information such as “memory potential failure, please repair, backup important data”.

[0061] Through the above embodiments, proactive warning can be performed based on the warning level to advance the potential memory failure.

[0062] In some embodiments, the memory power consumption strategy can also be adjusted according to the health feature index of the memory within the preset time period, to optimize power consumption and prolong the endurance time of the mobile device under the premise of ensuring reliability.

[0063] In some embodiments, the memory error can also be counted by hardware, for example, a pin is reserved on the chip as a failure signal of memory error, when a memory error occurs, the pin is pulled high once to count the memory error by an external design digital module.

[0064] The type of the memory in the embodiments of the application can be DRAM, double data rate (DDR) 5, graphics DDR (GDDR) 6, etc.

[0065] The above technical solutions provided by the embodiments of the application will be described below taking DRAM as an example.

[0066] Figure 2 A flowchart of another fault information storage method provided by the embodiments of the application is shown in FIG. 3, which mainly includes the following steps. Figure 2 As shown in FIG. 3, the method mainly includes the following steps. S201, error information collection configuration.

[0067] The host sets to enable the ECS function, for example, the host can configure to enable the ECS function of LPDDR6 and set a suitable scrub cycle (generally set according to the hour level) through the MR register defined by the protocol, enable the ECS function by setting MR111 OP[5] to 1, and enable the Auto ECS mode by setting MR111 OP[0] to 1 (or enable the Manual ECS function by setting MR111 OP[4] to 1), the Auto mode is to automatically perform periodic ECS actions within the specification of the protocol, and the Manual mode is to perform ECS actions when the host sends a special instruction; the two modes can also be switched.

[0068] S202, detecting DRAM data anomaly and performing error correction, if the error correction fails, performing S203, if the error correction succeeds, performing S203.

[0069] When the ECS period is reached or the instruction sent by the host is received, the ECS is executed. If the execution of the ECS results in no memory error, the current flow ends. If a DRAM data error occurs, the relevant error information is recorded in the set register. Since there are two results of correction success and failure for the memory error that occurs, they are correct error for the correction success and uncorrect error for the correction failure. Therefore, when the correction fails, S203 is executed, and when the correction succeeds, S204 is executed.

[0070] In S203, the error information is collected in real time, and the address information of the correction failure is recorded in MR113 OP[3:0], MR116 OP[7:0] and MR117 OP[7:0].

[0071] The OP[3:0] field of the MR113 register records the Bank[3:0] information of the correction failure address; the OP[7:0] field of the MR116 register records the Row address[15:8] information of the correction failure address; and the OP[7:0] field of the MR117 register records the Row address[7:0] information of the correction failure address.

[0072] In S204, the error information is collected in real time, and the address information of the correction success is recorded in MR113 OP[3:0], MR116 OP[7:0] and MR117 OP[7:0].

[0073] The OP[7:4] field of the MR113 register records the Bank[3:0] information of the correction success address; the OP[7:0] field of the MR115 register records the Row address[7:0] information of the correction success address; and the OP[7:0] field of the MR114 register records the Row address[15:8] information of the correction success address.

[0074] The three addresses in the above register are combined to generate a complete error physical address. In combination with the recording of the corresponding ECSError Flag, the error address and whether the correction succeeds or fails can be recorded completely.

[0075] In S205, the error address is analyzed and stored in a file. The three addresses in the register are combined to generate a complete error physical address and recorded in the UFS.

[0076] In this step, the Bank[3:0]+Row[15:0] complete information is composed, the ECSError Flag corresponding to each address is recorded, the file is generated according to the completion time, the file is named according to the occurrence time, for example, 20250903142546.bin (2025-09-03 14:25:46), and is stored in a special UFS partition (such as Data / Log / ECS_Log). The partition is divided into a fixed space size (such as 4MB), the partition automatically sorts the files according to the creation time, and the partition automatically deletes the file with the earliest creation time when full S206, calculation of multi-dimensional health feature indicators.

[0077] The host can read the file in the partition every 24 hours and calculate the health feature indicators.

[0078] The health feature indicators can include at least one of the following: Number of error correction failure addresses: count the number of Uncorrect Error addresses in the file; Number of error correction success addresses: count the number of Correct Error addresses in the file, and Address aggregation degree: same Bank, same Row, adjacent Row number statistics, sum.

[0079] S207, dynamic early warning evaluation.

[0080] In combination with the ECS scrub cycle and the memory usage scenario, the memory health risk level and the corresponding early warning level are evaluated according to the health feature indicators. Specifically, the evaluation can be performed according to Table 3 above, which will not be repeated here.

[0081] S208, hierarchical early warning.

[0082] In this step, the corresponding early warning operation can be performed according to the early warning level, and the error information and early warning result are recorded for subsequent analysis.

[0083] The specific early warning strategy can be: First-level early warning: the system background records fault information and tracks the change trend (without disturbing the user); Second-level early warning: the addresses with errors are forcibly isolated to avoid being used again by the user; Third-level early warning: on the basis of the second-level early warning mechanism, the system notification interface is called to pop up "potential memory failure, please repair, backup important data".

[0084] By the above technical solutions provided by the embodiments of the present application, the error address information recorded in the MR113, MR114, MR115, MR117, and MR116 registers is parsed based on the LPDDR6 protocol specification, so that the memory fault position can be accurately located, accurate guidance for maintenance and replacement is provided, potential faults can be found 1-3 months before the fatal error of the memory occurs, sufficient processing time is reserved for the user, the risk of data loss is reduced, and the early warning reliability can be improved through multi-dimensional evaluation. Moreover, by using the above scheme, the ECS function and register resources of the LPDDR6 protocol can be used without increasing additional hardware cost, and the scheme is easy to popularize and apply. Through automatic collection, analysis, and early warning of error information, the burden of manual management is reduced, and the efficiency of memory reliability management is improved.

[0085] The fault information storage method provided by the embodiments of the present application can be executed by the fault information storage device. In the embodiments of the present application, the fault information storage device is taken as an example to illustrate the fault information storage device provided by the embodiments of the present application.

[0086] Figure 3 The structure of the fault information storage device provided by the embodiments of the present application is shown in a structure diagram, as shown in Figure 3 The device mainly includes a reading module 301 and a storage module 302. The reading module 301 is configured to read first address information of a memory error or second address information of the memory error recorded in a target mode register in response to completion of error detection and scrubbing ECS results of the memory of the target mode register, where the first address information is address information corresponding to a memory error that is successfully corrected, and the second address information is address information corresponding to a memory error that fails to be corrected. The storage module 302 is configured to store fault information corresponding to the memory error in a nonvolatile memory, where the fault information includes the first address information or the second address information, and identification information, and the identification information is used to identify whether the memory error correction is successful.

[0087] In some embodiments, the storage module 302 stores the fault information corresponding to the memory error in the nonvolatile memory, including: A target file is created in the nonvolatile memory, and the fault information is stored through the target file.

[0088] In some embodiments, the name of the target file is the completion time of the ECS.

[0089] In some embodiments, the storage module 302 creates a target file in the nonvolatile memory, and stores the fault information through the target file, including: create the target file in a preset partition of the nonvolatile memory, and store the fault information through the target file, wherein a space size of the preset partition is a fixed value.

[0090] In some embodiments, as shown in FIG. 3, the apparatus can further include: Figure 4 The acquisition module 303 is configured to acquire a health feature index of the memory in a preset time period based on fault information of the memory errors stored in the preset time period. The determination module 304 is configured to determine a warning level of the memory based on the health feature index of the memory in the preset time period. The execution module 305 is configured to perform a warning operation corresponding to the determined warning level.

[0091] In some embodiments, the health feature index includes at least one of the following: a first quantity of the first address information; a second quantity of the second address information; an address aggregation degree, used to indicate a correlation of addresses of the memory that have failed in the preset time period.

[0092] In some embodiments, the warning level includes a first warning level, a second warning level, and a third warning level, a risk level corresponding to the first warning level is lower than a risk level corresponding to the second warning level, and the risk level corresponding to the second warning level is lower than a risk level corresponding to the third warning level; the determination module 304 determines the warning level of the memory based on the health feature index of the memory in the preset time period, including one of the following: determines the warning level as the first warning level when one of the following conditions is met: the first quantity is less than or equal to a first threshold, the address aggregation degree is less than or equal to a second threshold, and the second quantity is less than or equal to a third threshold; determines the warning level as the second warning level when one of the following conditions is met: the first quantity is greater than the first threshold and less than a fourth threshold, the address aggregation degree is greater than the second threshold and less than or equal to a fifth threshold, and the second quantity is greater than the third threshold and less than or equal to a sixth threshold; determines the warning level as the third warning level when one of the following conditions is met: the first quantity is greater than or equal to the fourth threshold, the address aggregation degree is greater than the fifth threshold, and the second quantity is greater than a seventh threshold; wherein the first threshold is less than the fourth threshold, the second threshold is less than the fifth threshold, and the third threshold is less than the sixth threshold. ​

[0093] In some embodiments, the execution module 306 performs a warning operation corresponding to the determined warning level, including one of the following: In a case where the warning level is a first warning level, recording failure information corresponding to the memory error and tracking a change trend of the memory failure; In a case where the warning level is a second warning level, isolating an address where the memory error occurs; In a case where the warning level is a third warning level, isolating an address where the memory error occurs and outputting prompt information.

[0094] The failure information storage apparatus in the embodiments of the present application can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc., and the embodiments of the present application are not limited in this regard.

[0095] The failure information storage apparatus in the embodiments of the present application can be a device with an operating system. The operating system can be an Android operating system, an ios operating system, or other possible operating systems, and the embodiments of the present application are not limited in this regard.

[0096] The failure information storage apparatus provided in the embodiments of the present application can implement each process of the method embodiments and has the same effect, and thus the details are not described herein again. Figures 1 to 2 The method embodiments implement each process and have the same effect, and thus the details are not described herein again.

[0097] Optionally, as shown in Figure 5 The embodiments of the present application further provide an electronic device 500, including a processor 501 and a memory 502, and the memory 502 stores programs or instructions executable on the processor 501. The programs or instructions are executed by the processor 501 to implement each step of the above failure information storage method embodiments and achieve the same technical effects, and thus the details are not described herein again.

[0098] It should be noted that the electronic device in the embodiments of the present application includes the mobile electronic device and the non-mobile electronic device described above.

[0099] Figure 6 A hardware structure schematic diagram of an electronic device according to an embodiment of the present application. The electronic device 600 includes, but is not limited to, a radio frequency unit 601, a network module 602, an audio output unit 603, an input unit 604, a sensor 605, a display unit 606, a user input unit 607, an interface unit 608, a memory 609, and a processor 610, etc.

[0100] Those skilled in the art can understand that the electronic device 600 can also include a power supply (such as a battery) for supplying power to each component, and the power supply can be logically connected to the processor 610 through a power management system, so as to realize the functions of managing charging, discharging, and power consumption management through the power management system. Figure 6 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and the electronic device can include more or fewer components than the figure, or combine certain components, or different component arrangements, which are not described here. The processor 610 is configured to: In response to the target mode register completing the error detection and scrubbing ECS result recording of the memory, reading the first address information of the memory error or the second address information of the memory error recorded in the target mode register, wherein the first address information is the address information corresponding to the memory error that is successfully corrected, and the second address information is the address information corresponding to the memory error that fails to be corrected; Storing the fault information corresponding to the memory error in the non-volatile memory, wherein the fault information includes the first address information or the second address information, and identification information, and the identification information is used to identify whether the memory error correction is successful.

[0101] The processor 610 is further configured to: Based on the fault information of the memory error stored in the preset time period, obtaining a health feature index of the memory in the preset time period; Based on the health feature index of the memory in the preset time period, determining a warning level of the memory; Performing a warning operation corresponding to the determined warning level.

[0102] It should be understood that in the embodiments of the present application, the input unit 604 can include a graphics processor (GPU) 6041 and a microphone 6042. The graphics processor 6041 processes image data of a still picture or a video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 606 can include a display panel 6061, which can be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 607 includes at least one of a touch panel 6071 and other input devices 6072. The touch panel 6071 is also referred to as a touch screen. The touch panel 6071 can include two parts of a touch detection device and a touch controller. The other input devices 6072 can include, but are not limited to, a physical keyboard, function keys (such as volume control keys, on-off keys, and the like), a trackball, a mouse, a joystick, and the like, which will not be described here.

[0103] The memory 609 can be used to store software programs and various data. The memory 609 can mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area can store an operating system, application programs or instructions required by at least one function (such as a sound playing function, an image playing function, and the like), and the like. In addition, the memory 609 can include a volatile memory or a non-volatile memory, or the memory 609 can include both volatile and non-volatile memories. The non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synch link dynamic random access memory (SLDRAM), and a direct memory bus random access memory (DRRAM). The memory 609 in the embodiments of the present application includes but is not limited to these and any other suitable types of memory.

[0104] The processor 610 can include one or more processing units; optionally, the processor 610 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and an application program, and the modem processor mainly processes a wireless communication signal, such as a baseband processor. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 610.

[0105] The embodiment of the present application further provides a readable storage medium, and the readable storage medium stores a program or instructions, the program or instructions are executed by a processor to realize each process of the above-mentioned fault information storage method embodiment, and the same technical effects can be achieved, and details are not repeated here.

[0106] The processor is the processor in the electronic device in the above-mentioned embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0107] The embodiment of the present application further provides a chip, and the chip includes a processor and a communication interface, the communication interface is coupled with the processor, and the processor is used to run a program or instructions to realize each process of the above-mentioned fault information storage method embodiment, and the same technical effects can be achieved, and details are not repeated here.

[0108] It should be understood that the chip mentioned in the embodiment of the present application can also be referred to as a system-level chip, a system chip, a chip system, or a system-on-chip chip, etc.

[0109] The embodiment of the present application provides a computer program product, and the program product is stored in a storage medium, and the program product is executed by at least one processor to realize each process of the above-mentioned fault information storage method embodiment, and the same technical effects can be achieved, and details are not repeated here.

[0110] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. Furthermore, it is to be understood that the method and apparatus of the present embodiments can be carried out by means of software consisting of code portions stored in a memory and executed by a processor, or by a combination of software and hardware. Moreover, the scope of the present embodiments is not intended to be limited to the particular embodiments of the process, method, article, or apparatus specifically described in the specification and drawings of the present document as such may vary. In other words, those skilled in the art will appreciate that the application is capable of additional embodiments and whose details are around those given in the description above.

[0111] From the above description of the embodiments, it is apparent that the above-described method of the embodiments can be implemented by means of software and the necessary universal hardware platform, of course, can also be implemented by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a computer software product in essence or in the form of a part of the prior art that makes a contribution, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk) and includes a number of instructions for causing a terminal (which can be a mobile phone, a computer, a server, or a network device) to execute the method described in each embodiment of the present application.

[0112] The embodiments of the present application are described above in conjunction with the drawings, but the present application is not limited to the above-described specific embodiments, which are merely illustrative rather than restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the protection scope of the claims.

Claims

1. A failure information storage method characterized by comprising: The method comprises: In response to completion of error detection and scrubbing ECS of a memory, reading first address information of a memory error or second address information of the memory error recorded in a target mode register, wherein the first address information is address information corresponding to a memory error that is successfully corrected, and the second address information is address information corresponding to a memory error that is unsuccessfully corrected; Storing fault information corresponding to the memory error in a nonvolatile memory, wherein the fault information comprises the first address information or the second address information, and identification information for identifying whether the memory error is successfully corrected.

2. The method of claim 1, wherein, The storing of the fault information corresponding to the memory error in the nonvolatile memory comprises: Creating a target file in the nonvolatile memory, and storing the fault information in the target file.

3. The method of claim 2, wherein, The name of the target file is the completion time of the ECS.

4. The method of claim 2, wherein, The creating of the target file in the nonvolatile memory and the storing of the fault information in the target file comprise: Creating the target file in a preset partition of the nonvolatile memory, and storing the fault information in the target file, wherein the space size of the preset partition is a fixed value.

5. The method according to any one of claims 1 to 4, characterized in that, After storing the fault information corresponding to the memory error in the nonvolatile memory, the method further comprises: Obtaining a health feature index of the memory in a preset time period based on the fault information corresponding to the memory error stored in the preset time period; Determining a warning level of the memory based on the health feature index of the memory in the preset time period; Performing a warning operation corresponding to the determined warning level.

6. The method of claim 5, wherein, The health feature index comprises at least one of: A first number of the first address information; A second number of the second address information; An address aggregation degree for indicating the relevance of addresses of the memory that have failed in the preset time period.

7. The method of claim 6, wherein: The warning level comprises a first warning level, a second warning level, and a third warning level, wherein a risk level corresponding to the first warning level is lower than a risk level corresponding to the second warning level, and the risk level corresponding to the second warning level is lower than a risk level corresponding to the third warning level; The determining of the warning level of the memory based on the health feature index of the memory in the preset time period comprises one of: Determining the warning level as the first warning level when one of the following conditions is met: the first number is less than or equal to a first threshold, the address aggregation degree is less than or equal to a second threshold, and the second number is less than or equal to a third threshold; Determining the warning level as the second warning level when one of the following conditions is met: the first number is greater than the first threshold and less than a fourth threshold, the address aggregation degree is greater than the second threshold and less than or equal to a fifth threshold, and the second number is greater than the third threshold and less than or equal to a sixth threshold; and The third warning level is determined when one of the following conditions is met: the first quantity is greater than or equal to the fourth threshold value, the address concentration is greater than the fifth threshold value, and the second quantity is greater than the seventh threshold value. The first threshold value is less than the fourth threshold value, the second threshold value is less than the fifth threshold value, and the third threshold value is less than the sixth threshold value.

8. The method of claim 5, wherein, The execution of the warning operation corresponding to the determined warning level includes one of the following: When the warning level is the first warning level, record the fault information corresponding to the memory error and track the change trend of the memory failure; When the warning level is the second warning level, isolate the address where the memory error occurs; When the warning level is the third warning level, isolate the address where the memory error occurs and output a prompt information.

9. A failure information storage device, characterized by comprising: The method comprises: The reading module reads the first address information where the memory error occurs or the second address information where the memory error occurs recorded in the target mode register in response to the completion of the error detection and scrubbing (ECS) result recording of the target memory. The storage module stores the fault information corresponding to the memory error in the non-volatile memory, wherein the fault information includes the first address information or the second address information, and identification information, and the identification information is used to identify whether the memory error correction is successful.

10. An electronic device, comprising: The processor and the memory are included, the memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the fault information storage method according to any one of claims 1 to 8.

11. A readable storage medium, characterized by, The readable storage medium stores programs or instructions, and the programs or instructions are executed by the processor to implement the steps of the fault information storage method according to any one of claims 1 to 8.

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