Semiconductor structure for wafer bonding and method for improving wafer bonding alignment

Abstract

The invention discloses a semiconductor structure for wafer bonding and a method for improving wafer bonding alignment. The bonding mark of the semiconductor structure comprises a contrast enhancement layer and a first dielectric layer which are stacked in sequence, and the light reflectivity of the contrast enhancement layer is higher than that of the first dielectric layer. According to the method, accurate alignment and bonding of the wafer are realized by using the high-contrast bonding mark structure. By introducing the contrast enhancement layer with high reflectivity, such as a silicon nitride layer, into the bonding mark, the optical contrast of the mark is remarkably improved, so that the recognition precision of bonding equipment is improved, the alignment error is reduced, the subsequent process risk is reduced, and the product yield is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure for wafer bonding and a method for improving wafer bonding alignment. BACKGROUND

[0002] Backside illuminated image sensor (BSI) is a key device in current high-performance imaging technology. Unlike the traditional front-side illuminated (FSI) sensor, the design of BSI sensor places the light-sensing elements such as photodiodes on the backside of the chip substrate, so that the incident light can reach the light-sensing area without passing through the metal wiring layer, thereby avoiding the obstruction and interference of the circuit layer to the light, significantly improving the quantum efficiency and imaging performance under low light conditions.

[0003] The manufacturing process flow of BSI sensor is relatively complex, and one of the core and challenging processes is wafer bonding. This process requires two pieces of separately processed wafers (e.g., one containing a light-sensing array and the other containing a readout circuit) to be permanently combined together through bonding technology. The alignment accuracy of the two wafers directly determines the final yield, performance and long-term reliability of the BSI product.

[0004] In the wafer bonding process, high-precision bonding equipment (e.g., a bonder) is usually used to achieve alignment by recognizing the bonding marks provided on the surfaces of the two wafers. Ideally, the alignment error needs to be controlled at the nanometer level. However, in actual production process, the recognition ability of the bonding equipment on the bonding marks can be affected by various factors, such as the shape, size and film layer structure of the marks. When there is a deviation in the recognition of the bonding marks by the equipment, it will cause the position deviation of the two wafers after bonding, resulting in the inaccurate alignment of the upper and lower circuits. This alignment error not only can cause the device to fail, but also can cause cracks at the wafer edge due to stress concentration in the subsequent wafer thinning process, and even cause the entire wafer to be scrapped, thereby causing huge economic losses.

[0005] In the prior art, the bonding marks are usually composed of conventional dielectric materials such as silicon dioxide (SiO2), which have insufficient difference in optical properties (such as reflectivity) from the surrounding area materials, resulting in low signal contrast generated by the optical recognition system. This low contrast makes it easy for the bonding equipment to make errors in identifying the exact position of the marks, and it is difficult to meet the increasingly stringent nanometer-level alignment requirements.

[0006] Therefore, there is an urgent need in the industry for a new method that can improve the recognition accuracy of the bonding marks and the alignment effect of the wafer bonding, in order to improve the manufacturing yield and reliability of products such as BSI. SUMMARY

[0007] The technical problem to be solved by the present application is that the wafer bonding mark in the prior art has a low contrast ratio when recognized by a bonding device, and is prone to recognition deviation, thereby affecting the alignment accuracy of wafer bonding and possibly causing yield loss in subsequent processes, because the difference in optical properties between the material constituting the wafer bonding mark and the surrounding area is not significant.

[0008] To achieve the above object and other related objects, the present application provides a semiconductor structure for wafer bonding and a method for improving wafer bonding alignment, which aims to improve the optical contrast ratio of the bonding mark by optimizing the film layer structure of the bonding mark, thereby improving the accuracy and reliability of bonding alignment.

[0009] In one aspect, the present application provides a semiconductor structure for wafer bonding, comprising:

[0010] a substrate; and

[0011] a bonding mark structure disposed on the substrate, the bonding mark structure being a groove structure formed by patterned etching of a contrast-enhancing layer and a first dielectric layer stacked in sequence;

[0012] wherein the light reflectivity of the contrast-enhancing layer is higher than that of the first dielectric layer.

[0013] Preferably, a second dielectric layer is further included between the substrate and the contrast-enhancing layer.

[0014] Preferably, the bonding mark structure comprises a cross-shaped pattern and / or a frame-shaped pattern.

[0015] Preferably, the contrast-enhancing layer is a silicon nitride layer.

[0016] Preferably, the first dielectric layer is a silicon oxide layer.

[0017] Preferably, the second dielectric layer is a silicon oxide layer.

[0018] Preferably, the thickness of the silicon nitride layer is 10-100 nm.

[0019] In another aspect, the present application provides a method for improving wafer bonding alignment, comprising the following steps:

[0020] Step 1: forming the bonding mark structure as described in any one of the preceding embodiments on the substrate of a first wafer;

[0021] Step 2: recognizing the bonding mark structure by a bonding device to align the first wafer with a second wafer;

[0022] Step 3: bonding the aligned first wafer and the second wafer.

[0023] Preferably, in step one, a second dielectric layer is further formed between the substrate and the contrast-enhancing layer.

[0024] Preferably, in step one, the forming of the bonding mark structure comprises:

[0025] The contrast-enhancing layer and the first dielectric layer are subjected to a photolithography process and an etching process to expose part of the substrate, thereby forming the bonding mark structure.

[0026] Preferably, in step one, the bonding mark structure comprises a cross-shaped pattern and / or a frame-shaped pattern.

[0027] Preferably, the contrast-enhancing layer is a silicon nitride layer.

[0028] Preferably, the first dielectric layer is a silicon oxide layer.

[0029] Preferably, the second dielectric layer is a silicon oxide layer.

[0030] Preferably, the forming of the silicon nitride layer comprises deposition by a plasma-enhanced chemical vapor deposition process.

[0031] Preferably, the plasma-enhanced chemical vapor deposition process is performed at a temperature of 380-420℃ and a pressure of 1.8-2.0MPa.

[0032] Preferably, the plasma-enhanced chemical vapor deposition process employs high-frequency power and low-frequency power, the high-frequency power being 900-950W and the low-frequency power being 350-410W.

[0033] Preferably, the deposition time of the plasma-enhanced chemical vapor deposition process is 6-7 seconds.

[0034] Preferably, the thickness of the silicon nitride layer is 50-100nm.

[0035] As described above, the semiconductor structure for wafer bonding and the method for improving wafer bonding alignment of the present application have the following beneficial effects:

[0036] 1. The present application effectively enhances the optical contrast between the mark pattern and the surrounding area by introducing a contrast-enhancing layer (such as silicon nitride) with significant light reflectivity difference from the dielectric layer in the bonding mark structure, so that the machine vision system of the bonding equipment can more accurately and reliably identify the mark position.

[0037] 2. Due to the improvement of mark identification accuracy, the alignment error of the two wafers in the bonding process is effectively controlled, and the translation error in X and Y directions is significantly reduced, thereby ensuring the accurate alignment of the upper and lower circuits.

[0038] 3. Precise wafer bonding alignment, reducing the risk of wafer edge cracking due to stress concentration in subsequent thinning process, avoiding the problem of device functional failure due to circuit mispositioning, ultimately helping to improve the overall manufacturing yield and reliability of back-illuminated image sensors and other products. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A cross-sectional schematic view of a semiconductor structure according to an embodiment of the present application;

[0040] Figure 2 A top view schematic diagram of a bonding mark structure according to an embodiment of the present application;

[0041] Figure 3 A flowchart schematic diagram of a method for improving wafer bonding alignment according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The embodiments of the present application will be described in detail with specific reference to particular examples, but it will be understood that the present application is not limited to these examples. Other advantages and effects of the present application will be understood by those skilled in the art from the contents disclosed in the present specification. The present application can also be implemented or applied in other different embodiments, and the details in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0043] Referring to Figure 1 , the present application provides a semiconductor structure for wafer bonding, comprising a substrate 101 and a bonding mark structure disposed on the substrate 101. The substrate 101 is usually a silicon (Si) substrate, but the present application is not limited thereto. Those skilled in the art can understand that the substrate 101 can also be other types of semiconductor substrates, such as but not limited to germanium (Ge) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, or silicon-on-insulator (SOI) substrate, etc. The bonding mark structure is a groove structure formed by patterned etching of the contrast-enhanced layer 102 and the first dielectric layer 103 stacked in sequence.

[0044] In some embodiments, referring to Figure 2 , the bonding mark structure includes a cross-shaped pattern and / or a frame-shaped pattern. These specific geometric shapes have clear edges and symmetry centers, which are beneficial for high-precision positioning and alignment calculation by the optical recognition system, thereby improving the accuracy of recognition.

[0045] In some embodiments, a second dielectric layer (not shown) is also included between the substrate 101 and the contrast enhancement layer 102, forming a more stable and common sandwich structure of dielectric layer-contrast enhancement layer-dielectric layer. This structure can effectively buffer the stress between the substrate 101 and the contrast enhancement layer 102, and provide better interface quality, which helps to improve the long-term reliability of the device.

[0046] In some embodiments, the contrast enhancement layer 102 is a silicon nitride (Si3N4) layer. However, the scope of the present application is not limited thereto, and the contrast enhancement layer 102 can be any material that can form a significant optical property difference (e.g., reflectivity or refractive index difference) with the adjacent dielectric layer. Alternative materials include, but are not limited to, amorphous silicon (a-Si), titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiO2), or other high refractive index dielectric materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or aluminum oxide (Al2O3), etc. The basis for selecting these materials is that they can provide a high-contrast optical signal for the alignment system of the bonding equipment. In embodiments of the present application, silicon nitride has a stronger refractive ability for light due to its dense crystal structure and polar Si-N bond, and its light reflectivity can reach 10-15%, which is significantly higher than that of conventional dielectric materials.

[0047] In some embodiments, the first dielectric layer 103 is a silicon oxide (SiO2) layer. It should be understood that the material of the first dielectric layer 103 is also not limited to silicon oxide. For example, it can also be other dielectric materials with lower refractive index at the working wavelength, including but not limited to silicon oxynitride (SiON), phosphorus-doped silicate glass (PSG), boron-doped phosphorus silicate glass (BPSG), or certain low dielectric constant (low-k) materials, as long as it can form sufficient optical contrast with the contrast enhancement layer 102. Silicon oxide, as a mature dielectric material, has good insulating properties and process compatibility, and its light reflectivity is usually in the range of 3-5%, forming a distinct optical contrast with the silicon nitride layer. The light reflectivity of the contrast enhancement layer 102 is higher than that of the first dielectric layer 103. This significant reflectivity difference allows the optical system of the bonding equipment to receive a higher-contrast signal image when identifying the bonding mark, thereby effectively reducing the identification error rate and improving the accuracy and reliability of the alignment.

[0048] In some embodiments, the second dielectric layer is a silicon oxide layer. Similarly, the material of the second dielectric layer can also be other alternative dielectric materials described above for the first dielectric layer 103.

[0049] In some embodiments, the thickness of the silicon nitride layer is For example, it can be The thickness range is optimized to ensure sufficient reflectivity enhancement without introducing excessive film stress or significantly increasing process cost.

[0050] Referring to Figure 3 The present application also provides a method for improving wafer bonding alignment, comprising the following steps:

[0051] Step one, forming the bonding mark structure as described in any of the preceding embodiments on the substrate 101 of the first wafer.

[0052] In some embodiments, a second dielectric layer is also formed between the substrate 101 and the contrast-enhancing layer 102 in step one.

[0053] In some embodiments, the forming of the bonding mark structure in step one comprises: performing photolithography and etching processes on the contrast-enhancing layer 102 and the first dielectric layer 103 to expose part of the substrate 101, thereby forming the bonding mark structure.

[0054] In some embodiments, the bonding mark structure in step one comprises a cross-shaped pattern and / or a frame-shaped pattern.

[0055] In some embodiments, the contrast-enhancing layer 102 in step one is a silicon nitride layer. Similarly, the method of the present application is not limited to forming a silicon nitride layer, and other types of contrast-enhancing layer 102 can also be formed in step one, such as but not limited to amorphous silicon, titanium nitride, tantalum nitride, titanium oxide, or other high-refractive-index dielectric materials such as hafnium oxide, zirconium oxide, or aluminum oxide, etc.

[0056] In some embodiments, the first dielectric layer 103 in step one is a silicon oxide layer. Similarly, the first dielectric layer 103 formed in step one is not limited to a silicon oxide layer, and can be other low-refractive-index dielectric materials, including but not limited to silicon oxynitride, phosphorus-doped silicate glass, boron-doped phosphorus silicate glass, or low-dielectric-constant materials.

[0057] In some embodiments, the second dielectric layer in step one is a silicon oxide layer. Similarly, the material of the second dielectric layer formed in this step can also be other alternative dielectric materials as described above for the first dielectric layer 103.

[0058] In some embodiments, the forming of the silicon nitride layer in step one comprises deposition by a plasma-enhanced chemical vapor deposition process.

[0059] In some embodiments, the plasma-enhanced chemical vapor deposition process in step one is performed at a temperature of 380-420℃ and a pressure of 1.8-2.0 MPa. In a specific embodiment, the temperature is 400℃ and the pressure is 1.9 MPa.

[0060] In some embodiments, in step one, the plasma enhanced chemical vapor deposition process employs high frequency power and low frequency power, the high frequency power is 900-950 W, and the low frequency power is 350-410 W. For example, the high frequency power can be 920 W, and the low frequency power can be 380 W.

[0061] In some embodiments, in step one, the deposition time of the plasma enhanced chemical vapor deposition process is 6-7 seconds.

[0062] In some embodiments, in step one, the thickness of the silicon nitride layer is 100-200 nm. For example, it can be 150 nm.

[0063] Step two, identify the bonding mark structure by using a bonding equipment to align the first wafer and the second wafer.

[0064] This step is usually performed in a high-precision wafer bonding equipment. The equipment is equipped with an advanced machine vision system, which includes a light source, one or more high-resolution cameras (such as CCD or CMOS cameras), and an image processing unit. During the alignment process, the first wafer and the second wafer are placed on movable stages in the equipment, respectively. The light source (such as visible light or infrared light) irradiates on the bonding marks of the two wafers. In particular, when one of the wafers is an opaque silicon wafer, an infrared (IR) light source is usually used, which takes advantage of the transmission of infrared light by silicon, so that the camera can capture the bonding mark images of the upper wafer and the lower wafer at the same time. After the image processing unit receives the images captured by the camera, it accurately identifies the center position and edge contour of the bonding mark through algorithms. Due to the high contrast of the bonding mark in the present application, these algorithms can complete the identification more quickly and accurately, reducing the interference of background noise. Subsequently, the system calculates the translation deviation and rotation deviation between the two wafers in the X-axis and Y-axis directions. According to the calculated deviation values, the system drives a high-precision stage (such as a stage driven by piezoelectric ceramics) with nanometer-level movement precision to fine-tune the position of one or both wafers until the bonding marks on the two wafers are accurately overlapped, so that the alignment error is controlled within the preset process tolerance.

[0065] Step three, bond the aligned first wafer and the second wafer.

[0066] After the precise alignment is completed, the bonding equipment slowly brings the bonding surfaces of the two wafers into physical contact in a highly controlled environment, such as a vacuum or a specific inert gas atmosphere. This controlled environment prevents particulate contaminants from being trapped between the bonding interface, thus avoiding the formation of bonding voids. Depending on the specific application requirements, the bonding process can take on various forms. One common form is direct bonding (also known as fusion bonding), which involves bringing two highly clean and flat surfaces into contact with each other at room temperature, forming an initial weak bond (also known as pre-bonding) through van der Waals forces. Subsequently, the wafer pair is subjected to a thermal annealing process (e.g., at a temperature of 200-400°C) to promote the formation of stronger covalent bonds (e.g., Si-O-Si bonds) at the bonding interface, thus achieving a permanent and strong bond. Another advanced form is hybrid bonding, which allows the simultaneous bonding of dielectric materials (e.g., silicon oxide) and metal pads (e.g., copper) on the bonding interface, thus achieving structural connection while forming high-density three-dimensional electrical interconnections. Regardless of the bonding method used, a structurally complete and reliably connected bonded wafer pair is ultimately formed, preparing for subsequent wafer thinning, backside processing, and other processes.

[0067] By introducing a high-reflectivity silicon nitride layer into the film layer structure of the bonding mark, the optical contrast between the bonding mark and the adjacent area is effectively enhanced. The actual test results show that after the process is improved, the recognition failure rate of the bonding machine to the mark is reduced by 16.3%, and the maximum translation error in the X direction is reduced by 78 nm, and the maximum translation error in the Y direction is reduced by 50 nm. This directly improves the alignment accuracy of wafer bonding, reduces the offset after wafer bonding, and provides protection for subsequent thinning and other process steps, reduces the risk of wafer edge cracking or device functional failure caused by poor alignment, and ultimately helps to improve the overall yield and reliability of back-illuminated image sensors and other products.

[0068] It should be noted that the diagrams provided in the embodiments only illustrate the basic concepts of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in terms of type, number and proportion, and the component layout pattern may also be more complex.

[0069] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A semiconductor structure for wafer bonding, characterized by, The application relates to a bonding mark structure, comprising: a substrate; and a bonding mark structure arranged on the substrate, the bonding mark structure being a groove structure formed by patterned etching of a contrast-enhancing layer and a first dielectric layer stacked in sequence; wherein the light reflectivity of the contrast-enhancing layer is higher than that of the first dielectric layer.

2. The semiconductor structure for wafer bonding of claim 1, wherein: A second dielectric layer is further included between the substrate and the contrast-enhancing layer.

3. The semiconductor structure for wafer bonding of claim 1, wherein: The bonding mark structure comprises a cross-shaped pattern and / or a frame-shaped pattern.

4. The semiconductor structure for wafer bonding according to claim 1 or 2, wherein: The contrast-enhancing layer is a silicon nitride layer.

5. The semiconductor structure for wafer bonding of claim 1 or 2, wherein: The first dielectric layer is a silicon oxide layer.

6. The semiconductor structure for wafer bonding of claim 2, wherein: The second dielectric layer is a silicon oxide layer.

7. The semiconductor structure for wafer bonding of claim 4, wherein: The thickness of the silicon nitride layer is 8. A method of improving wafer bonding alignment, comprising: The application further relates to a bonding mark structure manufacturing method, comprising: Step 1: forming the bonding mark structure as claimed in any one of claims 1 to 7 on a substrate of a first wafer; Step 2: identifying the bonding mark structure by using a bonding device to align the first wafer with a second wafer; Step 3: bonding the aligned first wafer and the second wafer.

9. The method of claim 8, wherein: In Step 1, a second dielectric layer is further formed between the substrate and the contrast-enhancing layer.

10. The method of improving wafer bonding alignment of claim 8, wherein: In Step 1, the formation of the bonding mark structure comprises: performing a photoetching process and an etching process on the contrast-enhancing layer and the first dielectric layer to expose part of the substrate, thereby forming the bonding mark structure.

11. The method of improving wafer bonding alignment of claim 10, wherein: In Step 1, the bonding mark structure comprises a cross-shaped pattern and / or a frame-shaped pattern.

12. The method of improving wafer bonding alignment of claim 8 or 9, wherein: The contrast-enhancing layer is a silicon nitride layer.

13. The method of improving wafer bonding alignment of claim 8 or 9, wherein: The first dielectric layer is a silicon oxide layer.

14. The method of improving wafer bonding alignment of claim 9, wherein: The second dielectric layer is a silicon oxide layer.

15. The method of improving wafer bonding alignment of claim 12, wherein: In Step 1, the formation of the silicon nitride layer comprises deposition by a plasma-enhanced chemical vapor deposition process.

16. The method of improving wafer bonding alignment of claim 15, wherein: In Step 1, the plasma-enhanced chemical vapor deposition process is performed at a temperature of 380-420 DEG C and a pressure of 1.8-2.0 MPa.

17. The method of improving wafer bonding alignment of claim 16, wherein: In Step 1, the plasma-enhanced chemical vapor deposition process adopts high-frequency power and low-frequency power, wherein the high-frequency power is 900-950 W and the low-frequency power is 350-410 W.

18. The method of improving wafer bonding alignment of claim 17, wherein: In Step 1, the deposition time of the plasma-enhanced chemical vapor deposition process is 6-7 seconds.

19. The method of improving wafer bonding alignment of claim 12, wherein: In step one, the thickness of the silicon nitride layer is

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